drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_errata.h>
  14 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  15 #include <asm/arch/clock.h>
  16 #endif
  17
  18 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  19         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  20 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  21 {
  22         int timeout = 1000;
  23
  24         ddr_out32(ptr, value);
  25
  26         while (ddr_in32(ptr) & bits) {
  27                 udelay(100);
  28                 timeout--;
  29         }
  30         if (timeout <= 0)
  31                 puts("Error: wait for clear timeout.\n");
  32 }
  33 #endif
  34
  35 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  36 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  37 #endif
  38
  39 /*
  40  * regs has the to-be-set values for DDR controller registers
  41  * ctrl_num is the DDR controller number
  42  * step: 0 goes through the initialization in one pass
  43  *       1 sets registers and returns before enabling controller
  44  *       2 resumes from step 1 and continues to initialize
  45  * Dividing the initialization to two steps to deassert DDR reset signal
  46  * to comply with JEDEC specs for RDIMMs.
  47  */
  48 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  49                              unsigned int ctrl_num, int step)
  50 {
  51         unsigned int i, bus_width;
  52         struct ccsr_ddr __iomem *ddr;
  53         u32 temp32;
  54         u32 total_gb_size_per_controller;
  55         int timeout;
  56
  57 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  58         u32 mr6;
  59         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  60         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  61         u32 *vref_seq = vref_seq1;
  62 #endif
  63 #ifdef CONFIG_FSL_DDR_BIST
  64         u32 mtcr, err_detect, err_sbe;
  65         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  66 #endif
  67 #ifdef CONFIG_FSL_DDR_BIST
  68         char buffer[CONFIG_SYS_CBSIZE];
  69 #endif
  70         switch (ctrl_num) {
  71         case 0:
  72                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  73                 break;
  74 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  75         case 1:
  76                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  77                 break;
  78 #endif
  79 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  80         case 2:
  81                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  82                 break;
  83 #endif
  84 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  85         case 3:
  86                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  87                 break;
  88 #endif
  89         default:
  90                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  91                 return;
  92         }
  93
  94         if (step == 2)
  95                 goto step2;
  96
  97         if (regs->ddr_eor)
  98                 ddr_out32(&ddr->eor, regs->ddr_eor);
  99
 100         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 101
 102         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 103                 if (i == 0) {
 104                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 105                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 106                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 107
 108                 } else if (i == 1) {
 109                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 110                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 111                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 112
 113                 } else if (i == 2) {
 114                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 115                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 116                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 117
 118                 } else if (i == 3) {
 119                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 120                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 121                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 122                 }
 123         }
 124
 125         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 126         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 127         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 128         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 129         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 130         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 131         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 132         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 133         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 134         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 135         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 136         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 137         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 138         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 139         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 140         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 141         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 142         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 143         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 144         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 145         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 146         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 147         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 148         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 149         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 150         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 151         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 152         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 153         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 154         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 155         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 156         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 157         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 158 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 159         ddr_out32(&ddr->sdram_interval,
 160                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 161 #else
 162         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 163 #endif
 164         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 165         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 166 #ifndef CONFIG_SYS_FSL_DDR_EMU
 167         /*
 168          * Skip these two registers if running on emulator
 169          * because emulator doesn't have skew between bytes.
 170          */
 171
 172         if (regs->ddr_wrlvl_cntl_2)
 173                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 174         if (regs->ddr_wrlvl_cntl_3)
 175                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 176 #endif
 177
 178         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 179         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 180         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 181         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 182         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 183         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 184         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 185         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 186 #ifdef CONFIG_DEEP_SLEEP
 187         if (is_warm_boot()) {
 188                 ddr_out32(&ddr->sdram_cfg_2,
 189                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 190                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 191                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 192
 193                 /* DRAM VRef will not be trained */
 194                 ddr_out32(&ddr->ddr_cdr2,
 195                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 196         } else
 197 #endif
 198         {
 199                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 200                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 201                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 202                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 203         }
 204
 205 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 206         /* part 1 of 2 */
 207         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 208                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 209                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 210                                   regs->ddr_sdram_rcw_2 & ~0x0f000000);
 211                 }
 212                 ddr_out32(&ddr->err_disable, regs->err_disable |
 213                           DDR_ERR_DISABLE_APED);
 214         }
 215 #else
 216         ddr_out32(&ddr->err_disable, regs->err_disable);
 217 #endif
 218         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 219         for (i = 0; i < 64; i++) {
 220                 if (regs->debug[i]) {
 221                         debug("Write to debug_%d as %08x\n",
 222                               i+1, regs->debug[i]);
 223                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 224                 }
 225         }
 226
 227 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 228         /* Part 1 of 2 */
 229         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 230                 /* Disable DRAM VRef training */
 231                 ddr_out32(&ddr->ddr_cdr2,
 232                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 233                 /* disable transmit bit deskew */
 234                 temp32 = ddr_in32(&ddr->debug[28]);
 235                 temp32 |= DDR_TX_BD_DIS;
 236                 ddr_out32(&ddr->debug[28], temp32);
 237                 ddr_out32(&ddr->debug[25], 0x9000);
 238         } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
 239                 /* Output enable forced off */
 240                 ddr_out32(&ddr->debug[37], 1 << 31);
 241                 /* Enable Vref training */
 242                 ddr_out32(&ddr->ddr_cdr2,
 243                           regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
 244         } else {
 245                 debug("Erratum A008511 doesn't apply.\n");
 246         }
 247 #endif
 248
 249 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
 250         defined(CONFIG_SYS_FSL_ERRATUM_A008511)
 251         /* Disable D_INIT */
 252         ddr_out32(&ddr->sdram_cfg_2,
 253                   regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 254 #endif
 255
 256 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 257         temp32 = ddr_in32(&ddr->debug[25]);
 258         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 259         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 260         ddr_out32(&ddr->debug[25], temp32);
 261 #endif
 262
 263 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 264         temp32 = get_ddr_freq(ctrl_num) / 1000000;
 265         if ((temp32 > 1900) && (temp32 < 2300)) {
 266                 temp32 = ddr_in32(&ddr->debug[28]);
 267                 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
 268         }
 269 #endif
 270         /*
 271          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 272          * deasserted. Clocks start when any chip select is enabled and clock
 273          * control register is set. Because all DDR components are connected to
 274          * one reset signal, this needs to be done in two steps. Step 1 is to
 275          * get the clocks started. Step 2 resumes after reset signal is
 276          * deasserted.
 277          */
 278         if (step == 1) {
 279                 udelay(200);
 280                 return;
 281         }
 282
 283 step2:
 284         /* Set, but do not enable the memory */
 285         temp32 = regs->ddr_sdram_cfg;
 286         temp32 &= ~(SDRAM_CFG_MEM_EN);
 287         ddr_out32(&ddr->sdram_cfg, temp32);
 288
 289         /*
 290          * 500 painful micro-seconds must elapse between
 291          * the DDR clock setup and the DDR config enable.
 292          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 293          * we choose the max, that is 500 us for all of case.
 294          */
 295         udelay(500);
 296         mb();
 297         isb();
 298
 299 #ifdef CONFIG_DEEP_SLEEP
 300         if (is_warm_boot()) {
 301                 /* enter self-refresh */
 302                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 303                 temp32 |= SDRAM_CFG2_FRC_SR;
 304                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 305                 /* do board specific memory setup */
 306                 board_mem_sleep_setup();
 307
 308                 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 309         } else
 310 #endif
 311                 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 312         /* Let the controller go */
 313         ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
 314         mb();
 315         isb();
 316
 317 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 318         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 319         /* Part 2 of 2 */
 320         timeout = 40;
 321         /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
 322         while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 323                (timeout > 0)) {
 324                 udelay(1000);
 325                 timeout--;
 326         }
 327         if (timeout <= 0) {
 328                 printf("Controler %d timeout, debug_2 = %x\n",
 329                        ctrl_num, ddr_in32(&ddr->debug[1]));
 330         }
 331
 332 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 333         /* This erraum only applies to verion 5.2.0 */
 334         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 335                 /* The vref setting sequence is different for range 2 */
 336                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 337                         vref_seq = vref_seq2;
 338
 339                 /* Set VREF */
 340                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 341                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 342                                 continue;
 343
 344                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 345                                  MD_CNTL_MD_EN                          |
 346                                  MD_CNTL_CS_SEL(i)                      |
 347                                  MD_CNTL_MD_SEL(6)                      |
 348                                  0x00200000;
 349                         temp32 = mr6 | vref_seq[0];
 350                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 351                                                 temp32, MD_CNTL_MD_EN);
 352                         udelay(1);
 353                         debug("MR6 = 0x%08x\n", temp32);
 354                         temp32 = mr6 | vref_seq[1];
 355                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 356                                                 temp32, MD_CNTL_MD_EN);
 357                         udelay(1);
 358                         debug("MR6 = 0x%08x\n", temp32);
 359                         temp32 = mr6 | vref_seq[2];
 360                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 361                                                 temp32, MD_CNTL_MD_EN);
 362                         udelay(1);
 363                         debug("MR6 = 0x%08x\n", temp32);
 364                 }
 365                 ddr_out32(&ddr->sdram_md_cntl, 0);
 366                 temp32 = ddr_in32(&ddr->debug[28]);
 367                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 368                 ddr_out32(&ddr->debug[28], temp32);
 369                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 370                 /* wait for idle */
 371                 timeout = 40;
 372                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 373                        (timeout > 0)) {
 374                         udelay(1000);
 375                         timeout--;
 376                 }
 377                 if (timeout <= 0) {
 378                         printf("Controler %d timeout, debug_2 = %x\n",
 379                                ctrl_num, ddr_in32(&ddr->debug[1]));
 380                 }
 381         }
 382 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 383
 384 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 385         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 386                 /* if it's RDIMM */
 387                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 388                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 389                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 390                                         continue;
 391                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 392                                                         MD_CNTL_MD_EN |
 393                                                         MD_CNTL_CS_SEL(i) |
 394                                                         0x070000ed,
 395                                                         MD_CNTL_MD_EN);
 396                                 udelay(1);
 397                         }
 398                 }
 399
 400                 ddr_out32(&ddr->err_disable,
 401                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 402         }
 403 #endif
 404         /* Restore D_INIT */
 405         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 406 #endif
 407
 408         total_gb_size_per_controller = 0;
 409         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 410                 if (!(regs->cs[i].config & 0x80000000))
 411                         continue;
 412                 total_gb_size_per_controller += 1 << (
 413                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 414                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 415                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 416                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 417                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 418                         26);                    /* minus 26 (count of 64M) */
 419         }
 420         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 421                 total_gb_size_per_controller *= 3;
 422         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 423                 total_gb_size_per_controller <<= 1;
 424         /*
 425          * total memory / bus width = transactions needed
 426          * transactions needed / data rate = seconds
 427          * to add plenty of buffer, double the time
 428          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 429          * Let's wait for 800ms
 430          */
 431         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 432                         >> SDRAM_CFG_DBW_SHIFT);
 433         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 434                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 435         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 436         debug("total %d GB\n", total_gb_size_per_controller);
 437         debug("Need to wait up to %d * 10ms\n", timeout);
 438
 439         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 440         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 441                 (timeout >= 0)) {
 442                 udelay(10000);          /* throttle polling rate */
 443                 timeout--;
 444         }
 445
 446         if (timeout <= 0)
 447                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 448
 449 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 450         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 451 #endif
 452
 453 #ifdef CONFIG_DEEP_SLEEP
 454         if (is_warm_boot()) {
 455                 /* exit self-refresh */
 456                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 457                 temp32 &= ~SDRAM_CFG2_FRC_SR;
 458                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 459         }
 460 #endif
 461
 462 #ifdef CONFIG_FSL_DDR_BIST
 463 #define BIST_PATTERN1   0xFFFFFFFF
 464 #define BIST_PATTERN2   0x0
 465 #define BIST_CR         0x80010000
 466 #define BIST_CR_EN      0x80000000
 467 #define BIST_CR_STAT    0x00000001
 468 #define CTLR_INTLV_MASK 0x20000000
 469         /* Perform build-in test on memory. Three-way interleaving is not yet
 470          * supported by this code. */
 471         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 472                 puts("Running BIST test. This will take a while...");
 473                 cs0_config = ddr_in32(&ddr->cs0_config);
 474                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 475                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 476                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 477                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 478                 if (cs0_config & CTLR_INTLV_MASK) {
 479                         /* set bnds to non-interleaving */
 480                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 481                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 482                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 483                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 484                 }
 485                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 486                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 487                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 488                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 489                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 490                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 491                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 492                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 493                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 494                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 495                 mtcr = BIST_CR;
 496                 ddr_out32(&ddr->mtcr, mtcr);
 497                 timeout = 100;
 498                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 499                         mdelay(1000);
 500                         timeout--;
 501                         mtcr = ddr_in32(&ddr->mtcr);
 502                 }
 503                 if (timeout <= 0)
 504                         puts("Timeout\n");
 505                 else
 506                         puts("Done\n");
 507                 err_detect = ddr_in32(&ddr->err_detect);
 508                 err_sbe = ddr_in32(&ddr->err_sbe);
 509                 if (mtcr & BIST_CR_STAT) {
 510                         printf("BIST test failed on controller %d.\n",
 511                                ctrl_num);
 512                 }
 513                 if (err_detect || (err_sbe & 0xffff)) {
 514                         printf("ECC error detected on controller %d.\n",
 515                                ctrl_num);
 516                 }
 517
 518                 if (cs0_config & CTLR_INTLV_MASK) {
 519                         /* restore bnds registers */
 520                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 521                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 522                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 523                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 524                 }
 525         }
 526 #endif
 527 }