drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_errata.h>
  14
  15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  16         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  18 {
  19         int timeout = 1000;
  20
  21         ddr_out32(ptr, value);
  22
  23         while (ddr_in32(ptr) & bits) {
  24                 udelay(100);
  25                 timeout--;
  26         }
  27         if (timeout <= 0)
  28                 puts("Error: wait for clear timeout.\n");
  29 }
  30 #endif
  31
  32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  34 #endif
  35
  36 /*
  37  * regs has the to-be-set values for DDR controller registers
  38  * ctrl_num is the DDR controller number
  39  * step: 0 goes through the initialization in one pass
  40  *       1 sets registers and returns before enabling controller
  41  *       2 resumes from step 1 and continues to initialize
  42  * Dividing the initialization to two steps to deassert DDR reset signal
  43  * to comply with JEDEC specs for RDIMMs.
  44  */
  45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  46                              unsigned int ctrl_num, int step)
  47 {
  48         unsigned int i, bus_width;
  49         struct ccsr_ddr __iomem *ddr;
  50         u32 temp32;
  51         u32 total_gb_size_per_controller;
  52         int timeout;
  53
  54 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  55         u32 mr6;
  56         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  57         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  58         u32 *vref_seq = vref_seq1;
  59 #endif
  60 #ifdef CONFIG_FSL_DDR_BIST
  61         u32 mtcr, err_detect, err_sbe;
  62         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  63 #endif
  64 #ifdef CONFIG_FSL_DDR_BIST
  65         char buffer[CONFIG_SYS_CBSIZE];
  66 #endif
  67 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942)
  68         u32 ddr_freq;
  69 #endif
  70         switch (ctrl_num) {
  71         case 0:
  72                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  73                 break;
  74 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  75         case 1:
  76                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  77                 break;
  78 #endif
  79 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  80         case 2:
  81                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  82                 break;
  83 #endif
  84 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  85         case 3:
  86                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  87                 break;
  88 #endif
  89         default:
  90                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  91                 return;
  92         }
  93
  94         if (step == 2)
  95                 goto step2;
  96
  97         if (regs->ddr_eor)
  98                 ddr_out32(&ddr->eor, regs->ddr_eor);
  99
 100         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 101
 102         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 103                 if (i == 0) {
 104                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 105                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 106                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 107
 108                 } else if (i == 1) {
 109                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 110                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 111                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 112
 113                 } else if (i == 2) {
 114                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 115                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 116                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 117
 118                 } else if (i == 3) {
 119                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 120                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 121                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 122                 }
 123         }
 124
 125         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 126         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 127         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 128         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 129         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 130         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 131         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 132         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 133         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 134         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 135         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 136         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 137         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 138         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 139         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 140         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 141         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 142         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 143         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 144         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 145         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 146         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 147         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 148         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 149         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 150         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 151         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 152         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 153         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 154         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 155         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 156         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 157         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 158 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 159         ddr_out32(&ddr->sdram_interval,
 160                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 161 #else
 162         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 163 #endif
 164         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 165         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 166 #ifndef CONFIG_SYS_FSL_DDR_EMU
 167         /*
 168          * Skip these two registers if running on emulator
 169          * because emulator doesn't have skew between bytes.
 170          */
 171
 172         if (regs->ddr_wrlvl_cntl_2)
 173                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 174         if (regs->ddr_wrlvl_cntl_3)
 175                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 176 #endif
 177
 178         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 179         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 180         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 181         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 182         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 183         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 184         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 185         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 186 #ifdef CONFIG_DEEP_SLEEP
 187         if (is_warm_boot()) {
 188                 ddr_out32(&ddr->sdram_cfg_2,
 189                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 190                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 191                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 192
 193                 /* DRAM VRef will not be trained */
 194                 ddr_out32(&ddr->ddr_cdr2,
 195                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 196         } else
 197 #endif
 198         {
 199                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 200                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 201                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 202                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 203         }
 204
 205 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 206         /* part 1 of 2 */
 207         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 208                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 209                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 210                                   regs->ddr_sdram_rcw_2 & ~0x0f000000);
 211                 }
 212                 ddr_out32(&ddr->err_disable, regs->err_disable |
 213                           DDR_ERR_DISABLE_APED);
 214         }
 215 #else
 216         ddr_out32(&ddr->err_disable, regs->err_disable);
 217 #endif
 218         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 219         for (i = 0; i < 64; i++) {
 220                 if (regs->debug[i]) {
 221                         debug("Write to debug_%d as %08x\n",
 222                               i+1, regs->debug[i]);
 223                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 224                 }
 225         }
 226 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 227         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 228 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 229 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 230         if (has_erratum_a008378()) {
 231                 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 232                     IS_DBI(regs->ddr_sdram_cfg_3))
 233                         ddr_setbits32(&ddr->debug[28], 0x9 << 20);
 234         }
 235 #endif
 236
 237 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 238         /* Part 1 of 2 */
 239         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 240                 /* Disable DRAM VRef training */
 241                 ddr_out32(&ddr->ddr_cdr2,
 242                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 243                 /* disable transmit bit deskew */
 244                 temp32 = ddr_in32(&ddr->debug[28]);
 245                 temp32 |= DDR_TX_BD_DIS;
 246                 ddr_out32(&ddr->debug[28], temp32);
 247                 ddr_out32(&ddr->debug[25], 0x9000);
 248         } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
 249                 /* Output enable forced off */
 250                 ddr_out32(&ddr->debug[37], 1 << 31);
 251                 /* Enable Vref training */
 252                 ddr_out32(&ddr->ddr_cdr2,
 253                           regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
 254         } else {
 255                 debug("Erratum A008511 doesn't apply.\n");
 256         }
 257 #endif
 258
 259 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
 260         defined(CONFIG_SYS_FSL_ERRATUM_A008511)
 261         /* Disable D_INIT */
 262         ddr_out32(&ddr->sdram_cfg_2,
 263                   regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 264 #endif
 265
 266 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 267         temp32 = ddr_in32(&ddr->debug[25]);
 268         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 269         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 270         ddr_out32(&ddr->debug[25], temp32);
 271 #endif
 272
 273 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 274         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 275         temp32 = ddr_in32(&ddr->debug[28]);
 276         if (ddr_freq <= 1333)
 277                 ddr_out32(&ddr->debug[28], temp32 | 0x0080006a);
 278         else if (ddr_freq <= 1600)
 279                 ddr_out32(&ddr->debug[28], temp32 | 0x0070006f);
 280         else if (ddr_freq <= 1867)
 281                 ddr_out32(&ddr->debug[28], temp32 | 0x00700076);
 282         else if (ddr_freq <= 2133)
 283                 ddr_out32(&ddr->debug[28], temp32 | 0x0060007b);
 284 #endif
 285
 286 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 287         temp32 = get_ddr_freq(ctrl_num) / 1000000;
 288         if ((temp32 > 1900) && (temp32 < 2300)) {
 289                 temp32 = ddr_in32(&ddr->debug[28]);
 290                 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
 291         }
 292 #endif
 293         /*
 294          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 295          * deasserted. Clocks start when any chip select is enabled and clock
 296          * control register is set. Because all DDR components are connected to
 297          * one reset signal, this needs to be done in two steps. Step 1 is to
 298          * get the clocks started. Step 2 resumes after reset signal is
 299          * deasserted.
 300          */
 301         if (step == 1) {
 302                 udelay(200);
 303                 return;
 304         }
 305
 306 step2:
 307         /* Set, but do not enable the memory */
 308         temp32 = regs->ddr_sdram_cfg;
 309         temp32 &= ~(SDRAM_CFG_MEM_EN);
 310         ddr_out32(&ddr->sdram_cfg, temp32);
 311
 312         /*
 313          * 500 painful micro-seconds must elapse between
 314          * the DDR clock setup and the DDR config enable.
 315          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 316          * we choose the max, that is 500 us for all of case.
 317          */
 318         udelay(500);
 319         mb();
 320         isb();
 321
 322 #ifdef CONFIG_DEEP_SLEEP
 323         if (is_warm_boot()) {
 324                 /* enter self-refresh */
 325                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 326                 temp32 |= SDRAM_CFG2_FRC_SR;
 327                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 328                 /* do board specific memory setup */
 329                 board_mem_sleep_setup();
 330
 331                 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 332         } else
 333 #endif
 334                 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 335         /* Let the controller go */
 336         ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
 337         mb();
 338         isb();
 339
 340 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 341         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 342         /* Part 2 of 2 */
 343         timeout = 40;
 344         /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
 345         while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 346                (timeout > 0)) {
 347                 udelay(1000);
 348                 timeout--;
 349         }
 350         if (timeout <= 0) {
 351                 printf("Controler %d timeout, debug_2 = %x\n",
 352                        ctrl_num, ddr_in32(&ddr->debug[1]));
 353         }
 354
 355 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 356         /* This erraum only applies to verion 5.2.0 */
 357         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 358                 /* The vref setting sequence is different for range 2 */
 359                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 360                         vref_seq = vref_seq2;
 361
 362                 /* Set VREF */
 363                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 364                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 365                                 continue;
 366
 367                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 368                                  MD_CNTL_MD_EN                          |
 369                                  MD_CNTL_CS_SEL(i)                      |
 370                                  MD_CNTL_MD_SEL(6)                      |
 371                                  0x00200000;
 372                         temp32 = mr6 | vref_seq[0];
 373                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 374                                                 temp32, MD_CNTL_MD_EN);
 375                         udelay(1);
 376                         debug("MR6 = 0x%08x\n", temp32);
 377                         temp32 = mr6 | vref_seq[1];
 378                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 379                                                 temp32, MD_CNTL_MD_EN);
 380                         udelay(1);
 381                         debug("MR6 = 0x%08x\n", temp32);
 382                         temp32 = mr6 | vref_seq[2];
 383                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 384                                                 temp32, MD_CNTL_MD_EN);
 385                         udelay(1);
 386                         debug("MR6 = 0x%08x\n", temp32);
 387                 }
 388                 ddr_out32(&ddr->sdram_md_cntl, 0);
 389                 temp32 = ddr_in32(&ddr->debug[28]);
 390                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 391                 ddr_out32(&ddr->debug[28], temp32);
 392                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 393                 /* wait for idle */
 394                 timeout = 40;
 395                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 396                        (timeout > 0)) {
 397                         udelay(1000);
 398                         timeout--;
 399                 }
 400                 if (timeout <= 0) {
 401                         printf("Controler %d timeout, debug_2 = %x\n",
 402                                ctrl_num, ddr_in32(&ddr->debug[1]));
 403                 }
 404         }
 405 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 406
 407 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 408         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 409                 /* if it's RDIMM */
 410                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 411                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 412                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 413                                         continue;
 414                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 415                                                         MD_CNTL_MD_EN |
 416                                                         MD_CNTL_CS_SEL(i) |
 417                                                         0x070000ed,
 418                                                         MD_CNTL_MD_EN);
 419                                 udelay(1);
 420                         }
 421                 }
 422
 423                 ddr_out32(&ddr->err_disable,
 424                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 425         }
 426 #endif
 427         /* Restore D_INIT */
 428         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 429 #endif
 430
 431         total_gb_size_per_controller = 0;
 432         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 433                 if (!(regs->cs[i].config & 0x80000000))
 434                         continue;
 435                 total_gb_size_per_controller += 1 << (
 436                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 437                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 438                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 439                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 440                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 441                         26);                    /* minus 26 (count of 64M) */
 442         }
 443         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 444                 total_gb_size_per_controller *= 3;
 445         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 446                 total_gb_size_per_controller <<= 1;
 447         /*
 448          * total memory / bus width = transactions needed
 449          * transactions needed / data rate = seconds
 450          * to add plenty of buffer, double the time
 451          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 452          * Let's wait for 800ms
 453          */
 454         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 455                         >> SDRAM_CFG_DBW_SHIFT);
 456         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 457                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 458         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 459         debug("total %d GB\n", total_gb_size_per_controller);
 460         debug("Need to wait up to %d * 10ms\n", timeout);
 461
 462         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 463         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 464                 (timeout >= 0)) {
 465                 udelay(10000);          /* throttle polling rate */
 466                 timeout--;
 467         }
 468
 469         if (timeout <= 0)
 470                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 471
 472 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 473         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 474 #endif
 475
 476 #ifdef CONFIG_DEEP_SLEEP
 477         if (is_warm_boot()) {
 478                 /* exit self-refresh */
 479                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 480                 temp32 &= ~SDRAM_CFG2_FRC_SR;
 481                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 482         }
 483 #endif
 484
 485 #ifdef CONFIG_FSL_DDR_BIST
 486 #define BIST_PATTERN1   0xFFFFFFFF
 487 #define BIST_PATTERN2   0x0
 488 #define BIST_CR         0x80010000
 489 #define BIST_CR_EN      0x80000000
 490 #define BIST_CR_STAT    0x00000001
 491 #define CTLR_INTLV_MASK 0x20000000
 492         /* Perform build-in test on memory. Three-way interleaving is not yet
 493          * supported by this code. */
 494         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 495                 puts("Running BIST test. This will take a while...");
 496                 cs0_config = ddr_in32(&ddr->cs0_config);
 497                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 498                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 499                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 500                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 501                 if (cs0_config & CTLR_INTLV_MASK) {
 502                         /* set bnds to non-interleaving */
 503                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 504                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 505                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 506                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 507                 }
 508                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 509                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 510                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 511                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 512                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 513                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 514                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 515                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 516                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 517                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 518                 mtcr = BIST_CR;
 519                 ddr_out32(&ddr->mtcr, mtcr);
 520                 timeout = 100;
 521                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 522                         mdelay(1000);
 523                         timeout--;
 524                         mtcr = ddr_in32(&ddr->mtcr);
 525                 }
 526                 if (timeout <= 0)
 527                         puts("Timeout\n");
 528                 else
 529                         puts("Done\n");
 530                 err_detect = ddr_in32(&ddr->err_detect);
 531                 err_sbe = ddr_in32(&ddr->err_sbe);
 532                 if (mtcr & BIST_CR_STAT) {
 533                         printf("BIST test failed on controller %d.\n",
 534                                ctrl_num);
 535                 }
 536                 if (err_detect || (err_sbe & 0xffff)) {
 537                         printf("ECC error detected on controller %d.\n",
 538                                ctrl_num);
 539                 }
 540
 541                 if (cs0_config & CTLR_INTLV_MASK) {
 542                         /* restore bnds registers */
 543                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 544                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 545                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 546                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 547                 }
 548         }
 549 #endif
 550 }