drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_errata.h>
  14
  15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  16         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  18 {
  19         int timeout = 1000;
  20
  21         ddr_out32(ptr, value);
  22
  23         while (ddr_in32(ptr) & bits) {
  24                 udelay(100);
  25                 timeout--;
  26         }
  27         if (timeout <= 0)
  28                 puts("Error: wait for clear timeout.\n");
  29 }
  30 #endif
  31
  32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  34 #endif
  35
  36 /*
  37  * regs has the to-be-set values for DDR controller registers
  38  * ctrl_num is the DDR controller number
  39  * step: 0 goes through the initialization in one pass
  40  *       1 sets registers and returns before enabling controller
  41  *       2 resumes from step 1 and continues to initialize
  42  * Dividing the initialization to two steps to deassert DDR reset signal
  43  * to comply with JEDEC specs for RDIMMs.
  44  */
  45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  46                              unsigned int ctrl_num, int step)
  47 {
  48         unsigned int i, bus_width;
  49         struct ccsr_ddr __iomem *ddr;
  50         u32 temp_sdram_cfg;
  51         u32 total_gb_size_per_controller;
  52         int timeout;
  53 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  54         u32 temp32, mr6;
  55         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  56         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  57         u32 *vref_seq = vref_seq1;
  58 #endif
  59 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  60         ulong ddr_freq;
  61         u32 tmp;
  62 #endif
  63 #ifdef CONFIG_FSL_DDR_BIST
  64         u32 mtcr, err_detect, err_sbe;
  65         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  66 #endif
  67 #ifdef CONFIG_FSL_DDR_BIST
  68         char buffer[CONFIG_SYS_CBSIZE];
  69 #endif
  70
  71         switch (ctrl_num) {
  72         case 0:
  73                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  74                 break;
  75 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  76         case 1:
  77                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  78                 break;
  79 #endif
  80 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  81         case 2:
  82                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  83                 break;
  84 #endif
  85 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  86         case 3:
  87                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  88                 break;
  89 #endif
  90         default:
  91                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  92                 return;
  93         }
  94
  95         if (step == 2)
  96                 goto step2;
  97
  98         if (regs->ddr_eor)
  99                 ddr_out32(&ddr->eor, regs->ddr_eor);
 100
 101         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 102
 103         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 104                 if (i == 0) {
 105                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 106                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 107                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 108
 109                 } else if (i == 1) {
 110                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 111                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 112                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 113
 114                 } else if (i == 2) {
 115                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 116                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 117                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 118
 119                 } else if (i == 3) {
 120                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 121                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 122                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 123                 }
 124         }
 125
 126         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 127         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 128         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 129         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 130         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 131         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 132         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 133         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 134         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 135         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 136         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 137         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 138         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 139         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 140         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 141         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 142         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 143         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 144         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 145         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 146         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 147         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 148         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 149         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 150         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 151         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 152         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 153         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 154         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 155         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 156         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 157         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 158         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 159 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 160         ddr_out32(&ddr->sdram_interval,
 161                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 162 #else
 163         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 164 #endif
 165         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 166         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 167 #ifndef CONFIG_SYS_FSL_DDR_EMU
 168         /*
 169          * Skip these two registers if running on emulator
 170          * because emulator doesn't have skew between bytes.
 171          */
 172
 173         if (regs->ddr_wrlvl_cntl_2)
 174                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 175         if (regs->ddr_wrlvl_cntl_3)
 176                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 177 #endif
 178
 179         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 180         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 181         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 182         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 183         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 184         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 185         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 186         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 187 #ifdef CONFIG_DEEP_SLEEP
 188         if (is_warm_boot()) {
 189                 ddr_out32(&ddr->sdram_cfg_2,
 190                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 191                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 192                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 193
 194                 /* DRAM VRef will not be trained */
 195                 ddr_out32(&ddr->ddr_cdr2,
 196                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 197         } else
 198 #endif
 199         {
 200                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 201                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 202                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 203                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 204         }
 205
 206 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 207         /* part 1 of 2 */
 208         if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 209                 ddr_out32(&ddr->ddr_sdram_rcw_2,
 210                           regs->ddr_sdram_rcw_2 & ~0x0f000000);
 211         }
 212
 213         ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 214 #else
 215         ddr_out32(&ddr->err_disable, regs->err_disable);
 216 #endif
 217         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 218         for (i = 0; i < 32; i++) {
 219                 if (regs->debug[i]) {
 220                         debug("Write to debug_%d as %08x\n",
 221                               i+1, regs->debug[i]);
 222                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 223                 }
 224         }
 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 226         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 227 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 228 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 229         if (has_erratum_a008378()) {
 230                 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 231                     IS_DBI(regs->ddr_sdram_cfg_3))
 232                         ddr_setbits32(&ddr->debug[28], 0x9 << 20);
 233         }
 234 #endif
 235
 236 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 237         /* Part 1 of 2 */
 238         /* This erraum only applies to verion 5.2.0 */
 239         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 240                 /* Disable DRAM VRef training */
 241                 ddr_out32(&ddr->ddr_cdr2,
 242                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 243                 /* Disable deskew */
 244                 ddr_out32(&ddr->debug[28], 0x400);
 245                 /* Disable D_INIT */
 246                 ddr_out32(&ddr->sdram_cfg_2,
 247                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 248                 ddr_out32(&ddr->debug[25], 0x9000);
 249         }
 250 #endif
 251
 252 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 253         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 254         tmp = ddr_in32(&ddr->debug[28]);
 255         if (ddr_freq <= 1333)
 256                 ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
 257         else if (ddr_freq <= 1600)
 258                 ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
 259         else if (ddr_freq <= 1867)
 260                 ddr_out32(&ddr->debug[28], tmp | 0x00700076);
 261         else if (ddr_freq <= 2133)
 262                 ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 263 #endif
 264
 265         /*
 266          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 267          * deasserted. Clocks start when any chip select is enabled and clock
 268          * control register is set. Because all DDR components are connected to
 269          * one reset signal, this needs to be done in two steps. Step 1 is to
 270          * get the clocks started. Step 2 resumes after reset signal is
 271          * deasserted.
 272          */
 273         if (step == 1) {
 274                 udelay(200);
 275                 return;
 276         }
 277
 278 step2:
 279         /* Set, but do not enable the memory */
 280         temp_sdram_cfg = regs->ddr_sdram_cfg;
 281         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 282         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 283
 284         /*
 285          * 500 painful micro-seconds must elapse between
 286          * the DDR clock setup and the DDR config enable.
 287          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 288          * we choose the max, that is 500 us for all of case.
 289          */
 290         udelay(500);
 291         mb();
 292         isb();
 293
 294 #ifdef CONFIG_DEEP_SLEEP
 295         if (is_warm_boot()) {
 296                 /* enter self-refresh */
 297                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 298                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 299                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 300                 /* do board specific memory setup */
 301                 board_mem_sleep_setup();
 302
 303                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 304         } else
 305 #endif
 306                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 307         /* Let the controller go */
 308         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 309         mb();
 310         isb();
 311
 312 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 313         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 314         /* Part 2 of 2 */
 315         /* This erraum only applies to verion 5.2.0 */
 316         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 317                 /* Wait for idle */
 318                 timeout = 40;
 319                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 320                        (timeout > 0)) {
 321                         udelay(1000);
 322                         timeout--;
 323                 }
 324                 if (timeout <= 0) {
 325                         printf("Controler %d timeout, debug_2 = %x\n",
 326                                ctrl_num, ddr_in32(&ddr->debug[1]));
 327                 }
 328
 329 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 330                 /* The vref setting sequence is different for range 2 */
 331                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 332                         vref_seq = vref_seq2;
 333
 334                 /* Set VREF */
 335                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 336                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 337                                 continue;
 338
 339                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 340                                  MD_CNTL_MD_EN                          |
 341                                  MD_CNTL_CS_SEL(i)                      |
 342                                  MD_CNTL_MD_SEL(6)                      |
 343                                  0x00200000;
 344                         temp32 = mr6 | vref_seq[0];
 345                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 346                                                 temp32, MD_CNTL_MD_EN);
 347                         udelay(1);
 348                         debug("MR6 = 0x%08x\n", temp32);
 349                         temp32 = mr6 | vref_seq[1];
 350                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 351                                                 temp32, MD_CNTL_MD_EN);
 352                         udelay(1);
 353                         debug("MR6 = 0x%08x\n", temp32);
 354                         temp32 = mr6 | vref_seq[2];
 355                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 356                                                 temp32, MD_CNTL_MD_EN);
 357                         udelay(1);
 358                         debug("MR6 = 0x%08x\n", temp32);
 359                 }
 360                 ddr_out32(&ddr->sdram_md_cntl, 0);
 361                 ddr_out32(&ddr->debug[28], 0);          /* Enable deskew */
 362                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 363                 /* wait for idle */
 364                 timeout = 40;
 365                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 366                        (timeout > 0)) {
 367                         udelay(1000);
 368                         timeout--;
 369                 }
 370                 if (timeout <= 0) {
 371                         printf("Controler %d timeout, debug_2 = %x\n",
 372                                ctrl_num, ddr_in32(&ddr->debug[1]));
 373                 }
 374                 /* Restore D_INIT */
 375                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 376 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 377
 378 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 379                 /* if it's RDIMM */
 380                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 381                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 382                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 383                                         continue;
 384                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 385                                                         MD_CNTL_MD_EN |
 386                                                         MD_CNTL_CS_SEL(i) |
 387                                                         0x070000ed,
 388                                                         MD_CNTL_MD_EN);
 389                                 udelay(1);
 390                         }
 391                 }
 392
 393                 ddr_out32(&ddr->err_disable,
 394                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 395 #endif
 396         }
 397 #endif
 398
 399         total_gb_size_per_controller = 0;
 400         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 401                 if (!(regs->cs[i].config & 0x80000000))
 402                         continue;
 403                 total_gb_size_per_controller += 1 << (
 404                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 405                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 406                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 407                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 408                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 409                         26);                    /* minus 26 (count of 64M) */
 410         }
 411         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 412                 total_gb_size_per_controller *= 3;
 413         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 414                 total_gb_size_per_controller <<= 1;
 415         /*
 416          * total memory / bus width = transactions needed
 417          * transactions needed / data rate = seconds
 418          * to add plenty of buffer, double the time
 419          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 420          * Let's wait for 800ms
 421          */
 422         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 423                         >> SDRAM_CFG_DBW_SHIFT);
 424         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 425                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 426         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 427         debug("total %d GB\n", total_gb_size_per_controller);
 428         debug("Need to wait up to %d * 10ms\n", timeout);
 429
 430         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 431         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 432                 (timeout >= 0)) {
 433                 udelay(10000);          /* throttle polling rate */
 434                 timeout--;
 435         }
 436
 437         if (timeout <= 0)
 438                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 439
 440 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 441         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 442 #endif
 443
 444 #ifdef CONFIG_DEEP_SLEEP
 445         if (is_warm_boot()) {
 446                 /* exit self-refresh */
 447                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 448                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 449                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 450         }
 451 #endif
 452
 453 #ifdef CONFIG_FSL_DDR_BIST
 454 #define BIST_PATTERN1   0xFFFFFFFF
 455 #define BIST_PATTERN2   0x0
 456 #define BIST_CR         0x80010000
 457 #define BIST_CR_EN      0x80000000
 458 #define BIST_CR_STAT    0x00000001
 459 #define CTLR_INTLV_MASK 0x20000000
 460         /* Perform build-in test on memory. Three-way interleaving is not yet
 461          * supported by this code. */
 462         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 463                 puts("Running BIST test. This will take a while...");
 464                 cs0_config = ddr_in32(&ddr->cs0_config);
 465                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 466                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 467                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 468                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 469                 if (cs0_config & CTLR_INTLV_MASK) {
 470                         /* set bnds to non-interleaving */
 471                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 472                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 473                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 474                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 475                 }
 476                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 477                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 478                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 479                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 480                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 481                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 482                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 483                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 484                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 485                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 486                 mtcr = BIST_CR;
 487                 ddr_out32(&ddr->mtcr, mtcr);
 488                 timeout = 100;
 489                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 490                         mdelay(1000);
 491                         timeout--;
 492                         mtcr = ddr_in32(&ddr->mtcr);
 493                 }
 494                 if (timeout <= 0)
 495                         puts("Timeout\n");
 496                 else
 497                         puts("Done\n");
 498                 err_detect = ddr_in32(&ddr->err_detect);
 499                 err_sbe = ddr_in32(&ddr->err_sbe);
 500                 if (mtcr & BIST_CR_STAT) {
 501                         printf("BIST test failed on controller %d.\n",
 502                                ctrl_num);
 503                 }
 504                 if (err_detect || (err_sbe & 0xffff)) {
 505                         printf("ECC error detected on controller %d.\n",
 506                                ctrl_num);
 507                 }
 508
 509                 if (cs0_config & CTLR_INTLV_MASK) {
 510                         /* restore bnds registers */
 511                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 512                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 513                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 514                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 515                 }
 516         }
 517 #endif
 518 }