2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
10 #include <asm/processor.h>
11 #include <fsl_immap.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
19 * regs has the to-be-set values for DDR controller registers
20 * ctrl_num is the DDR controller number
21 * step: 0 goes through the initialization in one pass
22 * 1 sets registers and returns before enabling controller
23 * 2 resumes from step 1 and continues to initialize
24 * Dividing the initialization to two steps to deassert DDR reset signal
25 * to comply with JEDEC specs for RDIMMs.
27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 unsigned int ctrl_num, int step)
30 unsigned int i, bus_width;
31 struct ccsr_ddr __iomem *ddr;
33 u32 total_gb_size_per_controller;
38 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
40 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
42 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
45 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
47 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
50 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
52 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
56 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
64 ddr_out32(&ddr->eor, regs->ddr_eor);
66 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
68 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
71 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
76 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
81 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
85 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
86 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
87 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
91 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
92 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
93 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
94 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
95 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
96 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
97 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
98 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
99 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
100 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
101 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
102 ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
103 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
104 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
105 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
106 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
107 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
108 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
109 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
110 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
111 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
112 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
113 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
114 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
115 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
116 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
117 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
118 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
119 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
120 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
121 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
122 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
123 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
124 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
125 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
126 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
127 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
128 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
129 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
130 #ifndef CONFIG_SYS_FSL_DDR_EMU
132 * Skip these two registers if running on emulator
133 * because emulator doesn't have skew between bytes.
136 if (regs->ddr_wrlvl_cntl_2)
137 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
138 if (regs->ddr_wrlvl_cntl_3)
139 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
142 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
143 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
144 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
145 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
146 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
147 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
148 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
149 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
150 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
151 ddr_out32(&ddr->err_disable, regs->err_disable);
152 ddr_out32(&ddr->err_int_en, regs->err_int_en);
153 for (i = 0; i < 32; i++) {
154 if (regs->debug[i]) {
155 debug("Write to debug_%d as %08x\n",
156 i+1, regs->debug[i]);
157 ddr_out32(&ddr->debug[i], regs->debug[i]);
162 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
163 * deasserted. Clocks start when any chip select is enabled and clock
164 * control register is set. Because all DDR components are connected to
165 * one reset signal, this needs to be done in two steps. Step 1 is to
166 * get the clocks started. Step 2 resumes after reset signal is
175 /* Set, but do not enable the memory */
176 temp_sdram_cfg = regs->ddr_sdram_cfg;
177 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
178 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
181 * 500 painful micro-seconds must elapse between
182 * the DDR clock setup and the DDR config enable.
183 * DDR2 need 200 us, and DDR3 need 500 us from spec,
184 * we choose the max, that is 500 us for all of case.
190 /* Let the controller go */
191 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
192 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
196 total_gb_size_per_controller = 0;
197 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
198 if (!(regs->cs[i].config & 0x80000000))
200 total_gb_size_per_controller += 1 << (
201 ((regs->cs[i].config >> 14) & 0x3) + 2 +
202 ((regs->cs[i].config >> 8) & 0x7) + 12 +
203 ((regs->cs[i].config >> 4) & 0x3) + 0 +
204 ((regs->cs[i].config >> 0) & 0x7) + 8 +
205 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
206 26); /* minus 26 (count of 64M) */
208 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
209 total_gb_size_per_controller *= 3;
210 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
211 total_gb_size_per_controller <<= 1;
213 * total memory / bus width = transactions needed
214 * transactions needed / data rate = seconds
215 * to add plenty of buffer, double the time
216 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
217 * Let's wait for 800ms
219 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
220 >> SDRAM_CFG_DBW_SHIFT);
221 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
222 (get_ddr_freq(0) >> 20)) << 2;
223 total_gb_size_per_controller >>= 4; /* shift down to gb size */
224 debug("total %d GB\n", total_gb_size_per_controller);
225 debug("Need to wait up to %d * 10ms\n", timeout);
227 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
228 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
230 udelay(10000); /* throttle polling rate */
235 printf("Waiting for D_INIT timeout. Memory may not work.\n");