drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 /*
  19  * regs has the to-be-set values for DDR controller registers
  20  * ctrl_num is the DDR controller number
  21  * step: 0 goes through the initialization in one pass
  22  *       1 sets registers and returns before enabling controller
  23  *       2 resumes from step 1 and continues to initialize
  24  * Dividing the initialization to two steps to deassert DDR reset signal
  25  * to comply with JEDEC specs for RDIMMs.
  26  */
  27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  28                              unsigned int ctrl_num, int step)
  29 {
  30         unsigned int i, bus_width;
  31         struct ccsr_ddr __iomem *ddr;
  32         u32 temp_sdram_cfg;
  33         u32 total_gb_size_per_controller;
  34         int timeout;
  35 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  36         u32 *eddrtqcr1;
  37 #endif
  38
  39         switch (ctrl_num) {
  40         case 0:
  41                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  42 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  43                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  44 #endif
  45                 break;
  46 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  47         case 1:
  48                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  49 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  50                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  51 #endif
  52                 break;
  53 #endif
  54 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  55         case 2:
  56                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  57 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  58                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  59 #endif
  60                 break;
  61 #endif
  62 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  63         case 3:
  64                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  65 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  66                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
  67 #endif
  68                 break;
  69 #endif
  70         default:
  71                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  72                 return;
  73         }
  74
  75         if (step == 2)
  76                 goto step2;
  77
  78 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
  79 #ifdef CONFIG_LS2085A
  80         /* A008336 only applies to general DDR controllers */
  81         if ((ctrl_num == 0) || (ctrl_num == 1))
  82 #endif
  83                 ddr_out32(eddrtqcr1, 0x63b30002);
  84 #endif
  85         if (regs->ddr_eor)
  86                 ddr_out32(&ddr->eor, regs->ddr_eor);
  87
  88         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  89
  90         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  91                 if (i == 0) {
  92                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
  93                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
  94                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
  95
  96                 } else if (i == 1) {
  97                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
  98                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
  99                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 100
 101                 } else if (i == 2) {
 102                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 103                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 104                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 105
 106                 } else if (i == 3) {
 107                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 108                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 109                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 110                 }
 111         }
 112
 113         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 114         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 115         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 116         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 117         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 118         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 119         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 120         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 121         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 122         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 123         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 124         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 125         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 126         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 127         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 128         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 129         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 130         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 131         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 132         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 133         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 134         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 135         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 136         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 137         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 138         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 139         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 140         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 141         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 142         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 143         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 144         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 145         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 146         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 147         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 148         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 149 #ifndef CONFIG_SYS_FSL_DDR_EMU
 150         /*
 151          * Skip these two registers if running on emulator
 152          * because emulator doesn't have skew between bytes.
 153          */
 154
 155         if (regs->ddr_wrlvl_cntl_2)
 156                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 157         if (regs->ddr_wrlvl_cntl_3)
 158                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 159 #endif
 160
 161         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 162         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 163         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 164         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 165         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 166         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 167         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 168         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 169 #ifdef CONFIG_DEEP_SLEEP
 170         if (is_warm_boot()) {
 171                 ddr_out32(&ddr->sdram_cfg_2,
 172                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 173                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 174                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 175
 176                 /* DRAM VRef will not be trained */
 177                 ddr_out32(&ddr->ddr_cdr2,
 178                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 179         } else
 180 #endif
 181         {
 182                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 183                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 184                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 185                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 186         }
 187         ddr_out32(&ddr->err_disable, regs->err_disable);
 188         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 189         for (i = 0; i < 32; i++) {
 190                 if (regs->debug[i]) {
 191                         debug("Write to debug_%d as %08x\n",
 192                               i+1, regs->debug[i]);
 193                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 194                 }
 195         }
 196 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 197         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 198 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 199 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 200         if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 201             IS_DBI(regs->ddr_sdram_cfg_3))
 202                 ddr_setbits32(ddr->debug[28], 0x9 << 20);
 203 #endif
 204
 205         /*
 206          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 207          * deasserted. Clocks start when any chip select is enabled and clock
 208          * control register is set. Because all DDR components are connected to
 209          * one reset signal, this needs to be done in two steps. Step 1 is to
 210          * get the clocks started. Step 2 resumes after reset signal is
 211          * deasserted.
 212          */
 213         if (step == 1) {
 214                 udelay(200);
 215                 return;
 216         }
 217
 218 step2:
 219         /* Set, but do not enable the memory */
 220         temp_sdram_cfg = regs->ddr_sdram_cfg;
 221         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 222         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 223
 224         /*
 225          * 500 painful micro-seconds must elapse between
 226          * the DDR clock setup and the DDR config enable.
 227          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 228          * we choose the max, that is 500 us for all of case.
 229          */
 230         udelay(500);
 231         mb();
 232         isb();
 233
 234 #ifdef CONFIG_DEEP_SLEEP
 235         if (is_warm_boot()) {
 236                 /* enter self-refresh */
 237                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 238                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 239                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 240                 /* do board specific memory setup */
 241                 board_mem_sleep_setup();
 242
 243                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 244         } else
 245 #endif
 246                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 247         /* Let the controller go */
 248         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 249         mb();
 250         isb();
 251
 252         total_gb_size_per_controller = 0;
 253         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 254                 if (!(regs->cs[i].config & 0x80000000))
 255                         continue;
 256                 total_gb_size_per_controller += 1 << (
 257                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 258                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 259                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 260                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 261                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 262                         26);                    /* minus 26 (count of 64M) */
 263         }
 264         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 265                 total_gb_size_per_controller *= 3;
 266         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 267                 total_gb_size_per_controller <<= 1;
 268         /*
 269          * total memory / bus width = transactions needed
 270          * transactions needed / data rate = seconds
 271          * to add plenty of buffer, double the time
 272          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 273          * Let's wait for 800ms
 274          */
 275         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 276                         >> SDRAM_CFG_DBW_SHIFT);
 277         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 278                 (get_ddr_freq(0) >> 20)) << 2;
 279         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 280         debug("total %d GB\n", total_gb_size_per_controller);
 281         debug("Need to wait up to %d * 10ms\n", timeout);
 282
 283         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 284         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 285                 (timeout >= 0)) {
 286                 udelay(10000);          /* throttle polling rate */
 287                 timeout--;
 288         }
 289
 290         if (timeout <= 0)
 291                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 292 #ifdef CONFIG_DEEP_SLEEP
 293         if (is_warm_boot()) {
 294                 /* exit self-refresh */
 295                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 296                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 297                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 298         }
 299 #endif
 300 }