2 * Copyright 2008 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
8 #include <fsl_ddr_sdram.h>
13 * Calculate the Density of each Physical Rank.
14 * Returned size is in bytes.
16 * Study these table from Byte 31 of JEDEC SPD Spec.
30 * Reorder Table to be linear by stripping the bottom
31 * 2 or 5 bits off and shifting them up to the top.
34 static unsigned long long
35 compute_ranksize(unsigned int mem_type, unsigned char row_dens)
37 unsigned long long bsize;
39 /* Bottom 2 bits up to the top. */
40 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6));
42 debug("DDR: DDR I rank density = 0x%16llx\n", bsize);
48 * Convert a two-nibble BCD value into a cycle time.
49 * While the spec calls for nano-seconds, picos are returned.
51 * This implements the tables for bytes 9, 23 and 25 for both
52 * DDR I and II. No allowance for distinguishing the invalid
53 * fields absent for DDR I yet present in DDR II is made.
54 * (That is, cycle times of .25, .33, .66 and .75 ns are
55 * allowed for both DDR II and I.)
58 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
60 /* Table look up the lower nibble, allow DDR I & II. */
61 unsigned int tenths_ps[16] = {
72 250, /* This and the next 3 entries valid ... */
73 330, /* ... only for tCK calculations. */
80 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
81 unsigned int tenth_ns = spd_val & 0x0F;
82 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
88 convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
90 unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
91 unsigned int hundredth_ns = spd_val & 0x0F;
92 unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
97 static unsigned int byte40_table_ps[8] = {
104 0, /* supposed to be RFC, but not sure what that means */
109 compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111 return ((trctrfc_ext & 0x1) * 256 + trfc) * 1000
112 + byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
116 compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
118 return trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
122 * tCKmax from DDR I SPD Byte 43
124 * Bits 7:2 == whole ns
125 * Bits 1:0 == quarter ns
131 * Returns picoseconds.
134 compute_tckmax_from_spd_ps(unsigned int byte43)
136 return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250;
140 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
141 * Table from SPD Spec, Byte 12, converted to picoseconds and
142 * filled in with "default" normal values.
145 determine_refresh_rate_ps(const unsigned int spd_refresh)
147 unsigned int refresh_time_ps[8] = {
148 15625000, /* 0 Normal 1.00x */
149 3900000, /* 1 Reduced .25x */
150 7800000, /* 2 Extended .50x */
151 31300000, /* 3 Extended 2.00x */
152 62500000, /* 4 Extended 4.00x */
153 125000000, /* 5 Extended 8.00x */
154 15625000, /* 6 Normal 1.00x filler */
155 15625000, /* 7 Normal 1.00x filler */
158 return refresh_time_ps[spd_refresh & 0x7];
162 * The purpose of this function is to compute a suitable
163 * CAS latency given the DRAM clock period. The SPD only
164 * defines at most 3 CAS latencies. Typically the slower in
165 * frequency the DIMM runs at, the shorter its CAS latency can be.
166 * If the DIMM is operating at a sufficiently low frequency,
167 * it may be able to run at a CAS latency shorter than the
168 * shortest SPD-defined CAS latency.
170 * If a CAS latency is not found, 0 is returned.
172 * Do this by finding in the standard speed bin table the longest
173 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
175 * An assumption made is that the SDRAM device allows the
176 * CL to be programmed for a value that is lower than those
177 * advertised by the SPD. This is not always the case,
178 * as those modes not defined in the SPD are optional.
180 * CAS latency de-rating based upon values JEDEC Standard No. 79-E
183 * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2
185 /* CL2.0 CL2.5 CL3.0 */
186 unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 };
189 compute_derated_DDR1_CAS_latency(unsigned int mclk_ps)
191 const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins);
192 unsigned int lowest_tCKmin_found = 0;
193 unsigned int lowest_tCKmin_CL = 0;
196 debug("mclk_ps = %u\n", mclk_ps);
198 for (i = 0; i < num_speed_bins; i++) {
199 unsigned int x = ddr1_speed_bins[i];
200 debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
201 i, x, lowest_tCKmin_found);
202 if (x && lowest_tCKmin_found <= x && x <= mclk_ps) {
203 lowest_tCKmin_found = x;
204 lowest_tCKmin_CL = i + 1;
208 debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
210 return lowest_tCKmin_CL;
214 * ddr_compute_dimm_parameters for DDR1 SPD
216 * Compute DIMM parameters based upon the SPD information in spd.
217 * Writes the results to the dimm_params_t structure pointed by pdimm.
219 * FIXME: use #define for the retvals
221 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
222 const ddr1_spd_eeprom_t *spd,
223 dimm_params_t *pdimm,
224 unsigned int dimm_number)
229 if (spd->mem_type != SPD_MEMTYPE_DDR) {
230 printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number);
234 memset(pdimm, 0, sizeof(dimm_params_t));
238 retval = ddr1_spd_check(spd);
240 printf("DIMM %u: failed checksum\n", dimm_number);
245 * The part name in ASCII in the SPD EEPROM is not null terminated.
246 * Guarantee null termination here by presetting all bytes to 0
247 * and copying the part name in ASCII from the SPD onto it
249 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
250 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
252 /* DIMM organization parameters */
253 pdimm->n_ranks = spd->nrows;
254 pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens);
255 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
256 pdimm->data_width = spd->dataw_lsb;
257 pdimm->primary_sdram_width = spd->primw;
258 pdimm->ec_sdram_width = spd->ecw;
261 * FIXME: Need to determine registered_dimm status.
262 * 1 == register buffered
265 pdimm->registered_dimm = 0; /* unbuffered */
267 /* SDRAM device parameters */
268 pdimm->n_row_addr = spd->nrow_addr;
269 pdimm->n_col_addr = spd->ncol_addr;
270 pdimm->n_banks_per_sdram_device = spd->nbanks;
271 pdimm->edc_config = spd->config;
272 pdimm->burst_lengths_bitmask = spd->burstl;
273 pdimm->row_density = spd->bank_dens;
276 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
277 * The SPD clk_cycle field (tCKmin) is measured in tenths of
278 * nanoseconds and represented as BCD.
281 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
282 pdimm->tckmin_x_minus_1_ps
283 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
284 pdimm->tckmin_x_minus_2_ps
285 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
287 pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
290 * Compute CAS latencies defined by SPD
291 * The SPD caslat_x should have at least 1 and at most 3 bits set.
293 * If cas_lat after masking is 0, the __ilog2 function returns
294 * 255 into the variable. This behavior is abused once.
296 pdimm->caslat_x = __ilog2(spd->cas_lat);
297 pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
298 & ~(1 << pdimm->caslat_x));
299 pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
300 & ~(1 << pdimm->caslat_x)
301 & ~(1 << pdimm->caslat_x_minus_1));
303 /* Compute CAS latencies below that defined by SPD */
304 pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency(
305 get_memory_clk_period_ps(ctrl_num));
307 /* Compute timing parameters */
308 pdimm->trcd_ps = spd->trcd * 250;
309 pdimm->trp_ps = spd->trp * 250;
310 pdimm->tras_ps = spd->tras * 1000;
312 pdimm->twr_ps = mclk_to_picos(ctrl_num, 3);
313 pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1);
314 pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
316 pdimm->trrd_ps = spd->trrd * 250;
317 pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
319 pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
321 pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
322 pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
324 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
326 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
328 pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */
329 pdimm->tdqsq_max_ps = spd->tdqsq * 10;
330 pdimm->tqhs_ps = spd->tqhs * 10;