2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
14 #include <fsl_ddr_sdram.h>
17 #include <fsl_immap.h>
21 * Determine Rtt value.
23 * This should likely be either board or controller specific.
25 * Rtt(nominal) - DDR2:
30 * Rtt(nominal) - DDR3:
38 * FIXME: Apparently 8641 needs a value of 2
39 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
41 * FIXME: There was some effort down this line earlier:
44 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
45 * if (popts->dimmslot[i].num_valid_cs
46 * && (popts->cs_local_opts[2*i].odt_rd_cfg
47 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
53 static inline int fsl_ddr_get_rtt(void)
57 #if defined(CONFIG_SYS_FSL_DDR1)
59 #elif defined(CONFIG_SYS_FSL_DDR2)
68 #ifdef CONFIG_SYS_FSL_DDR4
70 * compute CAS write latency according to DDR4 spec
71 * CWL = 9 for <= 1600MT/s
79 static inline unsigned int compute_cas_write_latency(
80 const unsigned int ctrl_num)
83 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
86 else if (mclk_ps >= 1070)
88 else if (mclk_ps >= 935)
90 else if (mclk_ps >= 833)
92 else if (mclk_ps >= 750)
94 else if (mclk_ps >= 681)
103 * compute the CAS write latency according to DDR3 spec
104 * CWL = 5 if tCK >= 2.5ns
105 * 6 if 2.5ns > tCK >= 1.875ns
106 * 7 if 1.875ns > tCK >= 1.5ns
107 * 8 if 1.5ns > tCK >= 1.25ns
108 * 9 if 1.25ns > tCK >= 1.07ns
109 * 10 if 1.07ns > tCK >= 0.935ns
110 * 11 if 0.935ns > tCK >= 0.833ns
111 * 12 if 0.833ns > tCK >= 0.75ns
113 static inline unsigned int compute_cas_write_latency(
114 const unsigned int ctrl_num)
117 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
121 else if (mclk_ps >= 1875)
123 else if (mclk_ps >= 1500)
125 else if (mclk_ps >= 1250)
127 else if (mclk_ps >= 1070)
129 else if (mclk_ps >= 935)
131 else if (mclk_ps >= 833)
133 else if (mclk_ps >= 750)
137 printf("Warning: CWL is out of range\n");
143 /* Chip Select Configuration (CSn_CONFIG) */
144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
145 const memctl_options_t *popts,
146 const dimm_params_t *dimm_params)
148 unsigned int cs_n_en = 0; /* Chip Select enable */
149 unsigned int intlv_en = 0; /* Memory controller interleave enable */
150 unsigned int intlv_ctl = 0; /* Interleaving control */
151 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
152 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
153 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
154 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
155 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
156 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
158 #ifdef CONFIG_SYS_FSL_DDR4
159 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
161 unsigned int n_banks_per_sdram_device;
164 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
167 if (dimm_params[dimm_number].n_ranks > 0) {
169 /* These fields only available in CS0_CONFIG */
170 if (!popts->memctl_interleaving)
172 switch (popts->memctl_interleaving_mode) {
173 case FSL_DDR_256B_INTERLEAVING:
174 case FSL_DDR_CACHE_LINE_INTERLEAVING:
175 case FSL_DDR_PAGE_INTERLEAVING:
176 case FSL_DDR_BANK_INTERLEAVING:
177 case FSL_DDR_SUPERBANK_INTERLEAVING:
178 intlv_en = popts->memctl_interleaving;
179 intlv_ctl = popts->memctl_interleaving_mode;
187 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
188 (dimm_number == 1 && dimm_params[1].n_ranks > 0))
192 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
193 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
197 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
198 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
199 (dimm_number == 3 && dimm_params[3].n_ranks > 0))
207 ap_n_en = popts->cs_local_opts[i].auto_precharge;
208 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
209 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
210 #ifdef CONFIG_SYS_FSL_DDR4
211 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
212 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
214 n_banks_per_sdram_device
215 = dimm_params[dimm_number].n_banks_per_sdram_device;
216 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
218 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
219 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
221 ddr->cs[i].config = (0
222 | ((cs_n_en & 0x1) << 31)
223 | ((intlv_en & 0x3) << 29)
224 | ((intlv_ctl & 0xf) << 24)
225 | ((ap_n_en & 0x1) << 23)
227 /* XXX: some implementation only have 1 bit starting at left */
228 | ((odt_rd_cfg & 0x7) << 20)
230 /* XXX: Some implementation only have 1 bit starting at left */
231 | ((odt_wr_cfg & 0x7) << 16)
233 | ((ba_bits_cs_n & 0x3) << 14)
234 | ((row_bits_cs_n & 0x7) << 8)
235 #ifdef CONFIG_SYS_FSL_DDR4
236 | ((bg_bits_cs_n & 0x3) << 4)
238 | ((col_bits_cs_n & 0x7) << 0)
240 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
247 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
249 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
250 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
255 #if !defined(CONFIG_SYS_FSL_DDR1)
257 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
258 * Return 1 if other two slots configuration. Return 0 if single slot.
260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
263 if (dimm_params[0].n_ranks == 4)
267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
268 if ((dimm_params[0].n_ranks == 2) &&
269 (dimm_params[1].n_ranks == 2))
272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
273 if (dimm_params[0].n_ranks == 4)
277 if ((dimm_params[0].n_ranks != 0) &&
278 (dimm_params[2].n_ranks != 0))
285 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
287 * Avoid writing for DDR I. The new PQ38 DDR controller
288 * dreams up non-zero default values to be backwards compatible.
290 static void set_timing_cfg_0(const unsigned int ctrl_num,
291 fsl_ddr_cfg_regs_t *ddr,
292 const memctl_options_t *popts,
293 const dimm_params_t *dimm_params)
295 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
296 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
297 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
298 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
299 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
301 /* Active powerdown exit timing (tXARD and tXARDS). */
302 unsigned char act_pd_exit_mclk;
303 /* Precharge powerdown exit timing (tXP). */
304 unsigned char pre_pd_exit_mclk;
305 /* ODT powerdown exit timing (tAXPD). */
306 unsigned char taxpd_mclk = 0;
307 /* Mode register set cycle time (tMRD). */
308 unsigned char tmrd_mclk;
309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
310 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
313 #ifdef CONFIG_SYS_FSL_DDR4
314 /* tXP=max(4nCK, 6ns) */
315 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
318 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
319 pre_pd_exit_mclk = act_pd_exit_mclk;
321 * MRS_CYC = max(tMRD, tMOD)
322 * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
324 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
325 #elif defined(CONFIG_SYS_FSL_DDR3)
326 unsigned int data_rate = get_ddr_freq(ctrl_num);
331 * (tXARD and tXARDS). Empirical?
332 * The DDR3 spec has not tXARD,
333 * we use the tXP instead of it.
334 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
335 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
336 * spec has not the tAXPD, we use
337 * tAXPD=1, need design to confirm.
339 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
341 ip_rev = fsl_ddr_get_version();
342 if (ip_rev >= 0x40700) {
344 * MRS_CYC = max(tMRD, tMOD)
345 * tMRD = 4nCK (8nCK for RDIMM)
346 * tMOD = max(12nCK, 15ns)
348 tmrd_mclk = max((unsigned int)12,
349 picos_to_mclk(ctrl_num, 15000));
353 * tMRD = 4nCK (8nCK for RDIMM)
355 if (popts->registered_dimm_en)
361 /* set the turnaround time */
364 * for single quad-rank DIMM and two-slot DIMMs
365 * to avoid ODT overlap
367 odt_overlap = avoid_odt_overlap(dimm_params);
368 switch (odt_overlap) {
381 /* for faster clock, need more time for data setup */
382 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
384 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
387 if (popts->dynamic_power == 0) { /* powerdown is not used */
388 act_pd_exit_mclk = 1;
389 pre_pd_exit_mclk = 1;
392 /* act_pd_exit_mclk = tXARD, see above */
393 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
394 /* Mode register MR0[A12] is '1' - fast exit */
395 pre_pd_exit_mclk = act_pd_exit_mclk;
398 #else /* CONFIG_SYS_FSL_DDR2 */
400 * (tXARD and tXARDS). Empirical?
405 act_pd_exit_mclk = 2;
406 pre_pd_exit_mclk = 2;
411 if (popts->trwt_override)
412 trwt_mclk = popts->trwt;
414 ddr->timing_cfg_0 = (0
415 | ((trwt_mclk & 0x3) << 30) /* RWT */
416 | ((twrt_mclk & 0x3) << 28) /* WRT */
417 | ((trrt_mclk & 0x3) << 26) /* RRT */
418 | ((twwt_mclk & 0x3) << 24) /* WWT */
419 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */
420 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
421 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
422 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */
424 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
426 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */
428 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
429 static void set_timing_cfg_3(const unsigned int ctrl_num,
430 fsl_ddr_cfg_regs_t *ddr,
431 const memctl_options_t *popts,
432 const common_timing_params_t *common_dimm,
433 unsigned int cas_latency,
434 unsigned int additive_latency)
436 /* Extended precharge to activate interval (tRP) */
437 unsigned int ext_pretoact = 0;
438 /* Extended Activate to precharge interval (tRAS) */
439 unsigned int ext_acttopre = 0;
440 /* Extended activate to read/write interval (tRCD) */
441 unsigned int ext_acttorw = 0;
442 /* Extended refresh recovery time (tRFC) */
443 unsigned int ext_refrec;
444 /* Extended MCAS latency from READ cmd */
445 unsigned int ext_caslat = 0;
446 /* Extended additive latency */
447 unsigned int ext_add_lat = 0;
448 /* Extended last data to precharge interval (tWR) */
449 unsigned int ext_wrrec = 0;
451 unsigned int cntl_adj = 0;
453 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
454 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
455 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
456 ext_caslat = (2 * cas_latency - 1) >> 4;
457 ext_add_lat = additive_latency >> 4;
458 #ifdef CONFIG_SYS_FSL_DDR4
459 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
461 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
462 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
464 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
465 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
467 ddr->timing_cfg_3 = (0
468 | ((ext_pretoact & 0x1) << 28)
469 | ((ext_acttopre & 0x3) << 24)
470 | ((ext_acttorw & 0x1) << 22)
471 | ((ext_refrec & 0x1F) << 16)
472 | ((ext_caslat & 0x3) << 12)
473 | ((ext_add_lat & 0x1) << 10)
474 | ((ext_wrrec & 0x1) << 8)
475 | ((cntl_adj & 0x7) << 0)
477 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
480 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
481 static void set_timing_cfg_1(const unsigned int ctrl_num,
482 fsl_ddr_cfg_regs_t *ddr,
483 const memctl_options_t *popts,
484 const common_timing_params_t *common_dimm,
485 unsigned int cas_latency)
487 /* Precharge-to-activate interval (tRP) */
488 unsigned char pretoact_mclk;
489 /* Activate to precharge interval (tRAS) */
490 unsigned char acttopre_mclk;
491 /* Activate to read/write interval (tRCD) */
492 unsigned char acttorw_mclk;
494 unsigned char caslat_ctrl;
495 /* Refresh recovery time (tRFC) ; trfc_low */
496 unsigned char refrec_ctrl;
497 /* Last data to precharge minimum interval (tWR) */
498 unsigned char wrrec_mclk;
499 /* Activate-to-activate interval (tRRD) */
500 unsigned char acttoact_mclk;
501 /* Last write data pair to read command issue interval (tWTR) */
502 unsigned char wrtord_mclk;
503 #ifdef CONFIG_SYS_FSL_DDR4
504 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
505 static const u8 wrrec_table[] = {
512 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
513 static const u8 wrrec_table[] = {
514 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
517 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
518 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
519 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
522 * Translate CAS Latency to a DDR controller field value:
524 * CAS Lat DDR I DDR II Ctrl
525 * Clocks SPD Bit SPD Bit Value
526 * ------- ------- ------- -----
537 #if defined(CONFIG_SYS_FSL_DDR1)
538 caslat_ctrl = (cas_latency + 1) & 0x07;
539 #elif defined(CONFIG_SYS_FSL_DDR2)
540 caslat_ctrl = 2 * cas_latency - 1;
543 * if the CAS latency more than 8 cycle,
544 * we need set extend bit for it at
545 * TIMING_CFG_3[EXT_CASLAT]
547 if (fsl_ddr_get_version() <= 0x40400)
548 caslat_ctrl = 2 * cas_latency - 1;
550 caslat_ctrl = (cas_latency - 1) << 1;
553 #ifdef CONFIG_SYS_FSL_DDR4
554 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
555 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
556 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
557 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
558 if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
559 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
561 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
563 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
564 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
565 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
566 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
567 if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
568 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
570 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
572 if (popts->otf_burst_chop_en)
576 * JEDEC has min requirement for tRRD
578 #if defined(CONFIG_SYS_FSL_DDR3)
579 if (acttoact_mclk < 4)
583 * JEDEC has some min requirements for tWTR
585 #if defined(CONFIG_SYS_FSL_DDR2)
588 #elif defined(CONFIG_SYS_FSL_DDR3)
592 if (popts->otf_burst_chop_en)
595 ddr->timing_cfg_1 = (0
596 | ((pretoact_mclk & 0x0F) << 28)
597 | ((acttopre_mclk & 0x0F) << 24)
598 | ((acttorw_mclk & 0xF) << 20)
599 | ((caslat_ctrl & 0xF) << 16)
600 | ((refrec_ctrl & 0xF) << 12)
601 | ((wrrec_mclk & 0x0F) << 8)
602 | ((acttoact_mclk & 0x0F) << 4)
603 | ((wrtord_mclk & 0x0F) << 0)
605 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
608 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
609 static void set_timing_cfg_2(const unsigned int ctrl_num,
610 fsl_ddr_cfg_regs_t *ddr,
611 const memctl_options_t *popts,
612 const common_timing_params_t *common_dimm,
613 unsigned int cas_latency,
614 unsigned int additive_latency)
616 /* Additive latency */
617 unsigned char add_lat_mclk;
618 /* CAS-to-preamble override */
621 unsigned char wr_lat;
622 /* Read to precharge (tRTP) */
623 unsigned char rd_to_pre;
624 /* Write command to write data strobe timing adjustment */
625 unsigned char wr_data_delay;
626 /* Minimum CKE pulse width (tCKE) */
627 unsigned char cke_pls;
628 /* Window for four activates (tFAW) */
629 unsigned short four_act;
630 #ifdef CONFIG_SYS_FSL_DDR3
631 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
634 /* FIXME add check that this must be less than acttorw_mclk */
635 add_lat_mclk = additive_latency;
636 cpo = popts->cpo_override;
638 #if defined(CONFIG_SYS_FSL_DDR1)
640 * This is a lie. It should really be 1, but if it is
641 * set to 1, bits overlap into the old controller's
642 * otherwise unused ACSM field. If we leave it 0, then
643 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
646 #elif defined(CONFIG_SYS_FSL_DDR2)
647 wr_lat = cas_latency - 1;
649 wr_lat = compute_cas_write_latency(ctrl_num);
652 #ifdef CONFIG_SYS_FSL_DDR4
653 rd_to_pre = picos_to_mclk(ctrl_num, 7500);
655 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
658 * JEDEC has some min requirements for tRTP
660 #if defined(CONFIG_SYS_FSL_DDR2)
663 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
667 if (popts->otf_burst_chop_en)
668 rd_to_pre += 2; /* according to UM */
670 wr_data_delay = popts->write_data_delay;
671 #ifdef CONFIG_SYS_FSL_DDR4
673 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
674 #elif defined(CONFIG_SYS_FSL_DDR3)
676 * cke pulse = max(3nCK, 7.5ns) for DDR3-800
677 * max(3nCK, 5.625ns) for DDR3-1066, 1333
678 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133
680 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
681 (mclk_ps > 1245 ? 5625 : 5000)));
683 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
685 four_act = picos_to_mclk(ctrl_num,
686 popts->tfaw_window_four_activates_ps);
688 ddr->timing_cfg_2 = (0
689 | ((add_lat_mclk & 0xf) << 28)
690 | ((cpo & 0x1f) << 23)
691 | ((wr_lat & 0xf) << 19)
692 | ((wr_lat & 0x10) << 14)
693 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
694 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
695 | ((cke_pls & 0x7) << 6)
696 | ((four_act & 0x3f) << 0)
698 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
701 /* DDR SDRAM Register Control Word */
702 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
703 const memctl_options_t *popts,
704 const common_timing_params_t *common_dimm)
706 if (common_dimm->all_dimms_registered &&
707 !common_dimm->all_dimms_unbuffered) {
708 if (popts->rcw_override) {
709 ddr->ddr_sdram_rcw_1 = popts->rcw_1;
710 ddr->ddr_sdram_rcw_2 = popts->rcw_2;
712 ddr->ddr_sdram_rcw_1 =
713 common_dimm->rcw[0] << 28 | \
714 common_dimm->rcw[1] << 24 | \
715 common_dimm->rcw[2] << 20 | \
716 common_dimm->rcw[3] << 16 | \
717 common_dimm->rcw[4] << 12 | \
718 common_dimm->rcw[5] << 8 | \
719 common_dimm->rcw[6] << 4 | \
721 ddr->ddr_sdram_rcw_2 =
722 common_dimm->rcw[8] << 28 | \
723 common_dimm->rcw[9] << 24 | \
724 common_dimm->rcw[10] << 20 | \
725 common_dimm->rcw[11] << 16 | \
726 common_dimm->rcw[12] << 12 | \
727 common_dimm->rcw[13] << 8 | \
728 common_dimm->rcw[14] << 4 | \
729 common_dimm->rcw[15];
731 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
732 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
736 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
737 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
738 const memctl_options_t *popts,
739 const common_timing_params_t *common_dimm)
741 unsigned int mem_en; /* DDR SDRAM interface logic enable */
742 unsigned int sren; /* Self refresh enable (during sleep) */
743 unsigned int ecc_en; /* ECC enable. */
744 unsigned int rd_en; /* Registered DIMM enable */
745 unsigned int sdram_type; /* Type of SDRAM */
746 unsigned int dyn_pwr; /* Dynamic power management mode */
747 unsigned int dbw; /* DRAM dta bus width */
748 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
749 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
750 unsigned int threet_en; /* Enable 3T timing */
751 unsigned int twot_en; /* Enable 2T timing */
752 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
753 unsigned int x32_en = 0; /* x32 enable */
754 unsigned int pchb8 = 0; /* precharge bit 8 enable */
755 unsigned int hse; /* Global half strength override */
756 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */
757 unsigned int mem_halt = 0; /* memory controller halt */
758 unsigned int bi = 0; /* Bypass initialization */
761 sren = popts->self_refresh_in_sleep;
762 if (common_dimm->all_dimms_ecc_capable) {
763 /* Allow setting of ECC only if all DIMMs are ECC. */
764 ecc_en = popts->ecc_mode;
769 if (common_dimm->all_dimms_registered &&
770 !common_dimm->all_dimms_unbuffered) {
775 twot_en = popts->twot_en;
778 sdram_type = CONFIG_FSL_SDRAM_TYPE;
780 dyn_pwr = popts->dynamic_power;
781 dbw = popts->data_bus_width;
782 /* 8-beat burst enable DDR-III case
783 * we must clear it when use the on-the-fly mode,
784 * must set it when use the 32-bits bus mode.
786 if ((sdram_type == SDRAM_TYPE_DDR3) ||
787 (sdram_type == SDRAM_TYPE_DDR4)) {
788 if (popts->burst_length == DDR_BL8)
790 if (popts->burst_length == DDR_OTF)
796 threet_en = popts->threet_en;
797 ba_intlv_ctl = popts->ba_intlv_ctl;
798 hse = popts->half_strength_driver_enable;
800 /* set when ddr bus width < 64 */
801 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
803 ddr->ddr_sdram_cfg = (0
804 | ((mem_en & 0x1) << 31)
805 | ((sren & 0x1) << 30)
806 | ((ecc_en & 0x1) << 29)
807 | ((rd_en & 0x1) << 28)
808 | ((sdram_type & 0x7) << 24)
809 | ((dyn_pwr & 0x1) << 21)
810 | ((dbw & 0x3) << 19)
811 | ((eight_be & 0x1) << 18)
812 | ((ncap & 0x1) << 17)
813 | ((threet_en & 0x1) << 16)
814 | ((twot_en & 0x1) << 15)
815 | ((ba_intlv_ctl & 0x7F) << 8)
816 | ((x32_en & 0x1) << 5)
817 | ((pchb8 & 0x1) << 4)
819 | ((acc_ecc_en & 0x1) << 2)
820 | ((mem_halt & 0x1) << 1)
823 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
826 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
827 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
828 fsl_ddr_cfg_regs_t *ddr,
829 const memctl_options_t *popts,
830 const unsigned int unq_mrs_en)
832 unsigned int frc_sr = 0; /* Force self refresh */
833 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
834 unsigned int odt_cfg = 0; /* ODT configuration */
835 unsigned int num_pr; /* Number of posted refreshes */
836 unsigned int slow = 0; /* DDR will be run less than 1250 */
837 unsigned int x4_en = 0; /* x4 DRAM enable */
838 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
839 unsigned int ap_en; /* Address Parity Enable */
840 unsigned int d_init; /* DRAM data initialization */
841 unsigned int rcw_en = 0; /* Register Control Word Enable */
842 unsigned int md_en = 0; /* Mirrored DIMM Enable */
843 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
845 #ifndef CONFIG_SYS_FSL_DDR4
846 unsigned int dll_rst_dis = 1; /* DLL reset disable */
847 unsigned int dqs_cfg; /* DQS configuration */
849 dqs_cfg = popts->dqs_config;
851 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
852 if (popts->cs_local_opts[i].odt_rd_cfg
853 || popts->cs_local_opts[i].odt_wr_cfg) {
854 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
859 num_pr = 1; /* Make this configurable */
863 * {TIMING_CFG_1[PRETOACT]
864 * + [DDR_SDRAM_CFG_2[NUM_PR]
865 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
866 * << DDR_SDRAM_INTERVAL[REFINT]
868 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
869 obc_cfg = popts->otf_burst_chop_en;
874 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
875 slow = get_ddr_freq(ctrl_num) < 1249000000;
878 if (popts->registered_dimm_en) {
880 ap_en = popts->ap_en;
885 x4_en = popts->x4_en ? 1 : 0;
887 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
888 /* Use the DDR controller to auto initialize memory. */
889 d_init = popts->ecc_init_using_memctl;
890 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
891 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
893 /* Memory will be initialized via DMA, or not at all. */
897 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
898 md_en = popts->mirrored_dimm;
900 qd_en = popts->quad_rank_present ? 1 : 0;
901 ddr->ddr_sdram_cfg_2 = (0
902 | ((frc_sr & 0x1) << 31)
903 | ((sr_ie & 0x1) << 30)
904 #ifndef CONFIG_SYS_FSL_DDR4
905 | ((dll_rst_dis & 0x1) << 29)
906 | ((dqs_cfg & 0x3) << 26)
908 | ((odt_cfg & 0x3) << 21)
909 | ((num_pr & 0xf) << 12)
914 | ((obc_cfg & 0x1) << 6)
915 | ((ap_en & 0x1) << 5)
916 | ((d_init & 0x1) << 4)
917 | ((rcw_en & 0x1) << 2)
918 | ((md_en & 0x1) << 0)
920 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
923 #ifdef CONFIG_SYS_FSL_DDR4
924 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
925 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
926 fsl_ddr_cfg_regs_t *ddr,
927 const memctl_options_t *popts,
928 const common_timing_params_t *common_dimm,
929 const unsigned int unq_mrs_en)
931 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
932 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
934 unsigned int wr_crc = 0; /* Disable */
935 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
936 unsigned int srt = 0; /* self-refresh temerature, normal range */
937 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
938 unsigned int mpr = 0; /* serial */
940 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
942 if (popts->rtt_override)
943 rtt_wr = popts->rtt_wr_override_value;
945 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
947 if (common_dimm->extended_op_srt)
948 srt = common_dimm->extended_op_srt;
951 | ((wr_crc & 0x1) << 12)
952 | ((rtt_wr & 0x3) << 9)
954 | ((cwl & 0x7) << 3));
958 else if (mclk_ps >= 833)
964 | ((mpr & 0x3) << 11)
965 | ((wc_lat & 0x3) << 9));
967 ddr->ddr_sdram_mode_2 = (0
968 | ((esdmode2 & 0xFFFF) << 16)
969 | ((esdmode3 & 0xFFFF) << 0)
971 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
973 if (unq_mrs_en) { /* unique mode registers are supported */
974 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
975 if (popts->rtt_override)
976 rtt_wr = popts->rtt_wr_override_value;
978 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
980 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
981 esdmode2 |= (rtt_wr & 0x3) << 9;
984 ddr->ddr_sdram_mode_4 = (0
985 | ((esdmode2 & 0xFFFF) << 16)
986 | ((esdmode3 & 0xFFFF) << 0)
990 ddr->ddr_sdram_mode_6 = (0
991 | ((esdmode2 & 0xFFFF) << 16)
992 | ((esdmode3 & 0xFFFF) << 0)
996 ddr->ddr_sdram_mode_8 = (0
997 | ((esdmode2 & 0xFFFF) << 16)
998 | ((esdmode3 & 0xFFFF) << 0)
1003 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1004 ddr->ddr_sdram_mode_4);
1005 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1006 ddr->ddr_sdram_mode_6);
1007 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1008 ddr->ddr_sdram_mode_8);
1011 #elif defined(CONFIG_SYS_FSL_DDR3)
1012 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1013 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1014 fsl_ddr_cfg_regs_t *ddr,
1015 const memctl_options_t *popts,
1016 const common_timing_params_t *common_dimm,
1017 const unsigned int unq_mrs_en)
1019 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1020 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1022 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
1023 unsigned int srt = 0; /* self-refresh temerature, normal range */
1024 unsigned int asr = 0; /* auto self-refresh disable */
1025 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1026 unsigned int pasr = 0; /* partial array self refresh disable */
1028 if (popts->rtt_override)
1029 rtt_wr = popts->rtt_wr_override_value;
1031 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1033 if (common_dimm->extended_op_srt)
1034 srt = common_dimm->extended_op_srt;
1037 | ((rtt_wr & 0x3) << 9)
1038 | ((srt & 0x1) << 7)
1039 | ((asr & 0x1) << 6)
1040 | ((cwl & 0x7) << 3)
1041 | ((pasr & 0x7) << 0));
1042 ddr->ddr_sdram_mode_2 = (0
1043 | ((esdmode2 & 0xFFFF) << 16)
1044 | ((esdmode3 & 0xFFFF) << 0)
1046 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1048 if (unq_mrs_en) { /* unique mode registers are supported */
1049 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1050 if (popts->rtt_override)
1051 rtt_wr = popts->rtt_wr_override_value;
1053 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1055 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
1056 esdmode2 |= (rtt_wr & 0x3) << 9;
1059 ddr->ddr_sdram_mode_4 = (0
1060 | ((esdmode2 & 0xFFFF) << 16)
1061 | ((esdmode3 & 0xFFFF) << 0)
1065 ddr->ddr_sdram_mode_6 = (0
1066 | ((esdmode2 & 0xFFFF) << 16)
1067 | ((esdmode3 & 0xFFFF) << 0)
1071 ddr->ddr_sdram_mode_8 = (0
1072 | ((esdmode2 & 0xFFFF) << 16)
1073 | ((esdmode3 & 0xFFFF) << 0)
1078 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1079 ddr->ddr_sdram_mode_4);
1080 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1081 ddr->ddr_sdram_mode_6);
1082 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1083 ddr->ddr_sdram_mode_8);
1087 #else /* for DDR2 and DDR1 */
1088 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1089 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1090 fsl_ddr_cfg_regs_t *ddr,
1091 const memctl_options_t *popts,
1092 const common_timing_params_t *common_dimm,
1093 const unsigned int unq_mrs_en)
1095 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
1096 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
1098 ddr->ddr_sdram_mode_2 = (0
1099 | ((esdmode2 & 0xFFFF) << 16)
1100 | ((esdmode3 & 0xFFFF) << 0)
1102 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1106 #ifdef CONFIG_SYS_FSL_DDR4
1107 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1108 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1109 const memctl_options_t *popts,
1110 const common_timing_params_t *common_dimm,
1111 const unsigned int unq_mrs_en)
1114 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */
1115 unsigned short esdmode5; /* Extended SDRAM mode 5 */
1117 esdmode5 = 0x00000400; /* Data mask enabled */
1119 ddr->ddr_sdram_mode_9 = (0
1120 | ((esdmode4 & 0xffff) << 16)
1121 | ((esdmode5 & 0xffff) << 0)
1123 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1124 if (unq_mrs_en) { /* unique mode registers are supported */
1125 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1128 ddr->ddr_sdram_mode_11 = (0
1129 | ((esdmode4 & 0xFFFF) << 16)
1130 | ((esdmode5 & 0xFFFF) << 0)
1134 ddr->ddr_sdram_mode_13 = (0
1135 | ((esdmode4 & 0xFFFF) << 16)
1136 | ((esdmode5 & 0xFFFF) << 0)
1140 ddr->ddr_sdram_mode_15 = (0
1141 | ((esdmode4 & 0xFFFF) << 16)
1142 | ((esdmode5 & 0xFFFF) << 0)
1147 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1148 ddr->ddr_sdram_mode_11);
1149 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1150 ddr->ddr_sdram_mode_13);
1151 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1152 ddr->ddr_sdram_mode_15);
1156 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1157 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1158 fsl_ddr_cfg_regs_t *ddr,
1159 const memctl_options_t *popts,
1160 const common_timing_params_t *common_dimm,
1161 const unsigned int unq_mrs_en)
1164 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */
1165 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */
1166 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1168 esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1170 ddr->ddr_sdram_mode_10 = (0
1171 | ((esdmode6 & 0xffff) << 16)
1172 | ((esdmode7 & 0xffff) << 0)
1174 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1175 if (unq_mrs_en) { /* unique mode registers are supported */
1176 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1179 ddr->ddr_sdram_mode_12 = (0
1180 | ((esdmode6 & 0xFFFF) << 16)
1181 | ((esdmode7 & 0xFFFF) << 0)
1185 ddr->ddr_sdram_mode_14 = (0
1186 | ((esdmode6 & 0xFFFF) << 16)
1187 | ((esdmode7 & 0xFFFF) << 0)
1191 ddr->ddr_sdram_mode_16 = (0
1192 | ((esdmode6 & 0xFFFF) << 16)
1193 | ((esdmode7 & 0xFFFF) << 0)
1198 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1199 ddr->ddr_sdram_mode_12);
1200 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1201 ddr->ddr_sdram_mode_14);
1202 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1203 ddr->ddr_sdram_mode_16);
1209 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1210 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1211 fsl_ddr_cfg_regs_t *ddr,
1212 const memctl_options_t *popts,
1213 const common_timing_params_t *common_dimm)
1215 unsigned int refint; /* Refresh interval */
1216 unsigned int bstopre; /* Precharge interval */
1218 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1220 bstopre = popts->bstopre;
1222 /* refint field used 0x3FFF in earlier controllers */
1223 ddr->ddr_sdram_interval = (0
1224 | ((refint & 0xFFFF) << 16)
1225 | ((bstopre & 0x3FFF) << 0)
1227 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1230 #ifdef CONFIG_SYS_FSL_DDR4
1231 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1232 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1233 fsl_ddr_cfg_regs_t *ddr,
1234 const memctl_options_t *popts,
1235 const common_timing_params_t *common_dimm,
1236 unsigned int cas_latency,
1237 unsigned int additive_latency,
1238 const unsigned int unq_mrs_en)
1241 unsigned short esdmode; /* Extended SDRAM mode */
1242 unsigned short sdmode; /* SDRAM mode */
1244 /* Mode Register - MR1 */
1245 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1246 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1248 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1249 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1250 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1251 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal),
1252 0=Disable (Test/Debug) */
1254 /* Mode Register - MR0 */
1255 unsigned int wr = 0; /* Write Recovery */
1256 unsigned int dll_rst; /* DLL Reset */
1257 unsigned int mode; /* Normal=0 or Test=1 */
1258 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1259 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1261 unsigned int bl; /* BL: Burst Length */
1263 unsigned int wr_mclk;
1264 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1265 static const u8 wr_table[] = {
1266 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1267 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1268 static const u8 cas_latency_table[] = {
1269 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1270 9, 9, 10, 10, 11, 11};
1272 if (popts->rtt_override)
1273 rtt = popts->rtt_override_value;
1275 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1277 if (additive_latency == (cas_latency - 1))
1279 if (additive_latency == (cas_latency - 2))
1282 if (popts->quad_rank_present)
1283 dic = 1; /* output driver impedance 240/7 ohm */
1286 * The esdmode value will also be used for writing
1287 * MR1 during write leveling for DDR3, although the
1288 * bits specifically related to the write leveling
1289 * scheme will be handled automatically by the DDR
1290 * controller. so we set the wrlvl_en = 0 here.
1293 | ((qoff & 0x1) << 12)
1294 | ((tdqs_en & 0x1) << 11)
1295 | ((rtt & 0x7) << 8)
1296 | ((wrlvl_en & 0x1) << 7)
1298 | ((dic & 0x3) << 1) /* DIC field is split */
1299 | ((dll_en & 0x1) << 0)
1303 * DLL control for precharge PD
1304 * 0=slow exit DLL off (tXPDLL)
1305 * 1=fast exit DLL on (tXP)
1308 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1309 if (wr_mclk <= 24) {
1310 wr = wr_table[wr_mclk - 10];
1312 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1316 dll_rst = 0; /* dll no reset */
1317 mode = 0; /* normal mode */
1319 /* look up table to get the cas latency bits */
1320 if (cas_latency >= 9 && cas_latency <= 24)
1321 caslat = cas_latency_table[cas_latency - 9];
1323 printf("Error: unsupported cas latency for mode register\n");
1325 bt = 0; /* Nibble sequential */
1327 switch (popts->burst_length) {
1338 printf("Error: invalid burst length of %u specified. ",
1339 popts->burst_length);
1340 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1347 | ((dll_rst & 0x1) << 8)
1348 | ((mode & 0x1) << 7)
1349 | (((caslat >> 1) & 0x7) << 4)
1351 | ((caslat & 1) << 2)
1355 ddr->ddr_sdram_mode = (0
1356 | ((esdmode & 0xFFFF) << 16)
1357 | ((sdmode & 0xFFFF) << 0)
1360 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1362 if (unq_mrs_en) { /* unique mode registers are supported */
1363 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1364 if (popts->rtt_override)
1365 rtt = popts->rtt_override_value;
1367 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1369 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
1370 esdmode |= (rtt & 0x7) << 8;
1373 ddr->ddr_sdram_mode_3 = (0
1374 | ((esdmode & 0xFFFF) << 16)
1375 | ((sdmode & 0xFFFF) << 0)
1379 ddr->ddr_sdram_mode_5 = (0
1380 | ((esdmode & 0xFFFF) << 16)
1381 | ((sdmode & 0xFFFF) << 0)
1385 ddr->ddr_sdram_mode_7 = (0
1386 | ((esdmode & 0xFFFF) << 16)
1387 | ((sdmode & 0xFFFF) << 0)
1392 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1393 ddr->ddr_sdram_mode_3);
1394 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1395 ddr->ddr_sdram_mode_5);
1396 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1397 ddr->ddr_sdram_mode_5);
1401 #elif defined(CONFIG_SYS_FSL_DDR3)
1402 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1403 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1404 fsl_ddr_cfg_regs_t *ddr,
1405 const memctl_options_t *popts,
1406 const common_timing_params_t *common_dimm,
1407 unsigned int cas_latency,
1408 unsigned int additive_latency,
1409 const unsigned int unq_mrs_en)
1412 unsigned short esdmode; /* Extended SDRAM mode */
1413 unsigned short sdmode; /* SDRAM mode */
1415 /* Mode Register - MR1 */
1416 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
1417 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
1419 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
1420 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
1421 unsigned int dic = 0; /* Output driver impedance, 40ohm */
1422 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1423 1=Disable (Test/Debug) */
1425 /* Mode Register - MR0 */
1426 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
1427 unsigned int wr = 0; /* Write Recovery */
1428 unsigned int dll_rst; /* DLL Reset */
1429 unsigned int mode; /* Normal=0 or Test=1 */
1430 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1431 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1433 unsigned int bl; /* BL: Burst Length */
1435 unsigned int wr_mclk;
1437 * DDR_SDRAM_MODE doesn't support 9,11,13,15
1438 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1441 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1443 if (popts->rtt_override)
1444 rtt = popts->rtt_override_value;
1446 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1448 if (additive_latency == (cas_latency - 1))
1450 if (additive_latency == (cas_latency - 2))
1453 if (popts->quad_rank_present)
1454 dic = 1; /* output driver impedance 240/7 ohm */
1457 * The esdmode value will also be used for writing
1458 * MR1 during write leveling for DDR3, although the
1459 * bits specifically related to the write leveling
1460 * scheme will be handled automatically by the DDR
1461 * controller. so we set the wrlvl_en = 0 here.
1464 | ((qoff & 0x1) << 12)
1465 | ((tdqs_en & 0x1) << 11)
1466 | ((rtt & 0x4) << 7) /* rtt field is split */
1467 | ((wrlvl_en & 0x1) << 7)
1468 | ((rtt & 0x2) << 5) /* rtt field is split */
1469 | ((dic & 0x2) << 4) /* DIC field is split */
1471 | ((rtt & 0x1) << 2) /* rtt field is split */
1472 | ((dic & 0x1) << 1) /* DIC field is split */
1473 | ((dll_en & 0x1) << 0)
1477 * DLL control for precharge PD
1478 * 0=slow exit DLL off (tXPDLL)
1479 * 1=fast exit DLL on (tXP)
1483 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1484 if (wr_mclk <= 16) {
1485 wr = wr_table[wr_mclk - 5];
1487 printf("Error: unsupported write recovery for mode register "
1488 "wr_mclk = %d\n", wr_mclk);
1491 dll_rst = 0; /* dll no reset */
1492 mode = 0; /* normal mode */
1494 /* look up table to get the cas latency bits */
1495 if (cas_latency >= 5 && cas_latency <= 16) {
1496 unsigned char cas_latency_table[] = {
1502 0xc, /* 10 clocks */
1503 0xe, /* 11 clocks */
1504 0x1, /* 12 clocks */
1505 0x3, /* 13 clocks */
1506 0x5, /* 14 clocks */
1507 0x7, /* 15 clocks */
1508 0x9, /* 16 clocks */
1510 caslat = cas_latency_table[cas_latency - 5];
1512 printf("Error: unsupported cas latency for mode register\n");
1515 bt = 0; /* Nibble sequential */
1517 switch (popts->burst_length) {
1528 printf("Error: invalid burst length of %u specified. "
1529 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1530 popts->burst_length);
1536 | ((dll_on & 0x1) << 12)
1538 | ((dll_rst & 0x1) << 8)
1539 | ((mode & 0x1) << 7)
1540 | (((caslat >> 1) & 0x7) << 4)
1542 | ((caslat & 1) << 2)
1546 ddr->ddr_sdram_mode = (0
1547 | ((esdmode & 0xFFFF) << 16)
1548 | ((sdmode & 0xFFFF) << 0)
1551 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1553 if (unq_mrs_en) { /* unique mode registers are supported */
1554 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1555 if (popts->rtt_override)
1556 rtt = popts->rtt_override_value;
1558 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1560 esdmode &= 0xFDBB; /* clear bit 9,6,2 */
1562 | ((rtt & 0x4) << 7) /* rtt field is split */
1563 | ((rtt & 0x2) << 5) /* rtt field is split */
1564 | ((rtt & 0x1) << 2) /* rtt field is split */
1568 ddr->ddr_sdram_mode_3 = (0
1569 | ((esdmode & 0xFFFF) << 16)
1570 | ((sdmode & 0xFFFF) << 0)
1574 ddr->ddr_sdram_mode_5 = (0
1575 | ((esdmode & 0xFFFF) << 16)
1576 | ((sdmode & 0xFFFF) << 0)
1580 ddr->ddr_sdram_mode_7 = (0
1581 | ((esdmode & 0xFFFF) << 16)
1582 | ((sdmode & 0xFFFF) << 0)
1587 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1588 ddr->ddr_sdram_mode_3);
1589 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1590 ddr->ddr_sdram_mode_5);
1591 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1592 ddr->ddr_sdram_mode_5);
1596 #else /* !CONFIG_SYS_FSL_DDR3 */
1598 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1599 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1600 fsl_ddr_cfg_regs_t *ddr,
1601 const memctl_options_t *popts,
1602 const common_timing_params_t *common_dimm,
1603 unsigned int cas_latency,
1604 unsigned int additive_latency,
1605 const unsigned int unq_mrs_en)
1607 unsigned short esdmode; /* Extended SDRAM mode */
1608 unsigned short sdmode; /* SDRAM mode */
1611 * FIXME: This ought to be pre-calculated in a
1612 * technology-specific routine,
1613 * e.g. compute_DDR2_mode_register(), and then the
1614 * sdmode and esdmode passed in as part of common_dimm.
1617 /* Extended Mode Register */
1618 unsigned int mrs = 0; /* Mode Register Set */
1619 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
1620 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
1621 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
1622 unsigned int ocd = 0; /* 0x0=OCD not supported,
1623 0x7=OCD default state */
1625 unsigned int al; /* Posted CAS# additive latency (AL) */
1626 unsigned int ods = 0; /* Output Drive Strength:
1627 0 = Full strength (18ohm)
1628 1 = Reduced strength (4ohm) */
1629 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1630 1=Disable (Test/Debug) */
1632 /* Mode Register (MR) */
1633 unsigned int mr; /* Mode Register Definition */
1634 unsigned int pd; /* Power-Down Mode */
1635 unsigned int wr; /* Write Recovery */
1636 unsigned int dll_res; /* DLL Reset */
1637 unsigned int mode; /* Normal=0 or Test=1 */
1638 unsigned int caslat = 0;/* CAS# latency */
1639 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1641 unsigned int bl; /* BL: Burst Length */
1643 dqs_en = !popts->dqs_config;
1644 rtt = fsl_ddr_get_rtt();
1646 al = additive_latency;
1649 | ((mrs & 0x3) << 14)
1650 | ((outputs & 0x1) << 12)
1651 | ((rdqs_en & 0x1) << 11)
1652 | ((dqs_en & 0x1) << 10)
1653 | ((ocd & 0x7) << 7)
1654 | ((rtt & 0x2) << 5) /* rtt field is split */
1656 | ((rtt & 0x1) << 2) /* rtt field is split */
1657 | ((ods & 0x1) << 1)
1658 | ((dll_en & 0x1) << 0)
1661 mr = 0; /* FIXME: CHECKME */
1664 * 0 = Fast Exit (Normal)
1665 * 1 = Slow Exit (Low Power)
1669 #if defined(CONFIG_SYS_FSL_DDR1)
1670 wr = 0; /* Historical */
1671 #elif defined(CONFIG_SYS_FSL_DDR2)
1672 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1677 #if defined(CONFIG_SYS_FSL_DDR1)
1678 if (1 <= cas_latency && cas_latency <= 4) {
1679 unsigned char mode_caslat_table[4] = {
1680 0x5, /* 1.5 clocks */
1681 0x2, /* 2.0 clocks */
1682 0x6, /* 2.5 clocks */
1683 0x3 /* 3.0 clocks */
1685 caslat = mode_caslat_table[cas_latency - 1];
1687 printf("Warning: unknown cas_latency %d\n", cas_latency);
1689 #elif defined(CONFIG_SYS_FSL_DDR2)
1690 caslat = cas_latency;
1694 switch (popts->burst_length) {
1702 printf("Error: invalid burst length of %u specified. "
1703 " Defaulting to 4 beats.\n",
1704 popts->burst_length);
1710 | ((mr & 0x3) << 14)
1711 | ((pd & 0x1) << 12)
1713 | ((dll_res & 0x1) << 8)
1714 | ((mode & 0x1) << 7)
1715 | ((caslat & 0x7) << 4)
1720 ddr->ddr_sdram_mode = (0
1721 | ((esdmode & 0xFFFF) << 16)
1722 | ((sdmode & 0xFFFF) << 0)
1724 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1728 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1729 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1731 unsigned int init_value; /* Initialization value */
1733 #ifdef CONFIG_MEM_INIT_VALUE
1734 init_value = CONFIG_MEM_INIT_VALUE;
1736 init_value = 0xDEADBEEF;
1738 ddr->ddr_data_init = init_value;
1742 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1743 * The old controller on the 8540/60 doesn't have this register.
1744 * Hope it's OK to set it (to 0) anyway.
1746 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1747 const memctl_options_t *popts)
1749 unsigned int clk_adjust; /* Clock adjust */
1751 clk_adjust = popts->clk_adjust;
1752 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1753 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1756 /* DDR Initialization Address (DDR_INIT_ADDR) */
1757 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1759 unsigned int init_addr = 0; /* Initialization address */
1761 ddr->ddr_init_addr = init_addr;
1764 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1765 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1767 unsigned int uia = 0; /* Use initialization address */
1768 unsigned int init_ext_addr = 0; /* Initialization address */
1770 ddr->ddr_init_ext_addr = (0
1771 | ((uia & 0x1) << 31)
1772 | (init_ext_addr & 0xF)
1776 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1777 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1778 const memctl_options_t *popts)
1780 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1781 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1782 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1783 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1784 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1786 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1787 if (popts->burst_length == DDR_BL8) {
1788 /* We set BL/2 for fixed BL8 */
1789 rrt = 0; /* BL/2 clocks */
1790 wwt = 0; /* BL/2 clocks */
1792 /* We need to set BL/2 + 2 to BC4 and OTF */
1793 rrt = 2; /* BL/2 + 2 clocks */
1794 wwt = 2; /* BL/2 + 2 clocks */
1798 #ifdef CONFIG_SYS_FSL_DDR4
1799 dll_lock = 2; /* tDLLK = 1024 clocks */
1800 #elif defined(CONFIG_SYS_FSL_DDR3)
1801 dll_lock = 1; /* tDLLK = 512 clocks from spec */
1803 ddr->timing_cfg_4 = (0
1804 | ((rwt & 0xf) << 28)
1805 | ((wrt & 0xf) << 24)
1806 | ((rrt & 0xf) << 20)
1807 | ((wwt & 0xf) << 16)
1810 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1813 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1814 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1816 unsigned int rodt_on = 0; /* Read to ODT on */
1817 unsigned int rodt_off = 0; /* Read to ODT off */
1818 unsigned int wodt_on = 0; /* Write to ODT on */
1819 unsigned int wodt_off = 0; /* Write to ODT off */
1821 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1822 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1823 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1824 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1825 if (cas_latency >= wr_lat)
1826 rodt_on = cas_latency - wr_lat + 1;
1827 rodt_off = 4; /* 4 clocks */
1828 wodt_on = 1; /* 1 clocks */
1829 wodt_off = 4; /* 4 clocks */
1832 ddr->timing_cfg_5 = (0
1833 | ((rodt_on & 0x1f) << 24)
1834 | ((rodt_off & 0x7) << 20)
1835 | ((wodt_on & 0x1f) << 12)
1836 | ((wodt_off & 0x7) << 8)
1838 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1841 #ifdef CONFIG_SYS_FSL_DDR4
1842 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1844 unsigned int hs_caslat = 0;
1845 unsigned int hs_wrlat = 0;
1846 unsigned int hs_wrrec = 0;
1847 unsigned int hs_clkadj = 0;
1848 unsigned int hs_wrlvl_start = 0;
1850 ddr->timing_cfg_6 = (0
1851 | ((hs_caslat & 0x1f) << 24)
1852 | ((hs_wrlat & 0x1f) << 19)
1853 | ((hs_wrrec & 0x1f) << 12)
1854 | ((hs_clkadj & 0x1f) << 6)
1855 | ((hs_wrlvl_start & 0x1f) << 0)
1857 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1860 static void set_timing_cfg_7(const unsigned int ctrl_num,
1861 fsl_ddr_cfg_regs_t *ddr,
1862 const common_timing_params_t *common_dimm)
1864 unsigned int txpr, tcksre, tcksrx;
1865 unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1867 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1868 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1869 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1875 else if (txpr <= 256)
1877 else if (txpr <= 512)
1892 ddr->timing_cfg_7 = (0
1893 | ((cke_rst & 0x3) << 28)
1894 | ((cksre & 0xf) << 24)
1895 | ((cksrx & 0xf) << 20)
1896 | ((par_lat & 0xf) << 16)
1897 | ((cs_to_cmd & 0xf) << 4)
1899 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1902 static void set_timing_cfg_8(const unsigned int ctrl_num,
1903 fsl_ddr_cfg_regs_t *ddr,
1904 const memctl_options_t *popts,
1905 const common_timing_params_t *common_dimm,
1906 unsigned int cas_latency)
1908 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1909 unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1910 unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1911 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1912 ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1914 rwt_bg = cas_latency + 2 + 4 - wr_lat;
1916 rwt_bg = tccdl - rwt_bg;
1920 wrt_bg = wr_lat + 4 + 1 - cas_latency;
1922 wrt_bg = tccdl - wrt_bg;
1926 if (popts->burst_length == DDR_BL8) {
1934 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1935 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
1936 if (popts->otf_burst_chop_en)
1941 ddr->timing_cfg_8 = (0
1942 | ((rwt_bg & 0xf) << 28)
1943 | ((wrt_bg & 0xf) << 24)
1944 | ((rrt_bg & 0xf) << 20)
1945 | ((wwt_bg & 0xf) << 16)
1946 | ((acttoact_bg & 0xf) << 12)
1947 | ((wrtord_bg & 0xf) << 8)
1948 | ((pre_all_rec & 0x1f) << 0)
1951 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1954 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1956 ddr->timing_cfg_9 = 0;
1957 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1960 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1961 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1962 const dimm_params_t *dimm_params)
1964 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1966 ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1967 ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1968 ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1969 ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1970 ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1972 ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1973 ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1974 ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1975 ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1976 ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1978 ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1979 ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1980 ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1981 ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1982 ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1984 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
1985 ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1986 ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1988 (dimm_params->dq_mapping[9] & 0x3F) << 14) |
1989 dimm_params->dq_mapping_ors;
1991 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1992 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1993 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1994 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1996 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1997 const memctl_options_t *popts)
2001 rd_pre = popts->quad_rank_present ? 1 : 0;
2003 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2005 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2007 #endif /* CONFIG_SYS_FSL_DDR4 */
2009 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2010 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2012 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2013 /* Normal Operation Full Calibration Time (tZQoper) */
2014 unsigned int zqoper = 0;
2015 /* Normal Operation Short Calibration Time (tZQCS) */
2016 unsigned int zqcs = 0;
2017 #ifdef CONFIG_SYS_FSL_DDR4
2018 unsigned int zqcs_init;
2022 #ifdef CONFIG_SYS_FSL_DDR4
2023 zqinit = 10; /* 1024 clocks */
2024 zqoper = 9; /* 512 clocks */
2025 zqcs = 7; /* 128 clocks */
2026 zqcs_init = 5; /* 1024 refresh sequences */
2028 zqinit = 9; /* 512 clocks */
2029 zqoper = 8; /* 256 clocks */
2030 zqcs = 6; /* 64 clocks */
2034 ddr->ddr_zq_cntl = (0
2035 | ((zq_en & 0x1) << 31)
2036 | ((zqinit & 0xF) << 24)
2037 | ((zqoper & 0xF) << 16)
2038 | ((zqcs & 0xF) << 8)
2039 #ifdef CONFIG_SYS_FSL_DDR4
2040 | ((zqcs_init & 0xF) << 0)
2043 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2046 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2047 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2048 const memctl_options_t *popts)
2051 * First DQS pulse rising edge after margining mode
2052 * is programmed (tWL_MRD)
2054 unsigned int wrlvl_mrd = 0;
2055 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2056 unsigned int wrlvl_odten = 0;
2057 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2058 unsigned int wrlvl_dqsen = 0;
2059 /* WRLVL_SMPL: Write leveling sample time */
2060 unsigned int wrlvl_smpl = 0;
2061 /* WRLVL_WLR: Write leveling repeition time */
2062 unsigned int wrlvl_wlr = 0;
2063 /* WRLVL_START: Write leveling start time */
2064 unsigned int wrlvl_start = 0;
2066 /* suggest enable write leveling for DDR3 due to fly-by topology */
2068 /* tWL_MRD min = 40 nCK, we set it 64 */
2072 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2075 * Write leveling sample time at least need 6 clocks
2076 * higher than tWLO to allow enough time for progagation
2077 * delay and sampling the prime data bits.
2081 * Write leveling repetition time
2082 * at least tWLO + 6 clocks clocks
2087 * Write leveling start time
2088 * The value use for the DQS_ADJUST for the first sample
2089 * when write leveling is enabled. It probably needs to be
2090 * overriden per platform.
2094 * Override the write leveling sample and start time
2095 * according to specific board
2097 if (popts->wrlvl_override) {
2098 wrlvl_smpl = popts->wrlvl_sample;
2099 wrlvl_start = popts->wrlvl_start;
2103 ddr->ddr_wrlvl_cntl = (0
2104 | ((wrlvl_en & 0x1) << 31)
2105 | ((wrlvl_mrd & 0x7) << 24)
2106 | ((wrlvl_odten & 0x7) << 20)
2107 | ((wrlvl_dqsen & 0x7) << 16)
2108 | ((wrlvl_smpl & 0xf) << 12)
2109 | ((wrlvl_wlr & 0x7) << 8)
2110 | ((wrlvl_start & 0x1F) << 0)
2112 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2113 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2114 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2115 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2116 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2120 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2121 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2123 /* Self Refresh Idle Threshold */
2124 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2127 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2129 if (popts->addr_hash) {
2130 ddr->ddr_eor = 0x40000000; /* address hash enable */
2131 puts("Address hashing enabled.\n");
2135 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2137 ddr->ddr_cdr1 = popts->ddr_cdr1;
2138 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2141 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2143 ddr->ddr_cdr2 = popts->ddr_cdr2;
2144 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2148 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2150 unsigned int res = 0;
2153 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2154 * not set at the same time.
2156 if (ddr->ddr_sdram_cfg & 0x10000000
2157 && ddr->ddr_sdram_cfg & 0x00008000) {
2158 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2159 " should not be set at the same time.\n");
2167 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2168 const memctl_options_t *popts,
2169 fsl_ddr_cfg_regs_t *ddr,
2170 const common_timing_params_t *common_dimm,
2171 const dimm_params_t *dimm_params,
2172 unsigned int dbw_cap_adj,
2173 unsigned int size_only)
2176 unsigned int cas_latency;
2177 unsigned int additive_latency;
2180 unsigned int wrlvl_en;
2181 unsigned int ip_rev = 0;
2182 unsigned int unq_mrs_en = 0;
2185 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2187 if (common_dimm == NULL) {
2188 printf("Error: subset DIMM params struct null pointer\n");
2193 * Process overrides first.
2195 * FIXME: somehow add dereated caslat to this
2197 cas_latency = (popts->cas_latency_override)
2198 ? popts->cas_latency_override_value
2199 : common_dimm->lowest_common_spd_caslat;
2201 additive_latency = (popts->additive_latency_override)
2202 ? popts->additive_latency_override_value
2203 : common_dimm->additive_latency;
2205 sr_it = (popts->auto_self_refresh_en)
2208 /* ZQ calibration */
2209 zq_en = (popts->zq_en) ? 1 : 0;
2210 /* write leveling */
2211 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2213 /* Chip Select Memory Bounds (CSn_BNDS) */
2214 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2215 unsigned long long ea, sa;
2216 unsigned int cs_per_dimm
2217 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2218 unsigned int dimm_number
2220 unsigned long long rank_density
2221 = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2223 if (dimm_params[dimm_number].n_ranks == 0) {
2224 debug("Skipping setup of CS%u "
2225 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2228 if (popts->memctl_interleaving) {
2229 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2230 case FSL_DDR_CS0_CS1_CS2_CS3:
2232 case FSL_DDR_CS0_CS1:
2233 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2237 case FSL_DDR_CS2_CS3:
2243 sa = common_dimm->base_address;
2244 ea = sa + common_dimm->total_mem - 1;
2245 } else if (!popts->memctl_interleaving) {
2247 * If memory interleaving between controllers is NOT
2248 * enabled, the starting address for each memory
2249 * controller is distinct. However, because rank
2250 * interleaving is enabled, the starting and ending
2251 * addresses of the total memory on that memory
2252 * controller needs to be programmed into its
2253 * respective CS0_BNDS.
2255 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2256 case FSL_DDR_CS0_CS1_CS2_CS3:
2257 sa = common_dimm->base_address;
2258 ea = sa + common_dimm->total_mem - 1;
2260 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2261 if ((i >= 2) && (dimm_number == 0)) {
2262 sa = dimm_params[dimm_number].base_address +
2264 ea = sa + 2 * rank_density - 1;
2266 sa = dimm_params[dimm_number].base_address;
2267 ea = sa + 2 * rank_density - 1;
2270 case FSL_DDR_CS0_CS1:
2271 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2272 sa = dimm_params[dimm_number].base_address;
2273 ea = sa + rank_density - 1;
2275 sa += (i % cs_per_dimm) * rank_density;
2276 ea += (i % cs_per_dimm) * rank_density;
2284 case FSL_DDR_CS2_CS3:
2285 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2286 sa = dimm_params[dimm_number].base_address;
2287 ea = sa + rank_density - 1;
2289 sa += (i % cs_per_dimm) * rank_density;
2290 ea += (i % cs_per_dimm) * rank_density;
2296 ea += (rank_density >> dbw_cap_adj);
2298 default: /* No bank(chip-select) interleaving */
2299 sa = dimm_params[dimm_number].base_address;
2300 ea = sa + rank_density - 1;
2301 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2302 sa += (i % cs_per_dimm) * rank_density;
2303 ea += (i % cs_per_dimm) * rank_density;
2316 ddr->cs[i].bnds = (0
2317 | ((sa & 0xffff) << 16) /* starting address */
2318 | ((ea & 0xffff) << 0) /* ending address */
2321 /* setting bnds to 0xffffffff for inactive CS */
2322 ddr->cs[i].bnds = 0xffffffff;
2325 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2326 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2327 set_csn_config_2(i, ddr);
2331 * In the case we only need to compute the ddr sdram size, we only need
2332 * to set csn registers, so return from here.
2337 set_ddr_eor(ddr, popts);
2339 #if !defined(CONFIG_SYS_FSL_DDR1)
2340 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2343 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2345 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2346 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2347 cas_latency, additive_latency);
2349 set_ddr_cdr1(ddr, popts);
2350 set_ddr_cdr2(ddr, popts);
2351 set_ddr_sdram_cfg(ddr, popts, common_dimm);
2352 ip_rev = fsl_ddr_get_version();
2353 if (ip_rev > 0x40400)
2356 if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2357 ddr->debug[18] = popts->cswl_override;
2359 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2360 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2361 cas_latency, additive_latency, unq_mrs_en);
2362 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2363 #ifdef CONFIG_SYS_FSL_DDR4
2364 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2365 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2367 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2368 set_ddr_data_init(ddr);
2369 set_ddr_sdram_clk_cntl(ddr, popts);
2370 set_ddr_init_addr(ddr);
2371 set_ddr_init_ext_addr(ddr);
2372 set_timing_cfg_4(ddr, popts);
2373 set_timing_cfg_5(ddr, cas_latency);
2374 #ifdef CONFIG_SYS_FSL_DDR4
2375 set_ddr_sdram_cfg_3(ddr, popts);
2376 set_timing_cfg_6(ddr);
2377 set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2378 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2379 set_timing_cfg_9(ddr);
2380 set_ddr_dq_mapping(ddr, dimm_params);
2383 set_ddr_zq_cntl(ddr, zq_en);
2384 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2386 set_ddr_sr_cntr(ddr, sr_it);
2388 set_ddr_sdram_rcw(ddr, popts, common_dimm);
2390 #ifdef CONFIG_SYS_FSL_DDR_EMU
2391 /* disble DDR training for emulator */
2392 ddr->debug[2] = 0x00000400;
2393 ddr->debug[4] = 0xff800800;
2394 ddr->debug[5] = 0x08000800;
2395 ddr->debug[6] = 0x08000800;
2396 ddr->debug[7] = 0x08000800;
2397 ddr->debug[8] = 0x08000800;
2399 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2400 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2401 ddr->debug[2] |= 0x00000200; /* set bit 22 */
2404 return check_fsl_memctl_config_regs(ddr);