drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 /*
  21  * Determine Rtt value.
  22  *
  23  * This should likely be either board or controller specific.
  24  *
  25  * Rtt(nominal) - DDR2:
  26  *      0 = Rtt disabled
  27  *      1 = 75 ohm
  28  *      2 = 150 ohm
  29  *      3 = 50 ohm
  30  * Rtt(nominal) - DDR3:
  31  *      0 = Rtt disabled
  32  *      1 = 60 ohm
  33  *      2 = 120 ohm
  34  *      3 = 40 ohm
  35  *      4 = 20 ohm
  36  *      5 = 30 ohm
  37  *
  38  * FIXME: Apparently 8641 needs a value of 2
  39  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  40  *
  41  * FIXME: There was some effort down this line earlier:
  42  *
  43  *      unsigned int i;
  44  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  45  *              if (popts->dimmslot[i].num_valid_cs
  46  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  47  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  48  *                      rtt = 2;
  49  *                      break;
  50  *              }
  51  *      }
  52  */
  53 static inline int fsl_ddr_get_rtt(void)
  54 {
  55         int rtt;
  56
  57 #if defined(CONFIG_SYS_FSL_DDR1)
  58         rtt = 0;
  59 #elif defined(CONFIG_SYS_FSL_DDR2)
  60         rtt = 3;
  61 #else
  62         rtt = 0;
  63 #endif
  64
  65         return rtt;
  66 }
  67
  68 #ifdef CONFIG_SYS_FSL_DDR4
  69 /*
  70  * compute CAS write latency according to DDR4 spec
  71  * CWL = 9 for <= 1600MT/s
  72  *       10 for <= 1866MT/s
  73  *       11 for <= 2133MT/s
  74  *       12 for <= 2400MT/s
  75  *       14 for <= 2667MT/s
  76  *       16 for <= 2933MT/s
  77  *       18 for higher
  78  */
  79 static inline unsigned int compute_cas_write_latency(
  80                                 const unsigned int ctrl_num)
  81 {
  82         unsigned int cwl;
  83         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  84         if (mclk_ps >= 1250)
  85                 cwl = 9;
  86         else if (mclk_ps >= 1070)
  87                 cwl = 10;
  88         else if (mclk_ps >= 935)
  89                 cwl = 11;
  90         else if (mclk_ps >= 833)
  91                 cwl = 12;
  92         else if (mclk_ps >= 750)
  93                 cwl = 14;
  94         else if (mclk_ps >= 681)
  95                 cwl = 16;
  96         else
  97                 cwl = 18;
  98
  99         return cwl;
 100 }
 101 #else
 102 /*
 103  * compute the CAS write latency according to DDR3 spec
 104  * CWL = 5 if tCK >= 2.5ns
 105  *       6 if 2.5ns > tCK >= 1.875ns
 106  *       7 if 1.875ns > tCK >= 1.5ns
 107  *       8 if 1.5ns > tCK >= 1.25ns
 108  *       9 if 1.25ns > tCK >= 1.07ns
 109  *       10 if 1.07ns > tCK >= 0.935ns
 110  *       11 if 0.935ns > tCK >= 0.833ns
 111  *       12 if 0.833ns > tCK >= 0.75ns
 112  */
 113 static inline unsigned int compute_cas_write_latency(
 114                                 const unsigned int ctrl_num)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 /*
 257  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 258  * Return 1 if other two slots configuration. Return 0 if single slot.
 259  */
 260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 261 {
 262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 263         if (dimm_params[0].n_ranks == 4)
 264                 return 2;
 265 #endif
 266
 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 268         if ((dimm_params[0].n_ranks == 2) &&
 269                 (dimm_params[1].n_ranks == 2))
 270                 return 2;
 271
 272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 273         if (dimm_params[0].n_ranks == 4)
 274                 return 2;
 275 #endif
 276
 277         if ((dimm_params[0].n_ranks != 0) &&
 278             (dimm_params[2].n_ranks != 0))
 279                 return 1;
 280 #endif
 281         return 0;
 282 }
 283
 284 /*
 285  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 286  *
 287  * Avoid writing for DDR I.  The new PQ38 DDR controller
 288  * dreams up non-zero default values to be backwards compatible.
 289  */
 290 static void set_timing_cfg_0(const unsigned int ctrl_num,
 291                                 fsl_ddr_cfg_regs_t *ddr,
 292                                 const memctl_options_t *popts,
 293                                 const dimm_params_t *dimm_params)
 294 {
 295         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 296         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 297         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 298         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 299         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 300
 301         /* Active powerdown exit timing (tXARD and tXARDS). */
 302         unsigned char act_pd_exit_mclk;
 303         /* Precharge powerdown exit timing (tXP). */
 304         unsigned char pre_pd_exit_mclk;
 305         /* ODT powerdown exit timing (tAXPD). */
 306         unsigned char taxpd_mclk = 0;
 307         /* Mode register set cycle time (tMRD). */
 308         unsigned char tmrd_mclk;
 309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 310         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 311 #endif
 312
 313 #ifdef CONFIG_SYS_FSL_DDR4
 314         /* tXP=max(4nCK, 6ns) */
 315         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 316         trwt_mclk = 2;
 317         twrt_mclk = 1;
 318         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 319         pre_pd_exit_mclk = act_pd_exit_mclk;
 320         /*
 321          * MRS_CYC = max(tMRD, tMOD)
 322          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 323          */
 324         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 325 #elif defined(CONFIG_SYS_FSL_DDR3)
 326         unsigned int data_rate = get_ddr_freq(ctrl_num);
 327         int txp;
 328         unsigned int ip_rev;
 329         int odt_overlap;
 330         /*
 331          * (tXARD and tXARDS). Empirical?
 332          * The DDR3 spec has not tXARD,
 333          * we use the tXP instead of it.
 334          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 335          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 336          * spec has not the tAXPD, we use
 337          * tAXPD=1, need design to confirm.
 338          */
 339         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 340
 341         ip_rev = fsl_ddr_get_version();
 342         if (ip_rev >= 0x40700) {
 343                 /*
 344                  * MRS_CYC = max(tMRD, tMOD)
 345                  * tMRD = 4nCK (8nCK for RDIMM)
 346                  * tMOD = max(12nCK, 15ns)
 347                  */
 348                 tmrd_mclk = max((unsigned int)12,
 349                                 picos_to_mclk(ctrl_num, 15000));
 350         } else {
 351                 /*
 352                  * MRS_CYC = tMRD
 353                  * tMRD = 4nCK (8nCK for RDIMM)
 354                  */
 355                 if (popts->registered_dimm_en)
 356                         tmrd_mclk = 8;
 357                 else
 358                         tmrd_mclk = 4;
 359         }
 360
 361         /* set the turnaround time */
 362
 363         /*
 364          * for single quad-rank DIMM and two-slot DIMMs
 365          * to avoid ODT overlap
 366          */
 367         odt_overlap = avoid_odt_overlap(dimm_params);
 368         switch (odt_overlap) {
 369         case 2:
 370                 twwt_mclk = 2;
 371                 trrt_mclk = 1;
 372                 break;
 373         case 1:
 374                 twwt_mclk = 1;
 375                 trrt_mclk = 0;
 376                 break;
 377         default:
 378                 break;
 379         }
 380
 381         /* for faster clock, need more time for data setup */
 382         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 383
 384         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 385                 twrt_mclk = 1;
 386
 387         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 388                 act_pd_exit_mclk = 1;
 389                 pre_pd_exit_mclk = 1;
 390                 taxpd_mclk = 1;
 391         } else {
 392                 /* act_pd_exit_mclk = tXARD, see above */
 393                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 394                 /* Mode register MR0[A12] is '1' - fast exit */
 395                 pre_pd_exit_mclk = act_pd_exit_mclk;
 396                 taxpd_mclk = 1;
 397         }
 398 #else /* CONFIG_SYS_FSL_DDR2 */
 399         /*
 400          * (tXARD and tXARDS). Empirical?
 401          * tXARD = 2 for DDR2
 402          * tXP=2
 403          * tAXPD=8
 404          */
 405         act_pd_exit_mclk = 2;
 406         pre_pd_exit_mclk = 2;
 407         taxpd_mclk = 8;
 408         tmrd_mclk = 2;
 409 #endif
 410
 411         if (popts->trwt_override)
 412                 trwt_mclk = popts->trwt;
 413
 414         ddr->timing_cfg_0 = (0
 415                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 416                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 417                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 418                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 419                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 420                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 421                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 422                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 423                 );
 424         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 425 }
 426 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 427
 428 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 429 static void set_timing_cfg_3(const unsigned int ctrl_num,
 430                              fsl_ddr_cfg_regs_t *ddr,
 431                              const memctl_options_t *popts,
 432                              const common_timing_params_t *common_dimm,
 433                              unsigned int cas_latency,
 434                              unsigned int additive_latency)
 435 {
 436         /* Extended precharge to activate interval (tRP) */
 437         unsigned int ext_pretoact = 0;
 438         /* Extended Activate to precharge interval (tRAS) */
 439         unsigned int ext_acttopre = 0;
 440         /* Extended activate to read/write interval (tRCD) */
 441         unsigned int ext_acttorw = 0;
 442         /* Extended refresh recovery time (tRFC) */
 443         unsigned int ext_refrec;
 444         /* Extended MCAS latency from READ cmd */
 445         unsigned int ext_caslat = 0;
 446         /* Extended additive latency */
 447         unsigned int ext_add_lat = 0;
 448         /* Extended last data to precharge interval (tWR) */
 449         unsigned int ext_wrrec = 0;
 450         /* Control Adjust */
 451         unsigned int cntl_adj = 0;
 452
 453         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 454         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 455         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 456         ext_caslat = (2 * cas_latency - 1) >> 4;
 457         ext_add_lat = additive_latency >> 4;
 458 #ifdef CONFIG_SYS_FSL_DDR4
 459         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 460 #else
 461         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 462         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 463 #endif
 464         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 465                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 466
 467         ddr->timing_cfg_3 = (0
 468                 | ((ext_pretoact & 0x1) << 28)
 469                 | ((ext_acttopre & 0x3) << 24)
 470                 | ((ext_acttorw & 0x1) << 22)
 471                 | ((ext_refrec & 0x1F) << 16)
 472                 | ((ext_caslat & 0x3) << 12)
 473                 | ((ext_add_lat & 0x1) << 10)
 474                 | ((ext_wrrec & 0x1) << 8)
 475                 | ((cntl_adj & 0x7) << 0)
 476                 );
 477         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 478 }
 479
 480 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 481 static void set_timing_cfg_1(const unsigned int ctrl_num,
 482                              fsl_ddr_cfg_regs_t *ddr,
 483                              const memctl_options_t *popts,
 484                              const common_timing_params_t *common_dimm,
 485                              unsigned int cas_latency)
 486 {
 487         /* Precharge-to-activate interval (tRP) */
 488         unsigned char pretoact_mclk;
 489         /* Activate to precharge interval (tRAS) */
 490         unsigned char acttopre_mclk;
 491         /*  Activate to read/write interval (tRCD) */
 492         unsigned char acttorw_mclk;
 493         /* CASLAT */
 494         unsigned char caslat_ctrl;
 495         /*  Refresh recovery time (tRFC) ; trfc_low */
 496         unsigned char refrec_ctrl;
 497         /* Last data to precharge minimum interval (tWR) */
 498         unsigned char wrrec_mclk;
 499         /* Activate-to-activate interval (tRRD) */
 500         unsigned char acttoact_mclk;
 501         /* Last write data pair to read command issue interval (tWTR) */
 502         unsigned char wrtord_mclk;
 503 #ifdef CONFIG_SYS_FSL_DDR4
 504         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 505         static const u8 wrrec_table[] = {
 506                 10, 10, 10, 10, 10,
 507                 10, 10, 10, 10, 10,
 508                 12, 12, 14, 14, 16,
 509                 16, 18, 18, 20, 20,
 510                 24, 24, 24, 24};
 511 #else
 512         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 513         static const u8 wrrec_table[] = {
 514                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 515 #endif
 516
 517         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 518         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 519         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 520
 521         /*
 522          * Translate CAS Latency to a DDR controller field value:
 523          *
 524          *      CAS Lat DDR I   DDR II  Ctrl
 525          *      Clocks  SPD Bit SPD Bit Value
 526          *      ------- ------- ------- -----
 527          *      1.0     0               0001
 528          *      1.5     1               0010
 529          *      2.0     2       2       0011
 530          *      2.5     3               0100
 531          *      3.0     4       3       0101
 532          *      3.5     5               0110
 533          *      4.0             4       0111
 534          *      4.5                     1000
 535          *      5.0             5       1001
 536          */
 537 #if defined(CONFIG_SYS_FSL_DDR1)
 538         caslat_ctrl = (cas_latency + 1) & 0x07;
 539 #elif defined(CONFIG_SYS_FSL_DDR2)
 540         caslat_ctrl = 2 * cas_latency - 1;
 541 #else
 542         /*
 543          * if the CAS latency more than 8 cycle,
 544          * we need set extend bit for it at
 545          * TIMING_CFG_3[EXT_CASLAT]
 546          */
 547         if (fsl_ddr_get_version() <= 0x40400)
 548                 caslat_ctrl = 2 * cas_latency - 1;
 549         else
 550                 caslat_ctrl = (cas_latency - 1) << 1;
 551 #endif
 552
 553 #ifdef CONFIG_SYS_FSL_DDR4
 554         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 555         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 556         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 557         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 558         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 559                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 560         else
 561                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 562 #else
 563         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 564         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 565         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 566         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 567         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 568                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 569         else
 570                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 571 #endif
 572         if (popts->otf_burst_chop_en)
 573                 wrrec_mclk += 2;
 574
 575         /*
 576          * JEDEC has min requirement for tRRD
 577          */
 578 #if defined(CONFIG_SYS_FSL_DDR3)
 579         if (acttoact_mclk < 4)
 580                 acttoact_mclk = 4;
 581 #endif
 582         /*
 583          * JEDEC has some min requirements for tWTR
 584          */
 585 #if defined(CONFIG_SYS_FSL_DDR2)
 586         if (wrtord_mclk < 2)
 587                 wrtord_mclk = 2;
 588 #elif defined(CONFIG_SYS_FSL_DDR3)
 589         if (wrtord_mclk < 4)
 590                 wrtord_mclk = 4;
 591 #endif
 592         if (popts->otf_burst_chop_en)
 593                 wrtord_mclk += 2;
 594
 595         ddr->timing_cfg_1 = (0
 596                 | ((pretoact_mclk & 0x0F) << 28)
 597                 | ((acttopre_mclk & 0x0F) << 24)
 598                 | ((acttorw_mclk & 0xF) << 20)
 599                 | ((caslat_ctrl & 0xF) << 16)
 600                 | ((refrec_ctrl & 0xF) << 12)
 601                 | ((wrrec_mclk & 0x0F) << 8)
 602                 | ((acttoact_mclk & 0x0F) << 4)
 603                 | ((wrtord_mclk & 0x0F) << 0)
 604                 );
 605         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 606 }
 607
 608 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 609 static void set_timing_cfg_2(const unsigned int ctrl_num,
 610                              fsl_ddr_cfg_regs_t *ddr,
 611                              const memctl_options_t *popts,
 612                              const common_timing_params_t *common_dimm,
 613                              unsigned int cas_latency,
 614                              unsigned int additive_latency)
 615 {
 616         /* Additive latency */
 617         unsigned char add_lat_mclk;
 618         /* CAS-to-preamble override */
 619         unsigned short cpo;
 620         /* Write latency */
 621         unsigned char wr_lat;
 622         /*  Read to precharge (tRTP) */
 623         unsigned char rd_to_pre;
 624         /* Write command to write data strobe timing adjustment */
 625         unsigned char wr_data_delay;
 626         /* Minimum CKE pulse width (tCKE) */
 627         unsigned char cke_pls;
 628         /* Window for four activates (tFAW) */
 629         unsigned short four_act;
 630 #ifdef CONFIG_SYS_FSL_DDR3
 631         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 632 #endif
 633
 634         /* FIXME add check that this must be less than acttorw_mclk */
 635         add_lat_mclk = additive_latency;
 636         cpo = popts->cpo_override;
 637
 638 #if defined(CONFIG_SYS_FSL_DDR1)
 639         /*
 640          * This is a lie.  It should really be 1, but if it is
 641          * set to 1, bits overlap into the old controller's
 642          * otherwise unused ACSM field.  If we leave it 0, then
 643          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 644          */
 645         wr_lat = 0;
 646 #elif defined(CONFIG_SYS_FSL_DDR2)
 647         wr_lat = cas_latency - 1;
 648 #else
 649         wr_lat = compute_cas_write_latency(ctrl_num);
 650 #endif
 651
 652 #ifdef CONFIG_SYS_FSL_DDR4
 653         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 654 #else
 655         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 656 #endif
 657         /*
 658          * JEDEC has some min requirements for tRTP
 659          */
 660 #if defined(CONFIG_SYS_FSL_DDR2)
 661         if (rd_to_pre  < 2)
 662                 rd_to_pre  = 2;
 663 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 664         if (rd_to_pre < 4)
 665                 rd_to_pre = 4;
 666 #endif
 667         if (popts->otf_burst_chop_en)
 668                 rd_to_pre += 2; /* according to UM */
 669
 670         wr_data_delay = popts->write_data_delay;
 671 #ifdef CONFIG_SYS_FSL_DDR4
 672         cpo = 0;
 673         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 674 #elif defined(CONFIG_SYS_FSL_DDR3)
 675         /*
 676          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 677          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 678          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 679          */
 680         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 681                                         (mclk_ps > 1245 ? 5625 : 5000)));
 682 #else
 683         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 684 #endif
 685         four_act = picos_to_mclk(ctrl_num,
 686                                  popts->tfaw_window_four_activates_ps);
 687
 688         ddr->timing_cfg_2 = (0
 689                 | ((add_lat_mclk & 0xf) << 28)
 690                 | ((cpo & 0x1f) << 23)
 691                 | ((wr_lat & 0xf) << 19)
 692                 | ((wr_lat & 0x10) << 14)
 693                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 694                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 695                 | ((cke_pls & 0x7) << 6)
 696                 | ((four_act & 0x3f) << 0)
 697                 );
 698         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 699 }
 700
 701 /* DDR SDRAM Register Control Word */
 702 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 703                                const memctl_options_t *popts,
 704                                const common_timing_params_t *common_dimm)
 705 {
 706         if (common_dimm->all_dimms_registered &&
 707             !common_dimm->all_dimms_unbuffered) {
 708                 if (popts->rcw_override) {
 709                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 710                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 711                 } else {
 712                         ddr->ddr_sdram_rcw_1 =
 713                                 common_dimm->rcw[0] << 28 | \
 714                                 common_dimm->rcw[1] << 24 | \
 715                                 common_dimm->rcw[2] << 20 | \
 716                                 common_dimm->rcw[3] << 16 | \
 717                                 common_dimm->rcw[4] << 12 | \
 718                                 common_dimm->rcw[5] << 8 | \
 719                                 common_dimm->rcw[6] << 4 | \
 720                                 common_dimm->rcw[7];
 721                         ddr->ddr_sdram_rcw_2 =
 722                                 common_dimm->rcw[8] << 28 | \
 723                                 common_dimm->rcw[9] << 24 | \
 724                                 common_dimm->rcw[10] << 20 | \
 725                                 common_dimm->rcw[11] << 16 | \
 726                                 common_dimm->rcw[12] << 12 | \
 727                                 common_dimm->rcw[13] << 8 | \
 728                                 common_dimm->rcw[14] << 4 | \
 729                                 common_dimm->rcw[15];
 730                 }
 731                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 732                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 733         }
 734 }
 735
 736 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 737 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 738                                const memctl_options_t *popts,
 739                                const common_timing_params_t *common_dimm)
 740 {
 741         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 742         unsigned int sren;              /* Self refresh enable (during sleep) */
 743         unsigned int ecc_en;            /* ECC enable. */
 744         unsigned int rd_en;             /* Registered DIMM enable */
 745         unsigned int sdram_type;        /* Type of SDRAM */
 746         unsigned int dyn_pwr;           /* Dynamic power management mode */
 747         unsigned int dbw;               /* DRAM dta bus width */
 748         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 749         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 750         unsigned int threet_en;         /* Enable 3T timing */
 751         unsigned int twot_en;           /* Enable 2T timing */
 752         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 753         unsigned int x32_en = 0;        /* x32 enable */
 754         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 755         unsigned int hse;               /* Global half strength override */
 756         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 757         unsigned int mem_halt = 0;      /* memory controller halt */
 758         unsigned int bi = 0;            /* Bypass initialization */
 759
 760         mem_en = 1;
 761         sren = popts->self_refresh_in_sleep;
 762         if (common_dimm->all_dimms_ecc_capable) {
 763                 /* Allow setting of ECC only if all DIMMs are ECC. */
 764                 ecc_en = popts->ecc_mode;
 765         } else {
 766                 ecc_en = 0;
 767         }
 768
 769         if (common_dimm->all_dimms_registered &&
 770             !common_dimm->all_dimms_unbuffered) {
 771                 rd_en = 1;
 772                 twot_en = 0;
 773         } else {
 774                 rd_en = 0;
 775                 twot_en = popts->twot_en;
 776         }
 777
 778         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 779
 780         dyn_pwr = popts->dynamic_power;
 781         dbw = popts->data_bus_width;
 782         /* 8-beat burst enable DDR-III case
 783          * we must clear it when use the on-the-fly mode,
 784          * must set it when use the 32-bits bus mode.
 785          */
 786         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 787             (sdram_type == SDRAM_TYPE_DDR4)) {
 788                 if (popts->burst_length == DDR_BL8)
 789                         eight_be = 1;
 790                 if (popts->burst_length == DDR_OTF)
 791                         eight_be = 0;
 792                 if (dbw == 0x1)
 793                         eight_be = 1;
 794         }
 795
 796         threet_en = popts->threet_en;
 797         ba_intlv_ctl = popts->ba_intlv_ctl;
 798         hse = popts->half_strength_driver_enable;
 799
 800         /* set when ddr bus width < 64 */
 801         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 802
 803         ddr->ddr_sdram_cfg = (0
 804                         | ((mem_en & 0x1) << 31)
 805                         | ((sren & 0x1) << 30)
 806                         | ((ecc_en & 0x1) << 29)
 807                         | ((rd_en & 0x1) << 28)
 808                         | ((sdram_type & 0x7) << 24)
 809                         | ((dyn_pwr & 0x1) << 21)
 810                         | ((dbw & 0x3) << 19)
 811                         | ((eight_be & 0x1) << 18)
 812                         | ((ncap & 0x1) << 17)
 813                         | ((threet_en & 0x1) << 16)
 814                         | ((twot_en & 0x1) << 15)
 815                         | ((ba_intlv_ctl & 0x7F) << 8)
 816                         | ((x32_en & 0x1) << 5)
 817                         | ((pchb8 & 0x1) << 4)
 818                         | ((hse & 0x1) << 3)
 819                         | ((acc_ecc_en & 0x1) << 2)
 820                         | ((mem_halt & 0x1) << 1)
 821                         | ((bi & 0x1) << 0)
 822                         );
 823         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 824 }
 825
 826 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 827 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 828                                fsl_ddr_cfg_regs_t *ddr,
 829                                const memctl_options_t *popts,
 830                                const unsigned int unq_mrs_en)
 831 {
 832         unsigned int frc_sr = 0;        /* Force self refresh */
 833         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 834         unsigned int odt_cfg = 0;       /* ODT configuration */
 835         unsigned int num_pr;            /* Number of posted refreshes */
 836         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 837         unsigned int x4_en = 0;         /* x4 DRAM enable */
 838         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 839         unsigned int ap_en;             /* Address Parity Enable */
 840         unsigned int d_init;            /* DRAM data initialization */
 841         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 842         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 843         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 844         int i;
 845 #ifndef CONFIG_SYS_FSL_DDR4
 846         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 847         unsigned int dqs_cfg;           /* DQS configuration */
 848
 849         dqs_cfg = popts->dqs_config;
 850 #endif
 851         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 852                 if (popts->cs_local_opts[i].odt_rd_cfg
 853                         || popts->cs_local_opts[i].odt_wr_cfg) {
 854                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 855                         break;
 856                 }
 857         }
 858
 859         num_pr = 1;     /* Make this configurable */
 860
 861         /*
 862          * 8572 manual says
 863          *     {TIMING_CFG_1[PRETOACT]
 864          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 865          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 866          *      << DDR_SDRAM_INTERVAL[REFINT]
 867          */
 868 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 869         obc_cfg = popts->otf_burst_chop_en;
 870 #else
 871         obc_cfg = 0;
 872 #endif
 873
 874 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 875         slow = get_ddr_freq(ctrl_num) < 1249000000;
 876 #endif
 877
 878         if (popts->registered_dimm_en) {
 879                 rcw_en = 1;
 880                 ap_en = popts->ap_en;
 881         } else {
 882                 ap_en = 0;
 883         }
 884
 885         x4_en = popts->x4_en ? 1 : 0;
 886
 887 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 888         /* Use the DDR controller to auto initialize memory. */
 889         d_init = popts->ecc_init_using_memctl;
 890         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 891         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 892 #else
 893         /* Memory will be initialized via DMA, or not at all. */
 894         d_init = 0;
 895 #endif
 896
 897 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 898         md_en = popts->mirrored_dimm;
 899 #endif
 900         qd_en = popts->quad_rank_present ? 1 : 0;
 901         ddr->ddr_sdram_cfg_2 = (0
 902                 | ((frc_sr & 0x1) << 31)
 903                 | ((sr_ie & 0x1) << 30)
 904 #ifndef CONFIG_SYS_FSL_DDR4
 905                 | ((dll_rst_dis & 0x1) << 29)
 906                 | ((dqs_cfg & 0x3) << 26)
 907 #endif
 908                 | ((odt_cfg & 0x3) << 21)
 909                 | ((num_pr & 0xf) << 12)
 910                 | ((slow & 1) << 11)
 911                 | (x4_en << 10)
 912                 | (qd_en << 9)
 913                 | (unq_mrs_en << 8)
 914                 | ((obc_cfg & 0x1) << 6)
 915                 | ((ap_en & 0x1) << 5)
 916                 | ((d_init & 0x1) << 4)
 917                 | ((rcw_en & 0x1) << 2)
 918                 | ((md_en & 0x1) << 0)
 919                 );
 920         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 921 }
 922
 923 #ifdef CONFIG_SYS_FSL_DDR4
 924 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 925 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 926                                 fsl_ddr_cfg_regs_t *ddr,
 927                                 const memctl_options_t *popts,
 928                                 const common_timing_params_t *common_dimm,
 929                                 const unsigned int unq_mrs_en)
 930 {
 931         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 932         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 933         int i;
 934         unsigned int wr_crc = 0;        /* Disable */
 935         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 936         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 937         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 938         unsigned int mpr = 0;   /* serial */
 939         unsigned int wc_lat;
 940         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 941
 942         if (popts->rtt_override)
 943                 rtt_wr = popts->rtt_wr_override_value;
 944         else
 945                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 946
 947         if (common_dimm->extended_op_srt)
 948                 srt = common_dimm->extended_op_srt;
 949
 950         esdmode2 = (0
 951                 | ((wr_crc & 0x1) << 12)
 952                 | ((rtt_wr & 0x3) << 9)
 953                 | ((srt & 0x3) << 6)
 954                 | ((cwl & 0x7) << 3));
 955
 956         if (mclk_ps >= 1250)
 957                 wc_lat = 0;
 958         else if (mclk_ps >= 833)
 959                 wc_lat = 1;
 960         else
 961                 wc_lat = 2;
 962
 963         esdmode3 = (0
 964                 | ((mpr & 0x3) << 11)
 965                 | ((wc_lat & 0x3) << 9));
 966
 967         ddr->ddr_sdram_mode_2 = (0
 968                                  | ((esdmode2 & 0xFFFF) << 16)
 969                                  | ((esdmode3 & 0xFFFF) << 0)
 970                                  );
 971         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 972
 973         if (unq_mrs_en) {       /* unique mode registers are supported */
 974                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 975                         if (popts->rtt_override)
 976                                 rtt_wr = popts->rtt_wr_override_value;
 977                         else
 978                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 979
 980                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 981                         esdmode2 |= (rtt_wr & 0x3) << 9;
 982                         switch (i) {
 983                         case 1:
 984                                 ddr->ddr_sdram_mode_4 = (0
 985                                         | ((esdmode2 & 0xFFFF) << 16)
 986                                         | ((esdmode3 & 0xFFFF) << 0)
 987                                         );
 988                                 break;
 989                         case 2:
 990                                 ddr->ddr_sdram_mode_6 = (0
 991                                         | ((esdmode2 & 0xFFFF) << 16)
 992                                         | ((esdmode3 & 0xFFFF) << 0)
 993                                         );
 994                                 break;
 995                         case 3:
 996                                 ddr->ddr_sdram_mode_8 = (0
 997                                         | ((esdmode2 & 0xFFFF) << 16)
 998                                         | ((esdmode3 & 0xFFFF) << 0)
 999                                         );
1000                                 break;
1001                         }
1002                 }
1003                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1004                       ddr->ddr_sdram_mode_4);
1005                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1006                       ddr->ddr_sdram_mode_6);
1007                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1008                       ddr->ddr_sdram_mode_8);
1009         }
1010 }
1011 #elif defined(CONFIG_SYS_FSL_DDR3)
1012 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1013 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1014                                 fsl_ddr_cfg_regs_t *ddr,
1015                                 const memctl_options_t *popts,
1016                                 const common_timing_params_t *common_dimm,
1017                                 const unsigned int unq_mrs_en)
1018 {
1019         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1020         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1021         int i;
1022         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1023         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1024         unsigned int asr = 0;   /* auto self-refresh disable */
1025         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1026         unsigned int pasr = 0;  /* partial array self refresh disable */
1027
1028         if (popts->rtt_override)
1029                 rtt_wr = popts->rtt_wr_override_value;
1030         else
1031                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1032
1033         if (common_dimm->extended_op_srt)
1034                 srt = common_dimm->extended_op_srt;
1035
1036         esdmode2 = (0
1037                 | ((rtt_wr & 0x3) << 9)
1038                 | ((srt & 0x1) << 7)
1039                 | ((asr & 0x1) << 6)
1040                 | ((cwl & 0x7) << 3)
1041                 | ((pasr & 0x7) << 0));
1042         ddr->ddr_sdram_mode_2 = (0
1043                                  | ((esdmode2 & 0xFFFF) << 16)
1044                                  | ((esdmode3 & 0xFFFF) << 0)
1045                                  );
1046         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1047
1048         if (unq_mrs_en) {       /* unique mode registers are supported */
1049                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1050                         if (popts->rtt_override)
1051                                 rtt_wr = popts->rtt_wr_override_value;
1052                         else
1053                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1054
1055                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1056                         esdmode2 |= (rtt_wr & 0x3) << 9;
1057                         switch (i) {
1058                         case 1:
1059                                 ddr->ddr_sdram_mode_4 = (0
1060                                         | ((esdmode2 & 0xFFFF) << 16)
1061                                         | ((esdmode3 & 0xFFFF) << 0)
1062                                         );
1063                                 break;
1064                         case 2:
1065                                 ddr->ddr_sdram_mode_6 = (0
1066                                         | ((esdmode2 & 0xFFFF) << 16)
1067                                         | ((esdmode3 & 0xFFFF) << 0)
1068                                         );
1069                                 break;
1070                         case 3:
1071                                 ddr->ddr_sdram_mode_8 = (0
1072                                         | ((esdmode2 & 0xFFFF) << 16)
1073                                         | ((esdmode3 & 0xFFFF) << 0)
1074                                         );
1075                                 break;
1076                         }
1077                 }
1078                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1079                         ddr->ddr_sdram_mode_4);
1080                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1081                         ddr->ddr_sdram_mode_6);
1082                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1083                         ddr->ddr_sdram_mode_8);
1084         }
1085 }
1086
1087 #else /* for DDR2 and DDR1 */
1088 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1089 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1090                                 fsl_ddr_cfg_regs_t *ddr,
1091                                 const memctl_options_t *popts,
1092                                 const common_timing_params_t *common_dimm,
1093                                 const unsigned int unq_mrs_en)
1094 {
1095         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1096         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1097
1098         ddr->ddr_sdram_mode_2 = (0
1099                                  | ((esdmode2 & 0xFFFF) << 16)
1100                                  | ((esdmode3 & 0xFFFF) << 0)
1101                                  );
1102         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1103 }
1104 #endif
1105
1106 #ifdef CONFIG_SYS_FSL_DDR4
1107 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1108 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1109                                 const memctl_options_t *popts,
1110                                 const common_timing_params_t *common_dimm,
1111                                 const unsigned int unq_mrs_en)
1112 {
1113         int i;
1114         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1115         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1116
1117         esdmode5 = 0x00000400;          /* Data mask enabled */
1118
1119         ddr->ddr_sdram_mode_9 = (0
1120                                  | ((esdmode4 & 0xffff) << 16)
1121                                  | ((esdmode5 & 0xffff) << 0)
1122                                 );
1123         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1124         if (unq_mrs_en) {       /* unique mode registers are supported */
1125                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1126                         switch (i) {
1127                         case 1:
1128                                 ddr->ddr_sdram_mode_11 = (0
1129                                         | ((esdmode4 & 0xFFFF) << 16)
1130                                         | ((esdmode5 & 0xFFFF) << 0)
1131                                         );
1132                                 break;
1133                         case 2:
1134                                 ddr->ddr_sdram_mode_13 = (0
1135                                         | ((esdmode4 & 0xFFFF) << 16)
1136                                         | ((esdmode5 & 0xFFFF) << 0)
1137                                         );
1138                                 break;
1139                         case 3:
1140                                 ddr->ddr_sdram_mode_15 = (0
1141                                         | ((esdmode4 & 0xFFFF) << 16)
1142                                         | ((esdmode5 & 0xFFFF) << 0)
1143                                         );
1144                                 break;
1145                         }
1146                 }
1147                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1148                       ddr->ddr_sdram_mode_11);
1149                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1150                       ddr->ddr_sdram_mode_13);
1151                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1152                       ddr->ddr_sdram_mode_15);
1153         }
1154 }
1155
1156 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1157 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1158                                 fsl_ddr_cfg_regs_t *ddr,
1159                                 const memctl_options_t *popts,
1160                                 const common_timing_params_t *common_dimm,
1161                                 const unsigned int unq_mrs_en)
1162 {
1163         int i;
1164         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1165         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1166         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1167
1168         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1169
1170         ddr->ddr_sdram_mode_10 = (0
1171                                  | ((esdmode6 & 0xffff) << 16)
1172                                  | ((esdmode7 & 0xffff) << 0)
1173                                 );
1174         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1175         if (unq_mrs_en) {       /* unique mode registers are supported */
1176                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1177                         switch (i) {
1178                         case 1:
1179                                 ddr->ddr_sdram_mode_12 = (0
1180                                         | ((esdmode6 & 0xFFFF) << 16)
1181                                         | ((esdmode7 & 0xFFFF) << 0)
1182                                         );
1183                                 break;
1184                         case 2:
1185                                 ddr->ddr_sdram_mode_14 = (0
1186                                         | ((esdmode6 & 0xFFFF) << 16)
1187                                         | ((esdmode7 & 0xFFFF) << 0)
1188                                         );
1189                                 break;
1190                         case 3:
1191                                 ddr->ddr_sdram_mode_16 = (0
1192                                         | ((esdmode6 & 0xFFFF) << 16)
1193                                         | ((esdmode7 & 0xFFFF) << 0)
1194                                         );
1195                                 break;
1196                         }
1197                 }
1198                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1199                       ddr->ddr_sdram_mode_12);
1200                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1201                       ddr->ddr_sdram_mode_14);
1202                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1203                       ddr->ddr_sdram_mode_16);
1204         }
1205 }
1206
1207 #endif
1208
1209 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1210 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1211                                 fsl_ddr_cfg_regs_t *ddr,
1212                                 const memctl_options_t *popts,
1213                                 const common_timing_params_t *common_dimm)
1214 {
1215         unsigned int refint;    /* Refresh interval */
1216         unsigned int bstopre;   /* Precharge interval */
1217
1218         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1219
1220         bstopre = popts->bstopre;
1221
1222         /* refint field used 0x3FFF in earlier controllers */
1223         ddr->ddr_sdram_interval = (0
1224                                    | ((refint & 0xFFFF) << 16)
1225                                    | ((bstopre & 0x3FFF) << 0)
1226                                    );
1227         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1228 }
1229
1230 #ifdef CONFIG_SYS_FSL_DDR4
1231 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1232 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1233                                fsl_ddr_cfg_regs_t *ddr,
1234                                const memctl_options_t *popts,
1235                                const common_timing_params_t *common_dimm,
1236                                unsigned int cas_latency,
1237                                unsigned int additive_latency,
1238                                const unsigned int unq_mrs_en)
1239 {
1240         int i;
1241         unsigned short esdmode;         /* Extended SDRAM mode */
1242         unsigned short sdmode;          /* SDRAM mode */
1243
1244         /* Mode Register - MR1 */
1245         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1246         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1247         unsigned int rtt;
1248         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1249         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1250         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1251         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1252                                                        0=Disable (Test/Debug) */
1253
1254         /* Mode Register - MR0 */
1255         unsigned int wr = 0;    /* Write Recovery */
1256         unsigned int dll_rst;   /* DLL Reset */
1257         unsigned int mode;      /* Normal=0 or Test=1 */
1258         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1259         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1260         unsigned int bt;
1261         unsigned int bl;        /* BL: Burst Length */
1262
1263         unsigned int wr_mclk;
1264         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1265         static const u8 wr_table[] = {
1266                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1267         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1268         static const u8 cas_latency_table[] = {
1269                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1270                 9, 9, 10, 10, 11, 11};
1271
1272         if (popts->rtt_override)
1273                 rtt = popts->rtt_override_value;
1274         else
1275                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1276
1277         if (additive_latency == (cas_latency - 1))
1278                 al = 1;
1279         if (additive_latency == (cas_latency - 2))
1280                 al = 2;
1281
1282         if (popts->quad_rank_present)
1283                 dic = 1;        /* output driver impedance 240/7 ohm */
1284
1285         /*
1286          * The esdmode value will also be used for writing
1287          * MR1 during write leveling for DDR3, although the
1288          * bits specifically related to the write leveling
1289          * scheme will be handled automatically by the DDR
1290          * controller. so we set the wrlvl_en = 0 here.
1291          */
1292         esdmode = (0
1293                 | ((qoff & 0x1) << 12)
1294                 | ((tdqs_en & 0x1) << 11)
1295                 | ((rtt & 0x7) << 8)
1296                 | ((wrlvl_en & 0x1) << 7)
1297                 | ((al & 0x3) << 3)
1298                 | ((dic & 0x3) << 1)   /* DIC field is split */
1299                 | ((dll_en & 0x1) << 0)
1300                 );
1301
1302         /*
1303          * DLL control for precharge PD
1304          * 0=slow exit DLL off (tXPDLL)
1305          * 1=fast exit DLL on (tXP)
1306          */
1307
1308         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1309         if (wr_mclk <= 24) {
1310                 wr = wr_table[wr_mclk - 10];
1311         } else {
1312                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1313                        wr_mclk);
1314         }
1315
1316         dll_rst = 0;    /* dll no reset */
1317         mode = 0;       /* normal mode */
1318
1319         /* look up table to get the cas latency bits */
1320         if (cas_latency >= 9 && cas_latency <= 24)
1321                 caslat = cas_latency_table[cas_latency - 9];
1322         else
1323                 printf("Error: unsupported cas latency for mode register\n");
1324
1325         bt = 0; /* Nibble sequential */
1326
1327         switch (popts->burst_length) {
1328         case DDR_BL8:
1329                 bl = 0;
1330                 break;
1331         case DDR_OTF:
1332                 bl = 1;
1333                 break;
1334         case DDR_BC4:
1335                 bl = 2;
1336                 break;
1337         default:
1338                 printf("Error: invalid burst length of %u specified. ",
1339                        popts->burst_length);
1340                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1341                 bl = 1;
1342                 break;
1343         }
1344
1345         sdmode = (0
1346                   | ((wr & 0x7) << 9)
1347                   | ((dll_rst & 0x1) << 8)
1348                   | ((mode & 0x1) << 7)
1349                   | (((caslat >> 1) & 0x7) << 4)
1350                   | ((bt & 0x1) << 3)
1351                   | ((caslat & 1) << 2)
1352                   | ((bl & 0x3) << 0)
1353                   );
1354
1355         ddr->ddr_sdram_mode = (0
1356                                | ((esdmode & 0xFFFF) << 16)
1357                                | ((sdmode & 0xFFFF) << 0)
1358                                );
1359
1360         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1361
1362         if (unq_mrs_en) {       /* unique mode registers are supported */
1363                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1364                         if (popts->rtt_override)
1365                                 rtt = popts->rtt_override_value;
1366                         else
1367                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1368
1369                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1370                         esdmode |= (rtt & 0x7) << 8;
1371                         switch (i) {
1372                         case 1:
1373                                 ddr->ddr_sdram_mode_3 = (0
1374                                        | ((esdmode & 0xFFFF) << 16)
1375                                        | ((sdmode & 0xFFFF) << 0)
1376                                        );
1377                                 break;
1378                         case 2:
1379                                 ddr->ddr_sdram_mode_5 = (0
1380                                        | ((esdmode & 0xFFFF) << 16)
1381                                        | ((sdmode & 0xFFFF) << 0)
1382                                        );
1383                                 break;
1384                         case 3:
1385                                 ddr->ddr_sdram_mode_7 = (0
1386                                        | ((esdmode & 0xFFFF) << 16)
1387                                        | ((sdmode & 0xFFFF) << 0)
1388                                        );
1389                                 break;
1390                         }
1391                 }
1392                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1393                       ddr->ddr_sdram_mode_3);
1394                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1395                       ddr->ddr_sdram_mode_5);
1396                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1397                       ddr->ddr_sdram_mode_5);
1398         }
1399 }
1400
1401 #elif defined(CONFIG_SYS_FSL_DDR3)
1402 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1403 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1404                                fsl_ddr_cfg_regs_t *ddr,
1405                                const memctl_options_t *popts,
1406                                const common_timing_params_t *common_dimm,
1407                                unsigned int cas_latency,
1408                                unsigned int additive_latency,
1409                                const unsigned int unq_mrs_en)
1410 {
1411         int i;
1412         unsigned short esdmode;         /* Extended SDRAM mode */
1413         unsigned short sdmode;          /* SDRAM mode */
1414
1415         /* Mode Register - MR1 */
1416         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1417         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1418         unsigned int rtt;
1419         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1420         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1421         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1422         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1423                                                        1=Disable (Test/Debug) */
1424
1425         /* Mode Register - MR0 */
1426         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1427         unsigned int wr = 0;    /* Write Recovery */
1428         unsigned int dll_rst;   /* DLL Reset */
1429         unsigned int mode;      /* Normal=0 or Test=1 */
1430         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1431         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1432         unsigned int bt;
1433         unsigned int bl;        /* BL: Burst Length */
1434
1435         unsigned int wr_mclk;
1436         /*
1437          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1438          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1439          * for this table
1440          */
1441         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1442
1443         if (popts->rtt_override)
1444                 rtt = popts->rtt_override_value;
1445         else
1446                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1447
1448         if (additive_latency == (cas_latency - 1))
1449                 al = 1;
1450         if (additive_latency == (cas_latency - 2))
1451                 al = 2;
1452
1453         if (popts->quad_rank_present)
1454                 dic = 1;        /* output driver impedance 240/7 ohm */
1455
1456         /*
1457          * The esdmode value will also be used for writing
1458          * MR1 during write leveling for DDR3, although the
1459          * bits specifically related to the write leveling
1460          * scheme will be handled automatically by the DDR
1461          * controller. so we set the wrlvl_en = 0 here.
1462          */
1463         esdmode = (0
1464                 | ((qoff & 0x1) << 12)
1465                 | ((tdqs_en & 0x1) << 11)
1466                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1467                 | ((wrlvl_en & 0x1) << 7)
1468                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1469                 | ((dic & 0x2) << 4)   /* DIC field is split */
1470                 | ((al & 0x3) << 3)
1471                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1472                 | ((dic & 0x1) << 1)   /* DIC field is split */
1473                 | ((dll_en & 0x1) << 0)
1474                 );
1475
1476         /*
1477          * DLL control for precharge PD
1478          * 0=slow exit DLL off (tXPDLL)
1479          * 1=fast exit DLL on (tXP)
1480          */
1481         dll_on = 1;
1482
1483         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1484         if (wr_mclk <= 16) {
1485                 wr = wr_table[wr_mclk - 5];
1486         } else {
1487                 printf("Error: unsupported write recovery for mode register "
1488                        "wr_mclk = %d\n", wr_mclk);
1489         }
1490
1491         dll_rst = 0;    /* dll no reset */
1492         mode = 0;       /* normal mode */
1493
1494         /* look up table to get the cas latency bits */
1495         if (cas_latency >= 5 && cas_latency <= 16) {
1496                 unsigned char cas_latency_table[] = {
1497                         0x2,    /* 5 clocks */
1498                         0x4,    /* 6 clocks */
1499                         0x6,    /* 7 clocks */
1500                         0x8,    /* 8 clocks */
1501                         0xa,    /* 9 clocks */
1502                         0xc,    /* 10 clocks */
1503                         0xe,    /* 11 clocks */
1504                         0x1,    /* 12 clocks */
1505                         0x3,    /* 13 clocks */
1506                         0x5,    /* 14 clocks */
1507                         0x7,    /* 15 clocks */
1508                         0x9,    /* 16 clocks */
1509                 };
1510                 caslat = cas_latency_table[cas_latency - 5];
1511         } else {
1512                 printf("Error: unsupported cas latency for mode register\n");
1513         }
1514
1515         bt = 0; /* Nibble sequential */
1516
1517         switch (popts->burst_length) {
1518         case DDR_BL8:
1519                 bl = 0;
1520                 break;
1521         case DDR_OTF:
1522                 bl = 1;
1523                 break;
1524         case DDR_BC4:
1525                 bl = 2;
1526                 break;
1527         default:
1528                 printf("Error: invalid burst length of %u specified. "
1529                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1530                         popts->burst_length);
1531                 bl = 1;
1532                 break;
1533         }
1534
1535         sdmode = (0
1536                   | ((dll_on & 0x1) << 12)
1537                   | ((wr & 0x7) << 9)
1538                   | ((dll_rst & 0x1) << 8)
1539                   | ((mode & 0x1) << 7)
1540                   | (((caslat >> 1) & 0x7) << 4)
1541                   | ((bt & 0x1) << 3)
1542                   | ((caslat & 1) << 2)
1543                   | ((bl & 0x3) << 0)
1544                   );
1545
1546         ddr->ddr_sdram_mode = (0
1547                                | ((esdmode & 0xFFFF) << 16)
1548                                | ((sdmode & 0xFFFF) << 0)
1549                                );
1550
1551         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1552
1553         if (unq_mrs_en) {       /* unique mode registers are supported */
1554                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1555                         if (popts->rtt_override)
1556                                 rtt = popts->rtt_override_value;
1557                         else
1558                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1559
1560                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1561                         esdmode |= (0
1562                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1563                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1564                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1565                                 );
1566                         switch (i) {
1567                         case 1:
1568                                 ddr->ddr_sdram_mode_3 = (0
1569                                        | ((esdmode & 0xFFFF) << 16)
1570                                        | ((sdmode & 0xFFFF) << 0)
1571                                        );
1572                                 break;
1573                         case 2:
1574                                 ddr->ddr_sdram_mode_5 = (0
1575                                        | ((esdmode & 0xFFFF) << 16)
1576                                        | ((sdmode & 0xFFFF) << 0)
1577                                        );
1578                                 break;
1579                         case 3:
1580                                 ddr->ddr_sdram_mode_7 = (0
1581                                        | ((esdmode & 0xFFFF) << 16)
1582                                        | ((sdmode & 0xFFFF) << 0)
1583                                        );
1584                                 break;
1585                         }
1586                 }
1587                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1588                         ddr->ddr_sdram_mode_3);
1589                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1590                         ddr->ddr_sdram_mode_5);
1591                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1592                         ddr->ddr_sdram_mode_5);
1593         }
1594 }
1595
1596 #else /* !CONFIG_SYS_FSL_DDR3 */
1597
1598 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1599 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1600                                fsl_ddr_cfg_regs_t *ddr,
1601                                const memctl_options_t *popts,
1602                                const common_timing_params_t *common_dimm,
1603                                unsigned int cas_latency,
1604                                unsigned int additive_latency,
1605                                const unsigned int unq_mrs_en)
1606 {
1607         unsigned short esdmode;         /* Extended SDRAM mode */
1608         unsigned short sdmode;          /* SDRAM mode */
1609
1610         /*
1611          * FIXME: This ought to be pre-calculated in a
1612          * technology-specific routine,
1613          * e.g. compute_DDR2_mode_register(), and then the
1614          * sdmode and esdmode passed in as part of common_dimm.
1615          */
1616
1617         /* Extended Mode Register */
1618         unsigned int mrs = 0;           /* Mode Register Set */
1619         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1620         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1621         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1622         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1623                                            0x7=OCD default state */
1624         unsigned int rtt;
1625         unsigned int al;                /* Posted CAS# additive latency (AL) */
1626         unsigned int ods = 0;           /* Output Drive Strength:
1627                                                 0 = Full strength (18ohm)
1628                                                 1 = Reduced strength (4ohm) */
1629         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1630                                                        1=Disable (Test/Debug) */
1631
1632         /* Mode Register (MR) */
1633         unsigned int mr;        /* Mode Register Definition */
1634         unsigned int pd;        /* Power-Down Mode */
1635         unsigned int wr;        /* Write Recovery */
1636         unsigned int dll_res;   /* DLL Reset */
1637         unsigned int mode;      /* Normal=0 or Test=1 */
1638         unsigned int caslat = 0;/* CAS# latency */
1639         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1640         unsigned int bt;
1641         unsigned int bl;        /* BL: Burst Length */
1642
1643         dqs_en = !popts->dqs_config;
1644         rtt = fsl_ddr_get_rtt();
1645
1646         al = additive_latency;
1647
1648         esdmode = (0
1649                 | ((mrs & 0x3) << 14)
1650                 | ((outputs & 0x1) << 12)
1651                 | ((rdqs_en & 0x1) << 11)
1652                 | ((dqs_en & 0x1) << 10)
1653                 | ((ocd & 0x7) << 7)
1654                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1655                 | ((al & 0x7) << 3)
1656                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1657                 | ((ods & 0x1) << 1)
1658                 | ((dll_en & 0x1) << 0)
1659                 );
1660
1661         mr = 0;          /* FIXME: CHECKME */
1662
1663         /*
1664          * 0 = Fast Exit (Normal)
1665          * 1 = Slow Exit (Low Power)
1666          */
1667         pd = 0;
1668
1669 #if defined(CONFIG_SYS_FSL_DDR1)
1670         wr = 0;       /* Historical */
1671 #elif defined(CONFIG_SYS_FSL_DDR2)
1672         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1673 #endif
1674         dll_res = 0;
1675         mode = 0;
1676
1677 #if defined(CONFIG_SYS_FSL_DDR1)
1678         if (1 <= cas_latency && cas_latency <= 4) {
1679                 unsigned char mode_caslat_table[4] = {
1680                         0x5,    /* 1.5 clocks */
1681                         0x2,    /* 2.0 clocks */
1682                         0x6,    /* 2.5 clocks */
1683                         0x3     /* 3.0 clocks */
1684                 };
1685                 caslat = mode_caslat_table[cas_latency - 1];
1686         } else {
1687                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1688         }
1689 #elif defined(CONFIG_SYS_FSL_DDR2)
1690         caslat = cas_latency;
1691 #endif
1692         bt = 0;
1693
1694         switch (popts->burst_length) {
1695         case DDR_BL4:
1696                 bl = 2;
1697                 break;
1698         case DDR_BL8:
1699                 bl = 3;
1700                 break;
1701         default:
1702                 printf("Error: invalid burst length of %u specified. "
1703                         " Defaulting to 4 beats.\n",
1704                         popts->burst_length);
1705                 bl = 2;
1706                 break;
1707         }
1708
1709         sdmode = (0
1710                   | ((mr & 0x3) << 14)
1711                   | ((pd & 0x1) << 12)
1712                   | ((wr & 0x7) << 9)
1713                   | ((dll_res & 0x1) << 8)
1714                   | ((mode & 0x1) << 7)
1715                   | ((caslat & 0x7) << 4)
1716                   | ((bt & 0x1) << 3)
1717                   | ((bl & 0x7) << 0)
1718                   );
1719
1720         ddr->ddr_sdram_mode = (0
1721                                | ((esdmode & 0xFFFF) << 16)
1722                                | ((sdmode & 0xFFFF) << 0)
1723                                );
1724         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1725 }
1726 #endif
1727
1728 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1729 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1730 {
1731         unsigned int init_value;        /* Initialization value */
1732
1733 #ifdef CONFIG_MEM_INIT_VALUE
1734         init_value = CONFIG_MEM_INIT_VALUE;
1735 #else
1736         init_value = 0xDEADBEEF;
1737 #endif
1738         ddr->ddr_data_init = init_value;
1739 }
1740
1741 /*
1742  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1743  * The old controller on the 8540/60 doesn't have this register.
1744  * Hope it's OK to set it (to 0) anyway.
1745  */
1746 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1747                                          const memctl_options_t *popts)
1748 {
1749         unsigned int clk_adjust;        /* Clock adjust */
1750         unsigned int ss_en = 0;         /* Source synchronous enable */
1751
1752 #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1753         /* Per FSL Application Note: AN2805 */
1754         ss_en = 1;
1755 #endif
1756         clk_adjust = popts->clk_adjust;
1757         ddr->ddr_sdram_clk_cntl = (0
1758                                    | ((ss_en & 0x1) << 31)
1759                                    | ((clk_adjust & 0xF) << 23)
1760                                    );
1761         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1762 }
1763
1764 /* DDR Initialization Address (DDR_INIT_ADDR) */
1765 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1766 {
1767         unsigned int init_addr = 0;     /* Initialization address */
1768
1769         ddr->ddr_init_addr = init_addr;
1770 }
1771
1772 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1773 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1774 {
1775         unsigned int uia = 0;   /* Use initialization address */
1776         unsigned int init_ext_addr = 0; /* Initialization address */
1777
1778         ddr->ddr_init_ext_addr = (0
1779                                   | ((uia & 0x1) << 31)
1780                                   | (init_ext_addr & 0xF)
1781                                   );
1782 }
1783
1784 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1785 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1786                                 const memctl_options_t *popts)
1787 {
1788         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1789         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1790         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1791         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1792         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1793
1794 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1795         if (popts->burst_length == DDR_BL8) {
1796                 /* We set BL/2 for fixed BL8 */
1797                 rrt = 0;        /* BL/2 clocks */
1798                 wwt = 0;        /* BL/2 clocks */
1799         } else {
1800                 /* We need to set BL/2 + 2 to BC4 and OTF */
1801                 rrt = 2;        /* BL/2 + 2 clocks */
1802                 wwt = 2;        /* BL/2 + 2 clocks */
1803         }
1804 #endif
1805
1806 #ifdef CONFIG_SYS_FSL_DDR4
1807         dll_lock = 2;   /* tDLLK = 1024 clocks */
1808 #elif defined(CONFIG_SYS_FSL_DDR3)
1809         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1810 #endif
1811         ddr->timing_cfg_4 = (0
1812                              | ((rwt & 0xf) << 28)
1813                              | ((wrt & 0xf) << 24)
1814                              | ((rrt & 0xf) << 20)
1815                              | ((wwt & 0xf) << 16)
1816                              | (dll_lock & 0x3)
1817                              );
1818         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1819 }
1820
1821 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1822 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1823 {
1824         unsigned int rodt_on = 0;       /* Read to ODT on */
1825         unsigned int rodt_off = 0;      /* Read to ODT off */
1826         unsigned int wodt_on = 0;       /* Write to ODT on */
1827         unsigned int wodt_off = 0;      /* Write to ODT off */
1828
1829 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1830         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1831                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1832         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1833         if (cas_latency >= wr_lat)
1834                 rodt_on = cas_latency - wr_lat + 1;
1835         rodt_off = 4;   /*  4 clocks */
1836         wodt_on = 1;    /*  1 clocks */
1837         wodt_off = 4;   /*  4 clocks */
1838 #endif
1839
1840         ddr->timing_cfg_5 = (0
1841                              | ((rodt_on & 0x1f) << 24)
1842                              | ((rodt_off & 0x7) << 20)
1843                              | ((wodt_on & 0x1f) << 12)
1844                              | ((wodt_off & 0x7) << 8)
1845                              );
1846         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1847 }
1848
1849 #ifdef CONFIG_SYS_FSL_DDR4
1850 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1851 {
1852         unsigned int hs_caslat = 0;
1853         unsigned int hs_wrlat = 0;
1854         unsigned int hs_wrrec = 0;
1855         unsigned int hs_clkadj = 0;
1856         unsigned int hs_wrlvl_start = 0;
1857
1858         ddr->timing_cfg_6 = (0
1859                              | ((hs_caslat & 0x1f) << 24)
1860                              | ((hs_wrlat & 0x1f) << 19)
1861                              | ((hs_wrrec & 0x1f) << 12)
1862                              | ((hs_clkadj & 0x1f) << 6)
1863                              | ((hs_wrlvl_start & 0x1f) << 0)
1864                             );
1865         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1866 }
1867
1868 static void set_timing_cfg_7(const unsigned int ctrl_num,
1869                              fsl_ddr_cfg_regs_t *ddr,
1870                              const common_timing_params_t *common_dimm)
1871 {
1872         unsigned int txpr, tcksre, tcksrx;
1873         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1874
1875         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1876         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1877         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1878         par_lat = 0;
1879         cs_to_cmd = 0;
1880
1881         if (txpr <= 200)
1882                 cke_rst = 0;
1883         else if (txpr <= 256)
1884                 cke_rst = 1;
1885         else if (txpr <= 512)
1886                 cke_rst = 2;
1887         else
1888                 cke_rst = 3;
1889
1890         if (tcksre <= 19)
1891                 cksre = tcksre - 5;
1892         else
1893                 cksre = 15;
1894
1895         if (tcksrx <= 19)
1896                 cksrx = tcksrx - 5;
1897         else
1898                 cksrx = 15;
1899
1900         ddr->timing_cfg_7 = (0
1901                              | ((cke_rst & 0x3) << 28)
1902                              | ((cksre & 0xf) << 24)
1903                              | ((cksrx & 0xf) << 20)
1904                              | ((par_lat & 0xf) << 16)
1905                              | ((cs_to_cmd & 0xf) << 4)
1906                             );
1907         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1908 }
1909
1910 static void set_timing_cfg_8(const unsigned int ctrl_num,
1911                              fsl_ddr_cfg_regs_t *ddr,
1912                              const memctl_options_t *popts,
1913                              const common_timing_params_t *common_dimm,
1914                              unsigned int cas_latency)
1915 {
1916         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1917         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1918         unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1919         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1920                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1921
1922         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1923         if (rwt_bg < tccdl)
1924                 rwt_bg = tccdl - rwt_bg;
1925         else
1926                 rwt_bg = 0;
1927
1928         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1929         if (wrt_bg < tccdl)
1930                 wrt_bg = tccdl - wrt_bg;
1931         else
1932                 wrt_bg = 0;
1933
1934         if (popts->burst_length == DDR_BL8) {
1935                 rrt_bg = tccdl - 4;
1936                 wwt_bg = tccdl - 4;
1937         } else {
1938                 rrt_bg = tccdl - 2;
1939                 wwt_bg = tccdl - 2;
1940         }
1941
1942         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1943         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
1944         if (popts->otf_burst_chop_en)
1945                 wrtord_bg += 2;
1946
1947         pre_all_rec = 0;
1948
1949         ddr->timing_cfg_8 = (0
1950                              | ((rwt_bg & 0xf) << 28)
1951                              | ((wrt_bg & 0xf) << 24)
1952                              | ((rrt_bg & 0xf) << 20)
1953                              | ((wwt_bg & 0xf) << 16)
1954                              | ((acttoact_bg & 0xf) << 12)
1955                              | ((wrtord_bg & 0xf) << 8)
1956                              | ((pre_all_rec & 0x1f) << 0)
1957                             );
1958
1959         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1960 }
1961
1962 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1963 {
1964         ddr->timing_cfg_9 = 0;
1965         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1966 }
1967
1968 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1969 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1970                                const dimm_params_t *dimm_params)
1971 {
1972         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1973
1974         ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1975                         ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1976                         ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1977                         ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1978                         ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1979
1980         ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1981                         ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1982                         ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1983                         ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1984                         ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1985
1986         ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1987                         ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1988                         ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1989                         ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1990                         ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1991
1992         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
1993         ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1994                         ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1995                         (acc_ecc_en ? 0 :
1996                          (dimm_params->dq_mapping[9] & 0x3F) << 14) |
1997                         dimm_params->dq_mapping_ors;
1998
1999         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2000         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2001         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2002         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2003 }
2004 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2005                                const memctl_options_t *popts)
2006 {
2007         int rd_pre;
2008
2009         rd_pre = popts->quad_rank_present ? 1 : 0;
2010
2011         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2012
2013         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2014 }
2015 #endif  /* CONFIG_SYS_FSL_DDR4 */
2016
2017 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2018 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2019 {
2020         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2021         /* Normal Operation Full Calibration Time (tZQoper) */
2022         unsigned int zqoper = 0;
2023         /* Normal Operation Short Calibration Time (tZQCS) */
2024         unsigned int zqcs = 0;
2025 #ifdef CONFIG_SYS_FSL_DDR4
2026         unsigned int zqcs_init;
2027 #endif
2028
2029         if (zq_en) {
2030 #ifdef CONFIG_SYS_FSL_DDR4
2031                 zqinit = 10;    /* 1024 clocks */
2032                 zqoper = 9;     /* 512 clocks */
2033                 zqcs = 7;       /* 128 clocks */
2034                 zqcs_init = 5;  /* 1024 refresh sequences */
2035 #else
2036                 zqinit = 9;     /* 512 clocks */
2037                 zqoper = 8;     /* 256 clocks */
2038                 zqcs = 6;       /* 64 clocks */
2039 #endif
2040         }
2041
2042         ddr->ddr_zq_cntl = (0
2043                             | ((zq_en & 0x1) << 31)
2044                             | ((zqinit & 0xF) << 24)
2045                             | ((zqoper & 0xF) << 16)
2046                             | ((zqcs & 0xF) << 8)
2047 #ifdef CONFIG_SYS_FSL_DDR4
2048                             | ((zqcs_init & 0xF) << 0)
2049 #endif
2050                             );
2051         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2052 }
2053
2054 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2055 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2056                                 const memctl_options_t *popts)
2057 {
2058         /*
2059          * First DQS pulse rising edge after margining mode
2060          * is programmed (tWL_MRD)
2061          */
2062         unsigned int wrlvl_mrd = 0;
2063         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2064         unsigned int wrlvl_odten = 0;
2065         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2066         unsigned int wrlvl_dqsen = 0;
2067         /* WRLVL_SMPL: Write leveling sample time */
2068         unsigned int wrlvl_smpl = 0;
2069         /* WRLVL_WLR: Write leveling repeition time */
2070         unsigned int wrlvl_wlr = 0;
2071         /* WRLVL_START: Write leveling start time */
2072         unsigned int wrlvl_start = 0;
2073
2074         /* suggest enable write leveling for DDR3 due to fly-by topology */
2075         if (wrlvl_en) {
2076                 /* tWL_MRD min = 40 nCK, we set it 64 */
2077                 wrlvl_mrd = 0x6;
2078                 /* tWL_ODTEN 128 */
2079                 wrlvl_odten = 0x7;
2080                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2081                 wrlvl_dqsen = 0x5;
2082                 /*
2083                  * Write leveling sample time at least need 6 clocks
2084                  * higher than tWLO to allow enough time for progagation
2085                  * delay and sampling the prime data bits.
2086                  */
2087                 wrlvl_smpl = 0xf;
2088                 /*
2089                  * Write leveling repetition time
2090                  * at least tWLO + 6 clocks clocks
2091                  * we set it 64
2092                  */
2093                 wrlvl_wlr = 0x6;
2094                 /*
2095                  * Write leveling start time
2096                  * The value use for the DQS_ADJUST for the first sample
2097                  * when write leveling is enabled. It probably needs to be
2098                  * overriden per platform.
2099                  */
2100                 wrlvl_start = 0x8;
2101                 /*
2102                  * Override the write leveling sample and start time
2103                  * according to specific board
2104                  */
2105                 if (popts->wrlvl_override) {
2106                         wrlvl_smpl = popts->wrlvl_sample;
2107                         wrlvl_start = popts->wrlvl_start;
2108                 }
2109         }
2110
2111         ddr->ddr_wrlvl_cntl = (0
2112                                | ((wrlvl_en & 0x1) << 31)
2113                                | ((wrlvl_mrd & 0x7) << 24)
2114                                | ((wrlvl_odten & 0x7) << 20)
2115                                | ((wrlvl_dqsen & 0x7) << 16)
2116                                | ((wrlvl_smpl & 0xf) << 12)
2117                                | ((wrlvl_wlr & 0x7) << 8)
2118                                | ((wrlvl_start & 0x1F) << 0)
2119                                );
2120         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2121         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2122         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2123         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2124         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2125
2126 }
2127
2128 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2129 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2130 {
2131         /* Self Refresh Idle Threshold */
2132         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2133 }
2134
2135 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2136 {
2137         if (popts->addr_hash) {
2138                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2139                 puts("Address hashing enabled.\n");
2140         }
2141 }
2142
2143 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2144 {
2145         ddr->ddr_cdr1 = popts->ddr_cdr1;
2146         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2147 }
2148
2149 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2150 {
2151         ddr->ddr_cdr2 = popts->ddr_cdr2;
2152         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2153 }
2154
2155 unsigned int
2156 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2157 {
2158         unsigned int res = 0;
2159
2160         /*
2161          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2162          * not set at the same time.
2163          */
2164         if (ddr->ddr_sdram_cfg & 0x10000000
2165             && ddr->ddr_sdram_cfg & 0x00008000) {
2166                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2167                                 " should not be set at the same time.\n");
2168                 res++;
2169         }
2170
2171         return res;
2172 }
2173
2174 unsigned int
2175 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2176                                const memctl_options_t *popts,
2177                                fsl_ddr_cfg_regs_t *ddr,
2178                                const common_timing_params_t *common_dimm,
2179                                const dimm_params_t *dimm_params,
2180                                unsigned int dbw_cap_adj,
2181                                unsigned int size_only)
2182 {
2183         unsigned int i;
2184         unsigned int cas_latency;
2185         unsigned int additive_latency;
2186         unsigned int sr_it;
2187         unsigned int zq_en;
2188         unsigned int wrlvl_en;
2189         unsigned int ip_rev = 0;
2190         unsigned int unq_mrs_en = 0;
2191         int cs_en = 1;
2192
2193         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2194
2195         if (common_dimm == NULL) {
2196                 printf("Error: subset DIMM params struct null pointer\n");
2197                 return 1;
2198         }
2199
2200         /*
2201          * Process overrides first.
2202          *
2203          * FIXME: somehow add dereated caslat to this
2204          */
2205         cas_latency = (popts->cas_latency_override)
2206                 ? popts->cas_latency_override_value
2207                 : common_dimm->lowest_common_spd_caslat;
2208
2209         additive_latency = (popts->additive_latency_override)
2210                 ? popts->additive_latency_override_value
2211                 : common_dimm->additive_latency;
2212
2213         sr_it = (popts->auto_self_refresh_en)
2214                 ? popts->sr_it
2215                 : 0;
2216         /* ZQ calibration */
2217         zq_en = (popts->zq_en) ? 1 : 0;
2218         /* write leveling */
2219         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2220
2221         /* Chip Select Memory Bounds (CSn_BNDS) */
2222         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2223                 unsigned long long ea, sa;
2224                 unsigned int cs_per_dimm
2225                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2226                 unsigned int dimm_number
2227                         = i / cs_per_dimm;
2228                 unsigned long long rank_density
2229                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2230
2231                 if (dimm_params[dimm_number].n_ranks == 0) {
2232                         debug("Skipping setup of CS%u "
2233                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2234                         continue;
2235                 }
2236                 if (popts->memctl_interleaving) {
2237                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2238                         case FSL_DDR_CS0_CS1_CS2_CS3:
2239                                 break;
2240                         case FSL_DDR_CS0_CS1:
2241                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2242                                 if (i > 1)
2243                                         cs_en = 0;
2244                                 break;
2245                         case FSL_DDR_CS2_CS3:
2246                         default:
2247                                 if (i > 0)
2248                                         cs_en = 0;
2249                                 break;
2250                         }
2251                         sa = common_dimm->base_address;
2252                         ea = sa + common_dimm->total_mem - 1;
2253                 } else if (!popts->memctl_interleaving) {
2254                         /*
2255                          * If memory interleaving between controllers is NOT
2256                          * enabled, the starting address for each memory
2257                          * controller is distinct.  However, because rank
2258                          * interleaving is enabled, the starting and ending
2259                          * addresses of the total memory on that memory
2260                          * controller needs to be programmed into its
2261                          * respective CS0_BNDS.
2262                          */
2263                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2264                         case FSL_DDR_CS0_CS1_CS2_CS3:
2265                                 sa = common_dimm->base_address;
2266                                 ea = sa + common_dimm->total_mem - 1;
2267                                 break;
2268                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2269                                 if ((i >= 2) && (dimm_number == 0)) {
2270                                         sa = dimm_params[dimm_number].base_address +
2271                                               2 * rank_density;
2272                                         ea = sa + 2 * rank_density - 1;
2273                                 } else {
2274                                         sa = dimm_params[dimm_number].base_address;
2275                                         ea = sa + 2 * rank_density - 1;
2276                                 }
2277                                 break;
2278                         case FSL_DDR_CS0_CS1:
2279                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2280                                         sa = dimm_params[dimm_number].base_address;
2281                                         ea = sa + rank_density - 1;
2282                                         if (i != 1)
2283                                                 sa += (i % cs_per_dimm) * rank_density;
2284                                         ea += (i % cs_per_dimm) * rank_density;
2285                                 } else {
2286                                         sa = 0;
2287                                         ea = 0;
2288                                 }
2289                                 if (i == 0)
2290                                         ea += rank_density;
2291                                 break;
2292                         case FSL_DDR_CS2_CS3:
2293                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2294                                         sa = dimm_params[dimm_number].base_address;
2295                                         ea = sa + rank_density - 1;
2296                                         if (i != 3)
2297                                                 sa += (i % cs_per_dimm) * rank_density;
2298                                         ea += (i % cs_per_dimm) * rank_density;
2299                                 } else {
2300                                         sa = 0;
2301                                         ea = 0;
2302                                 }
2303                                 if (i == 2)
2304                                         ea += (rank_density >> dbw_cap_adj);
2305                                 break;
2306                         default:  /* No bank(chip-select) interleaving */
2307                                 sa = dimm_params[dimm_number].base_address;
2308                                 ea = sa + rank_density - 1;
2309                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2310                                         sa += (i % cs_per_dimm) * rank_density;
2311                                         ea += (i % cs_per_dimm) * rank_density;
2312                                 } else {
2313                                         sa = 0;
2314                                         ea = 0;
2315                                 }
2316                                 break;
2317                         }
2318                 }
2319
2320                 sa >>= 24;
2321                 ea >>= 24;
2322
2323                 if (cs_en) {
2324                         ddr->cs[i].bnds = (0
2325                                 | ((sa & 0xffff) << 16) /* starting address */
2326                                 | ((ea & 0xffff) << 0)  /* ending address */
2327                                 );
2328                 } else {
2329                         /* setting bnds to 0xffffffff for inactive CS */
2330                         ddr->cs[i].bnds = 0xffffffff;
2331                 }
2332
2333                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2334                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2335                 set_csn_config_2(i, ddr);
2336         }
2337
2338         /*
2339          * In the case we only need to compute the ddr sdram size, we only need
2340          * to set csn registers, so return from here.
2341          */
2342         if (size_only)
2343                 return 0;
2344
2345         set_ddr_eor(ddr, popts);
2346
2347 #if !defined(CONFIG_SYS_FSL_DDR1)
2348         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2349 #endif
2350
2351         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2352                          additive_latency);
2353         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2354         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2355                          cas_latency, additive_latency);
2356
2357         set_ddr_cdr1(ddr, popts);
2358         set_ddr_cdr2(ddr, popts);
2359         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2360         ip_rev = fsl_ddr_get_version();
2361         if (ip_rev > 0x40400)
2362                 unq_mrs_en = 1;
2363
2364         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2365                 ddr->debug[18] = popts->cswl_override;
2366
2367         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2368         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2369                            cas_latency, additive_latency, unq_mrs_en);
2370         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2371 #ifdef CONFIG_SYS_FSL_DDR4
2372         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2373         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2374 #endif
2375         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2376         set_ddr_data_init(ddr);
2377         set_ddr_sdram_clk_cntl(ddr, popts);
2378         set_ddr_init_addr(ddr);
2379         set_ddr_init_ext_addr(ddr);
2380         set_timing_cfg_4(ddr, popts);
2381         set_timing_cfg_5(ddr, cas_latency);
2382 #ifdef CONFIG_SYS_FSL_DDR4
2383         set_ddr_sdram_cfg_3(ddr, popts);
2384         set_timing_cfg_6(ddr);
2385         set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2386         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2387         set_timing_cfg_9(ddr);
2388         set_ddr_dq_mapping(ddr, dimm_params);
2389 #endif
2390
2391         set_ddr_zq_cntl(ddr, zq_en);
2392         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2393
2394         set_ddr_sr_cntr(ddr, sr_it);
2395
2396         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2397
2398 #ifdef CONFIG_SYS_FSL_DDR_EMU
2399         /* disble DDR training for emulator */
2400         ddr->debug[2] = 0x00000400;
2401         ddr->debug[4] = 0xff800800;
2402         ddr->debug[5] = 0x08000800;
2403         ddr->debug[6] = 0x08000800;
2404         ddr->debug[7] = 0x08000800;
2405         ddr->debug[8] = 0x08000800;
2406 #endif
2407 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2408         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2409                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2410 #endif
2411
2412         return check_fsl_memctl_config_regs(ddr);
2413 }