drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 unsigned int picos_to_mclk(unsigned int picos);
  21
  22 /*
  23  * Determine Rtt value.
  24  *
  25  * This should likely be either board or controller specific.
  26  *
  27  * Rtt(nominal) - DDR2:
  28  *      0 = Rtt disabled
  29  *      1 = 75 ohm
  30  *      2 = 150 ohm
  31  *      3 = 50 ohm
  32  * Rtt(nominal) - DDR3:
  33  *      0 = Rtt disabled
  34  *      1 = 60 ohm
  35  *      2 = 120 ohm
  36  *      3 = 40 ohm
  37  *      4 = 20 ohm
  38  *      5 = 30 ohm
  39  *
  40  * FIXME: Apparently 8641 needs a value of 2
  41  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  42  *
  43  * FIXME: There was some effort down this line earlier:
  44  *
  45  *      unsigned int i;
  46  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  47  *              if (popts->dimmslot[i].num_valid_cs
  48  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  49  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  50  *                      rtt = 2;
  51  *                      break;
  52  *              }
  53  *      }
  54  */
  55 static inline int fsl_ddr_get_rtt(void)
  56 {
  57         int rtt;
  58
  59 #if defined(CONFIG_SYS_FSL_DDR1)
  60         rtt = 0;
  61 #elif defined(CONFIG_SYS_FSL_DDR2)
  62         rtt = 3;
  63 #else
  64         rtt = 0;
  65 #endif
  66
  67         return rtt;
  68 }
  69
  70 #ifdef CONFIG_SYS_FSL_DDR4
  71 /*
  72  * compute CAS write latency according to DDR4 spec
  73  * CWL = 9 for <= 1600MT/s
  74  *       10 for <= 1866MT/s
  75  *       11 for <= 2133MT/s
  76  *       12 for <= 2400MT/s
  77  *       14 for <= 2667MT/s
  78  *       16 for <= 2933MT/s
  79  *       18 for higher
  80  */
  81 static inline unsigned int compute_cas_write_latency(void)
  82 {
  83         unsigned int cwl;
  84         const unsigned int mclk_ps = get_memory_clk_period_ps();
  85         if (mclk_ps >= 1250)
  86                 cwl = 9;
  87         else if (mclk_ps >= 1070)
  88                 cwl = 10;
  89         else if (mclk_ps >= 935)
  90                 cwl = 11;
  91         else if (mclk_ps >= 833)
  92                 cwl = 12;
  93         else if (mclk_ps >= 750)
  94                 cwl = 14;
  95         else if (mclk_ps >= 681)
  96                 cwl = 16;
  97         else
  98                 cwl = 18;
  99
 100         return cwl;
 101 }
 102 #else
 103 /*
 104  * compute the CAS write latency according to DDR3 spec
 105  * CWL = 5 if tCK >= 2.5ns
 106  *       6 if 2.5ns > tCK >= 1.875ns
 107  *       7 if 1.875ns > tCK >= 1.5ns
 108  *       8 if 1.5ns > tCK >= 1.25ns
 109  *       9 if 1.25ns > tCK >= 1.07ns
 110  *       10 if 1.07ns > tCK >= 0.935ns
 111  *       11 if 0.935ns > tCK >= 0.833ns
 112  *       12 if 0.833ns > tCK >= 0.75ns
 113  */
 114 static inline unsigned int compute_cas_write_latency(void)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps();
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 257 {
 258 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 259         if (dimm_params[0].n_ranks == 4)
 260                 return 1;
 261 #endif
 262
 263 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 264         if ((dimm_params[0].n_ranks == 2) &&
 265                 (dimm_params[1].n_ranks == 2))
 266                 return 1;
 267
 268 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 269         if (dimm_params[0].n_ranks == 4)
 270                 return 1;
 271 #endif
 272 #endif
 273         return 0;
 274 }
 275
 276 /*
 277  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 278  *
 279  * Avoid writing for DDR I.  The new PQ38 DDR controller
 280  * dreams up non-zero default values to be backwards compatible.
 281  */
 282 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 283                                 const memctl_options_t *popts,
 284                                 const dimm_params_t *dimm_params)
 285 {
 286         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 287         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 288         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 289         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 290         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 291
 292         /* Active powerdown exit timing (tXARD and tXARDS). */
 293         unsigned char act_pd_exit_mclk;
 294         /* Precharge powerdown exit timing (tXP). */
 295         unsigned char pre_pd_exit_mclk;
 296         /* ODT powerdown exit timing (tAXPD). */
 297         unsigned char taxpd_mclk = 0;
 298         /* Mode register set cycle time (tMRD). */
 299         unsigned char tmrd_mclk;
 300 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 301         const unsigned int mclk_ps = get_memory_clk_period_ps();
 302 #endif
 303
 304 #ifdef CONFIG_SYS_FSL_DDR4
 305         /* tXP=max(4nCK, 6ns) */
 306         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 307         trwt_mclk = 2;
 308         twrt_mclk = 1;
 309         act_pd_exit_mclk = picos_to_mclk(txp);
 310         pre_pd_exit_mclk = act_pd_exit_mclk;
 311         /*
 312          * MRS_CYC = max(tMRD, tMOD)
 313          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 314          */
 315         tmrd_mclk = max(24U, picos_to_mclk(15000));
 316 #elif defined(CONFIG_SYS_FSL_DDR3)
 317         unsigned int data_rate = get_ddr_freq(0);
 318         int txp;
 319         /*
 320          * (tXARD and tXARDS). Empirical?
 321          * The DDR3 spec has not tXARD,
 322          * we use the tXP instead of it.
 323          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 324          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 325          * spec has not the tAXPD, we use
 326          * tAXPD=1, need design to confirm.
 327          */
 328         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 329
 330         tmrd_mclk = 4;
 331         /* set the turnaround time */
 332
 333         /*
 334          * for single quad-rank DIMM and two dual-rank DIMMs
 335          * to avoid ODT overlap
 336          */
 337         if (avoid_odt_overlap(dimm_params)) {
 338                 twwt_mclk = 2;
 339                 trrt_mclk = 1;
 340         }
 341         /* for faster clock, need more time for data setup */
 342         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 343
 344         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 345                 twrt_mclk = 1;
 346
 347         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 348                 act_pd_exit_mclk = 1;
 349                 pre_pd_exit_mclk = 1;
 350                 taxpd_mclk = 1;
 351         } else {
 352                 /* act_pd_exit_mclk = tXARD, see above */
 353                 act_pd_exit_mclk = picos_to_mclk(txp);
 354                 /* Mode register MR0[A12] is '1' - fast exit */
 355                 pre_pd_exit_mclk = act_pd_exit_mclk;
 356                 taxpd_mclk = 1;
 357         }
 358 #else /* CONFIG_SYS_FSL_DDR2 */
 359         /*
 360          * (tXARD and tXARDS). Empirical?
 361          * tXARD = 2 for DDR2
 362          * tXP=2
 363          * tAXPD=8
 364          */
 365         act_pd_exit_mclk = 2;
 366         pre_pd_exit_mclk = 2;
 367         taxpd_mclk = 8;
 368         tmrd_mclk = 2;
 369 #endif
 370
 371         if (popts->trwt_override)
 372                 trwt_mclk = popts->trwt;
 373
 374         ddr->timing_cfg_0 = (0
 375                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 376                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 377                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 378                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 379                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 380                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 381                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 382                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 383                 );
 384         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 385 }
 386 #endif  /* defined(CONFIG_SYS_FSL_DDR2) */
 387
 388 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 389 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 390                                const memctl_options_t *popts,
 391                                const common_timing_params_t *common_dimm,
 392                                unsigned int cas_latency,
 393                                unsigned int additive_latency)
 394 {
 395         /* Extended precharge to activate interval (tRP) */
 396         unsigned int ext_pretoact = 0;
 397         /* Extended Activate to precharge interval (tRAS) */
 398         unsigned int ext_acttopre = 0;
 399         /* Extended activate to read/write interval (tRCD) */
 400         unsigned int ext_acttorw = 0;
 401         /* Extended refresh recovery time (tRFC) */
 402         unsigned int ext_refrec;
 403         /* Extended MCAS latency from READ cmd */
 404         unsigned int ext_caslat = 0;
 405         /* Extended additive latency */
 406         unsigned int ext_add_lat = 0;
 407         /* Extended last data to precharge interval (tWR) */
 408         unsigned int ext_wrrec = 0;
 409         /* Control Adjust */
 410         unsigned int cntl_adj = 0;
 411
 412         ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
 413         ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
 414         ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 415         ext_caslat = (2 * cas_latency - 1) >> 4;
 416         ext_add_lat = additive_latency >> 4;
 417 #ifdef CONFIG_SYS_FSL_DDR4
 418         ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4;
 419 #else
 420         ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 421         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 422 #endif
 423         ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
 424                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 425
 426         ddr->timing_cfg_3 = (0
 427                 | ((ext_pretoact & 0x1) << 28)
 428                 | ((ext_acttopre & 0x3) << 24)
 429                 | ((ext_acttorw & 0x1) << 22)
 430                 | ((ext_refrec & 0x1F) << 16)
 431                 | ((ext_caslat & 0x3) << 12)
 432                 | ((ext_add_lat & 0x1) << 10)
 433                 | ((ext_wrrec & 0x1) << 8)
 434                 | ((cntl_adj & 0x7) << 0)
 435                 );
 436         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 437 }
 438
 439 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 440 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 441                                const memctl_options_t *popts,
 442                                const common_timing_params_t *common_dimm,
 443                                unsigned int cas_latency)
 444 {
 445         /* Precharge-to-activate interval (tRP) */
 446         unsigned char pretoact_mclk;
 447         /* Activate to precharge interval (tRAS) */
 448         unsigned char acttopre_mclk;
 449         /*  Activate to read/write interval (tRCD) */
 450         unsigned char acttorw_mclk;
 451         /* CASLAT */
 452         unsigned char caslat_ctrl;
 453         /*  Refresh recovery time (tRFC) ; trfc_low */
 454         unsigned char refrec_ctrl;
 455         /* Last data to precharge minimum interval (tWR) */
 456         unsigned char wrrec_mclk;
 457         /* Activate-to-activate interval (tRRD) */
 458         unsigned char acttoact_mclk;
 459         /* Last write data pair to read command issue interval (tWTR) */
 460         unsigned char wrtord_mclk;
 461 #ifdef CONFIG_SYS_FSL_DDR4
 462         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 463         static const u8 wrrec_table[] = {
 464                 10, 10, 10, 10, 10,
 465                 10, 10, 10, 10, 10,
 466                 12, 12, 14, 14, 16,
 467                 16, 18, 18, 20, 20,
 468                 24, 24, 24, 24};
 469 #else
 470         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 471         static const u8 wrrec_table[] = {
 472                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 473 #endif
 474
 475         pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
 476         acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
 477         acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 478
 479         /*
 480          * Translate CAS Latency to a DDR controller field value:
 481          *
 482          *      CAS Lat DDR I   DDR II  Ctrl
 483          *      Clocks  SPD Bit SPD Bit Value
 484          *      ------- ------- ------- -----
 485          *      1.0     0               0001
 486          *      1.5     1               0010
 487          *      2.0     2       2       0011
 488          *      2.5     3               0100
 489          *      3.0     4       3       0101
 490          *      3.5     5               0110
 491          *      4.0             4       0111
 492          *      4.5                     1000
 493          *      5.0             5       1001
 494          */
 495 #if defined(CONFIG_SYS_FSL_DDR1)
 496         caslat_ctrl = (cas_latency + 1) & 0x07;
 497 #elif defined(CONFIG_SYS_FSL_DDR2)
 498         caslat_ctrl = 2 * cas_latency - 1;
 499 #else
 500         /*
 501          * if the CAS latency more than 8 cycle,
 502          * we need set extend bit for it at
 503          * TIMING_CFG_3[EXT_CASLAT]
 504          */
 505         if (fsl_ddr_get_version() <= 0x40400)
 506                 caslat_ctrl = 2 * cas_latency - 1;
 507         else
 508                 caslat_ctrl = (cas_latency - 1) << 1;
 509 #endif
 510
 511 #ifdef CONFIG_SYS_FSL_DDR4
 512         refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8;
 513         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 514         acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U);
 515         wrtord_mclk = max(2U, picos_to_mclk(2500));
 516         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 517                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 518         else
 519                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 520 #else
 521         refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
 522         wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 523         acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 524         wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 525         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 526                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 527         else
 528                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 529 #endif
 530         if (popts->otf_burst_chop_en)
 531                 wrrec_mclk += 2;
 532
 533         /*
 534          * JEDEC has min requirement for tRRD
 535          */
 536 #if defined(CONFIG_SYS_FSL_DDR3)
 537         if (acttoact_mclk < 4)
 538                 acttoact_mclk = 4;
 539 #endif
 540         /*
 541          * JEDEC has some min requirements for tWTR
 542          */
 543 #if defined(CONFIG_SYS_FSL_DDR2)
 544         if (wrtord_mclk < 2)
 545                 wrtord_mclk = 2;
 546 #elif defined(CONFIG_SYS_FSL_DDR3)
 547         if (wrtord_mclk < 4)
 548                 wrtord_mclk = 4;
 549 #endif
 550         if (popts->otf_burst_chop_en)
 551                 wrtord_mclk += 2;
 552
 553         ddr->timing_cfg_1 = (0
 554                 | ((pretoact_mclk & 0x0F) << 28)
 555                 | ((acttopre_mclk & 0x0F) << 24)
 556                 | ((acttorw_mclk & 0xF) << 20)
 557                 | ((caslat_ctrl & 0xF) << 16)
 558                 | ((refrec_ctrl & 0xF) << 12)
 559                 | ((wrrec_mclk & 0x0F) << 8)
 560                 | ((acttoact_mclk & 0x0F) << 4)
 561                 | ((wrtord_mclk & 0x0F) << 0)
 562                 );
 563         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 564 }
 565
 566 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 567 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 568                                const memctl_options_t *popts,
 569                                const common_timing_params_t *common_dimm,
 570                                unsigned int cas_latency,
 571                                unsigned int additive_latency)
 572 {
 573         /* Additive latency */
 574         unsigned char add_lat_mclk;
 575         /* CAS-to-preamble override */
 576         unsigned short cpo;
 577         /* Write latency */
 578         unsigned char wr_lat;
 579         /*  Read to precharge (tRTP) */
 580         unsigned char rd_to_pre;
 581         /* Write command to write data strobe timing adjustment */
 582         unsigned char wr_data_delay;
 583         /* Minimum CKE pulse width (tCKE) */
 584         unsigned char cke_pls;
 585         /* Window for four activates (tFAW) */
 586         unsigned short four_act;
 587 #ifdef CONFIG_SYS_FSL_DDR3
 588         const unsigned int mclk_ps = get_memory_clk_period_ps();
 589 #endif
 590
 591         /* FIXME add check that this must be less than acttorw_mclk */
 592         add_lat_mclk = additive_latency;
 593         cpo = popts->cpo_override;
 594
 595 #if defined(CONFIG_SYS_FSL_DDR1)
 596         /*
 597          * This is a lie.  It should really be 1, but if it is
 598          * set to 1, bits overlap into the old controller's
 599          * otherwise unused ACSM field.  If we leave it 0, then
 600          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 601          */
 602         wr_lat = 0;
 603 #elif defined(CONFIG_SYS_FSL_DDR2)
 604         wr_lat = cas_latency - 1;
 605 #else
 606         wr_lat = compute_cas_write_latency();
 607 #endif
 608
 609 #ifdef CONFIG_SYS_FSL_DDR4
 610         rd_to_pre = picos_to_mclk(7500);
 611 #else
 612         rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 613 #endif
 614         /*
 615          * JEDEC has some min requirements for tRTP
 616          */
 617 #if defined(CONFIG_SYS_FSL_DDR2)
 618         if (rd_to_pre  < 2)
 619                 rd_to_pre  = 2;
 620 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 621         if (rd_to_pre < 4)
 622                 rd_to_pre = 4;
 623 #endif
 624         if (popts->otf_burst_chop_en)
 625                 rd_to_pre += 2; /* according to UM */
 626
 627         wr_data_delay = popts->write_data_delay;
 628 #ifdef CONFIG_SYS_FSL_DDR4
 629         cpo = 0;
 630         cke_pls = max(3U, picos_to_mclk(5000));
 631 #elif defined(CONFIG_SYS_FSL_DDR3)
 632         /*
 633          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 634          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 635          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 636          */
 637         cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 :
 638                                        (mclk_ps > 1245 ? 5625 : 5000)));
 639 #else
 640         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 641 #endif
 642         four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 643
 644         ddr->timing_cfg_2 = (0
 645                 | ((add_lat_mclk & 0xf) << 28)
 646                 | ((cpo & 0x1f) << 23)
 647                 | ((wr_lat & 0xf) << 19)
 648                 | ((wr_lat & 0x10) << 14)
 649                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 650                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 651                 | ((cke_pls & 0x7) << 6)
 652                 | ((four_act & 0x3f) << 0)
 653                 );
 654         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 655 }
 656
 657 /* DDR SDRAM Register Control Word */
 658 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 659                                const memctl_options_t *popts,
 660                                const common_timing_params_t *common_dimm)
 661 {
 662         if (common_dimm->all_dimms_registered &&
 663             !common_dimm->all_dimms_unbuffered) {
 664                 if (popts->rcw_override) {
 665                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 666                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 667                 } else {
 668                         ddr->ddr_sdram_rcw_1 =
 669                                 common_dimm->rcw[0] << 28 | \
 670                                 common_dimm->rcw[1] << 24 | \
 671                                 common_dimm->rcw[2] << 20 | \
 672                                 common_dimm->rcw[3] << 16 | \
 673                                 common_dimm->rcw[4] << 12 | \
 674                                 common_dimm->rcw[5] << 8 | \
 675                                 common_dimm->rcw[6] << 4 | \
 676                                 common_dimm->rcw[7];
 677                         ddr->ddr_sdram_rcw_2 =
 678                                 common_dimm->rcw[8] << 28 | \
 679                                 common_dimm->rcw[9] << 24 | \
 680                                 common_dimm->rcw[10] << 20 | \
 681                                 common_dimm->rcw[11] << 16 | \
 682                                 common_dimm->rcw[12] << 12 | \
 683                                 common_dimm->rcw[13] << 8 | \
 684                                 common_dimm->rcw[14] << 4 | \
 685                                 common_dimm->rcw[15];
 686                 }
 687                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 688                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 689         }
 690 }
 691
 692 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 693 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 694                                const memctl_options_t *popts,
 695                                const common_timing_params_t *common_dimm)
 696 {
 697         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 698         unsigned int sren;              /* Self refresh enable (during sleep) */
 699         unsigned int ecc_en;            /* ECC enable. */
 700         unsigned int rd_en;             /* Registered DIMM enable */
 701         unsigned int sdram_type;        /* Type of SDRAM */
 702         unsigned int dyn_pwr;           /* Dynamic power management mode */
 703         unsigned int dbw;               /* DRAM dta bus width */
 704         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 705         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 706         unsigned int threet_en;         /* Enable 3T timing */
 707         unsigned int twot_en;           /* Enable 2T timing */
 708         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 709         unsigned int x32_en = 0;        /* x32 enable */
 710         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 711         unsigned int hse;               /* Global half strength override */
 712         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 713         unsigned int mem_halt = 0;      /* memory controller halt */
 714         unsigned int bi = 0;            /* Bypass initialization */
 715
 716         mem_en = 1;
 717         sren = popts->self_refresh_in_sleep;
 718         if (common_dimm->all_dimms_ecc_capable) {
 719                 /* Allow setting of ECC only if all DIMMs are ECC. */
 720                 ecc_en = popts->ecc_mode;
 721         } else {
 722                 ecc_en = 0;
 723         }
 724
 725         if (common_dimm->all_dimms_registered &&
 726             !common_dimm->all_dimms_unbuffered) {
 727                 rd_en = 1;
 728                 twot_en = 0;
 729         } else {
 730                 rd_en = 0;
 731                 twot_en = popts->twot_en;
 732         }
 733
 734         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 735
 736         dyn_pwr = popts->dynamic_power;
 737         dbw = popts->data_bus_width;
 738         /* 8-beat burst enable DDR-III case
 739          * we must clear it when use the on-the-fly mode,
 740          * must set it when use the 32-bits bus mode.
 741          */
 742         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 743             (sdram_type == SDRAM_TYPE_DDR4)) {
 744                 if (popts->burst_length == DDR_BL8)
 745                         eight_be = 1;
 746                 if (popts->burst_length == DDR_OTF)
 747                         eight_be = 0;
 748                 if (dbw == 0x1)
 749                         eight_be = 1;
 750         }
 751
 752         threet_en = popts->threet_en;
 753         ba_intlv_ctl = popts->ba_intlv_ctl;
 754         hse = popts->half_strength_driver_enable;
 755
 756         /* set when ddr bus width < 64 */
 757         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 758
 759         ddr->ddr_sdram_cfg = (0
 760                         | ((mem_en & 0x1) << 31)
 761                         | ((sren & 0x1) << 30)
 762                         | ((ecc_en & 0x1) << 29)
 763                         | ((rd_en & 0x1) << 28)
 764                         | ((sdram_type & 0x7) << 24)
 765                         | ((dyn_pwr & 0x1) << 21)
 766                         | ((dbw & 0x3) << 19)
 767                         | ((eight_be & 0x1) << 18)
 768                         | ((ncap & 0x1) << 17)
 769                         | ((threet_en & 0x1) << 16)
 770                         | ((twot_en & 0x1) << 15)
 771                         | ((ba_intlv_ctl & 0x7F) << 8)
 772                         | ((x32_en & 0x1) << 5)
 773                         | ((pchb8 & 0x1) << 4)
 774                         | ((hse & 0x1) << 3)
 775                         | ((acc_ecc_en & 0x1) << 2)
 776                         | ((mem_halt & 0x1) << 1)
 777                         | ((bi & 0x1) << 0)
 778                         );
 779         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 780 }
 781
 782 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 783 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 784                                const memctl_options_t *popts,
 785                                const unsigned int unq_mrs_en)
 786 {
 787         unsigned int frc_sr = 0;        /* Force self refresh */
 788         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 789         unsigned int odt_cfg = 0;       /* ODT configuration */
 790         unsigned int num_pr;            /* Number of posted refreshes */
 791         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 792         unsigned int x4_en = 0;         /* x4 DRAM enable */
 793         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 794         unsigned int ap_en;             /* Address Parity Enable */
 795         unsigned int d_init;            /* DRAM data initialization */
 796         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 797         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 798         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 799         int i;
 800 #ifndef CONFIG_SYS_FSL_DDR4
 801         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 802         unsigned int dqs_cfg;           /* DQS configuration */
 803
 804         dqs_cfg = popts->dqs_config;
 805 #endif
 806         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 807                 if (popts->cs_local_opts[i].odt_rd_cfg
 808                         || popts->cs_local_opts[i].odt_wr_cfg) {
 809                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 810                         break;
 811                 }
 812         }
 813
 814         num_pr = 1;     /* Make this configurable */
 815
 816         /*
 817          * 8572 manual says
 818          *     {TIMING_CFG_1[PRETOACT]
 819          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 820          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 821          *      << DDR_SDRAM_INTERVAL[REFINT]
 822          */
 823 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 824         obc_cfg = popts->otf_burst_chop_en;
 825 #else
 826         obc_cfg = 0;
 827 #endif
 828
 829 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 830         slow = get_ddr_freq(0) < 1249000000;
 831 #endif
 832
 833         if (popts->registered_dimm_en) {
 834                 rcw_en = 1;
 835                 ap_en = popts->ap_en;
 836         } else {
 837                 ap_en = 0;
 838         }
 839
 840         x4_en = popts->x4_en ? 1 : 0;
 841
 842 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 843         /* Use the DDR controller to auto initialize memory. */
 844         d_init = popts->ecc_init_using_memctl;
 845         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 846         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 847 #else
 848         /* Memory will be initialized via DMA, or not at all. */
 849         d_init = 0;
 850 #endif
 851
 852 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 853         md_en = popts->mirrored_dimm;
 854 #endif
 855         qd_en = popts->quad_rank_present ? 1 : 0;
 856         ddr->ddr_sdram_cfg_2 = (0
 857                 | ((frc_sr & 0x1) << 31)
 858                 | ((sr_ie & 0x1) << 30)
 859 #ifndef CONFIG_SYS_FSL_DDR4
 860                 | ((dll_rst_dis & 0x1) << 29)
 861                 | ((dqs_cfg & 0x3) << 26)
 862 #endif
 863                 | ((odt_cfg & 0x3) << 21)
 864                 | ((num_pr & 0xf) << 12)
 865                 | ((slow & 1) << 11)
 866                 | (x4_en << 10)
 867                 | (qd_en << 9)
 868                 | (unq_mrs_en << 8)
 869                 | ((obc_cfg & 0x1) << 6)
 870                 | ((ap_en & 0x1) << 5)
 871                 | ((d_init & 0x1) << 4)
 872                 | ((rcw_en & 0x1) << 2)
 873                 | ((md_en & 0x1) << 0)
 874                 );
 875         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 876 }
 877
 878 #ifdef CONFIG_SYS_FSL_DDR4
 879 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 880 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 881                                 const memctl_options_t *popts,
 882                                 const common_timing_params_t *common_dimm,
 883                                 const unsigned int unq_mrs_en)
 884 {
 885         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 886         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 887         int i;
 888         unsigned int wr_crc = 0;        /* Disable */
 889         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 890         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 891         unsigned int cwl = compute_cas_write_latency() - 9;
 892         unsigned int mpr = 0;   /* serial */
 893         unsigned int wc_lat;
 894         const unsigned int mclk_ps = get_memory_clk_period_ps();
 895
 896         if (popts->rtt_override)
 897                 rtt_wr = popts->rtt_wr_override_value;
 898         else
 899                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 900
 901         if (common_dimm->extended_op_srt)
 902                 srt = common_dimm->extended_op_srt;
 903
 904         esdmode2 = (0
 905                 | ((wr_crc & 0x1) << 12)
 906                 | ((rtt_wr & 0x3) << 9)
 907                 | ((srt & 0x3) << 6)
 908                 | ((cwl & 0x7) << 3));
 909
 910         if (mclk_ps >= 1250)
 911                 wc_lat = 0;
 912         else if (mclk_ps >= 833)
 913                 wc_lat = 1;
 914         else
 915                 wc_lat = 2;
 916
 917         esdmode3 = (0
 918                 | ((mpr & 0x3) << 11)
 919                 | ((wc_lat & 0x3) << 9));
 920
 921         ddr->ddr_sdram_mode_2 = (0
 922                                  | ((esdmode2 & 0xFFFF) << 16)
 923                                  | ((esdmode3 & 0xFFFF) << 0)
 924                                  );
 925         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 926
 927         if (unq_mrs_en) {       /* unique mode registers are supported */
 928                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 929                         if (popts->rtt_override)
 930                                 rtt_wr = popts->rtt_wr_override_value;
 931                         else
 932                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 933
 934                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 935                         esdmode2 |= (rtt_wr & 0x3) << 9;
 936                         switch (i) {
 937                         case 1:
 938                                 ddr->ddr_sdram_mode_4 = (0
 939                                         | ((esdmode2 & 0xFFFF) << 16)
 940                                         | ((esdmode3 & 0xFFFF) << 0)
 941                                         );
 942                                 break;
 943                         case 2:
 944                                 ddr->ddr_sdram_mode_6 = (0
 945                                         | ((esdmode2 & 0xFFFF) << 16)
 946                                         | ((esdmode3 & 0xFFFF) << 0)
 947                                         );
 948                                 break;
 949                         case 3:
 950                                 ddr->ddr_sdram_mode_8 = (0
 951                                         | ((esdmode2 & 0xFFFF) << 16)
 952                                         | ((esdmode3 & 0xFFFF) << 0)
 953                                         );
 954                                 break;
 955                         }
 956                 }
 957                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
 958                       ddr->ddr_sdram_mode_4);
 959                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
 960                       ddr->ddr_sdram_mode_6);
 961                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
 962                       ddr->ddr_sdram_mode_8);
 963         }
 964 }
 965 #elif defined(CONFIG_SYS_FSL_DDR3)
 966 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 967 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 968                                 const memctl_options_t *popts,
 969                                 const common_timing_params_t *common_dimm,
 970                                 const unsigned int unq_mrs_en)
 971 {
 972         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 973         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 974         int i;
 975         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 976         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 977         unsigned int asr = 0;   /* auto self-refresh disable */
 978         unsigned int cwl = compute_cas_write_latency() - 5;
 979         unsigned int pasr = 0;  /* partial array self refresh disable */
 980
 981         if (popts->rtt_override)
 982                 rtt_wr = popts->rtt_wr_override_value;
 983         else
 984                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 985
 986         if (common_dimm->extended_op_srt)
 987                 srt = common_dimm->extended_op_srt;
 988
 989         esdmode2 = (0
 990                 | ((rtt_wr & 0x3) << 9)
 991                 | ((srt & 0x1) << 7)
 992                 | ((asr & 0x1) << 6)
 993                 | ((cwl & 0x7) << 3)
 994                 | ((pasr & 0x7) << 0));
 995         ddr->ddr_sdram_mode_2 = (0
 996                                  | ((esdmode2 & 0xFFFF) << 16)
 997                                  | ((esdmode3 & 0xFFFF) << 0)
 998                                  );
 999         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1000
1001         if (unq_mrs_en) {       /* unique mode registers are supported */
1002                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1003                         if (popts->rtt_override)
1004                                 rtt_wr = popts->rtt_wr_override_value;
1005                         else
1006                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1007
1008                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1009                         esdmode2 |= (rtt_wr & 0x3) << 9;
1010                         switch (i) {
1011                         case 1:
1012                                 ddr->ddr_sdram_mode_4 = (0
1013                                         | ((esdmode2 & 0xFFFF) << 16)
1014                                         | ((esdmode3 & 0xFFFF) << 0)
1015                                         );
1016                                 break;
1017                         case 2:
1018                                 ddr->ddr_sdram_mode_6 = (0
1019                                         | ((esdmode2 & 0xFFFF) << 16)
1020                                         | ((esdmode3 & 0xFFFF) << 0)
1021                                         );
1022                                 break;
1023                         case 3:
1024                                 ddr->ddr_sdram_mode_8 = (0
1025                                         | ((esdmode2 & 0xFFFF) << 16)
1026                                         | ((esdmode3 & 0xFFFF) << 0)
1027                                         );
1028                                 break;
1029                         }
1030                 }
1031                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1032                         ddr->ddr_sdram_mode_4);
1033                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1034                         ddr->ddr_sdram_mode_6);
1035                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1036                         ddr->ddr_sdram_mode_8);
1037         }
1038 }
1039
1040 #else /* for DDR2 and DDR1 */
1041 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1042 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
1043                                 const memctl_options_t *popts,
1044                                 const common_timing_params_t *common_dimm,
1045                                 const unsigned int unq_mrs_en)
1046 {
1047         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1048         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1049
1050         ddr->ddr_sdram_mode_2 = (0
1051                                  | ((esdmode2 & 0xFFFF) << 16)
1052                                  | ((esdmode3 & 0xFFFF) << 0)
1053                                  );
1054         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1055 }
1056 #endif
1057
1058 #ifdef CONFIG_SYS_FSL_DDR4
1059 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1060 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1061                                 const memctl_options_t *popts,
1062                                 const common_timing_params_t *common_dimm,
1063                                 const unsigned int unq_mrs_en)
1064 {
1065         int i;
1066         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1067         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1068
1069         esdmode5 = 0x00000400;          /* Data mask enabled */
1070
1071         ddr->ddr_sdram_mode_9 = (0
1072                                  | ((esdmode4 & 0xffff) << 16)
1073                                  | ((esdmode5 & 0xffff) << 0)
1074                                 );
1075         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1076         if (unq_mrs_en) {       /* unique mode registers are supported */
1077                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1078                         switch (i) {
1079                         case 1:
1080                                 ddr->ddr_sdram_mode_11 = (0
1081                                         | ((esdmode4 & 0xFFFF) << 16)
1082                                         | ((esdmode5 & 0xFFFF) << 0)
1083                                         );
1084                                 break;
1085                         case 2:
1086                                 ddr->ddr_sdram_mode_13 = (0
1087                                         | ((esdmode4 & 0xFFFF) << 16)
1088                                         | ((esdmode5 & 0xFFFF) << 0)
1089                                         );
1090                                 break;
1091                         case 3:
1092                                 ddr->ddr_sdram_mode_15 = (0
1093                                         | ((esdmode4 & 0xFFFF) << 16)
1094                                         | ((esdmode5 & 0xFFFF) << 0)
1095                                         );
1096                                 break;
1097                         }
1098                 }
1099                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1100                       ddr->ddr_sdram_mode_11);
1101                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1102                       ddr->ddr_sdram_mode_13);
1103                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1104                       ddr->ddr_sdram_mode_15);
1105         }
1106 }
1107
1108 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1109 static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr,
1110                                 const memctl_options_t *popts,
1111                                 const common_timing_params_t *common_dimm,
1112                                 const unsigned int unq_mrs_en)
1113 {
1114         int i;
1115         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1116         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1117         unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps);
1118
1119         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1120
1121         ddr->ddr_sdram_mode_10 = (0
1122                                  | ((esdmode6 & 0xffff) << 16)
1123                                  | ((esdmode7 & 0xffff) << 0)
1124                                 );
1125         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1126         if (unq_mrs_en) {       /* unique mode registers are supported */
1127                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1128                         switch (i) {
1129                         case 1:
1130                                 ddr->ddr_sdram_mode_12 = (0
1131                                         | ((esdmode6 & 0xFFFF) << 16)
1132                                         | ((esdmode7 & 0xFFFF) << 0)
1133                                         );
1134                                 break;
1135                         case 2:
1136                                 ddr->ddr_sdram_mode_14 = (0
1137                                         | ((esdmode6 & 0xFFFF) << 16)
1138                                         | ((esdmode7 & 0xFFFF) << 0)
1139                                         );
1140                                 break;
1141                         case 3:
1142                                 ddr->ddr_sdram_mode_16 = (0
1143                                         | ((esdmode6 & 0xFFFF) << 16)
1144                                         | ((esdmode7 & 0xFFFF) << 0)
1145                                         );
1146                                 break;
1147                         }
1148                 }
1149                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1150                       ddr->ddr_sdram_mode_12);
1151                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1152                       ddr->ddr_sdram_mode_14);
1153                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1154                       ddr->ddr_sdram_mode_16);
1155         }
1156 }
1157
1158 #endif
1159
1160 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1161 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
1162                                const memctl_options_t *popts,
1163                                const common_timing_params_t *common_dimm)
1164 {
1165         unsigned int refint;    /* Refresh interval */
1166         unsigned int bstopre;   /* Precharge interval */
1167
1168         refint = picos_to_mclk(common_dimm->refresh_rate_ps);
1169
1170         bstopre = popts->bstopre;
1171
1172         /* refint field used 0x3FFF in earlier controllers */
1173         ddr->ddr_sdram_interval = (0
1174                                    | ((refint & 0xFFFF) << 16)
1175                                    | ((bstopre & 0x3FFF) << 0)
1176                                    );
1177         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1178 }
1179
1180 #ifdef CONFIG_SYS_FSL_DDR4
1181 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1182 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1183                                const memctl_options_t *popts,
1184                                const common_timing_params_t *common_dimm,
1185                                unsigned int cas_latency,
1186                                unsigned int additive_latency,
1187                                const unsigned int unq_mrs_en)
1188 {
1189         int i;
1190         unsigned short esdmode;         /* Extended SDRAM mode */
1191         unsigned short sdmode;          /* SDRAM mode */
1192
1193         /* Mode Register - MR1 */
1194         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1195         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1196         unsigned int rtt;
1197         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1198         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1199         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1200         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1201                                                        0=Disable (Test/Debug) */
1202
1203         /* Mode Register - MR0 */
1204         unsigned int wr = 0;    /* Write Recovery */
1205         unsigned int dll_rst;   /* DLL Reset */
1206         unsigned int mode;      /* Normal=0 or Test=1 */
1207         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1208         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1209         unsigned int bt;
1210         unsigned int bl;        /* BL: Burst Length */
1211
1212         unsigned int wr_mclk;
1213         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1214         static const u8 wr_table[] = {
1215                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1216         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1217         static const u8 cas_latency_table[] = {
1218                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1219                 9, 9, 10, 10, 11, 11};
1220
1221         if (popts->rtt_override)
1222                 rtt = popts->rtt_override_value;
1223         else
1224                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1225
1226         if (additive_latency == (cas_latency - 1))
1227                 al = 1;
1228         if (additive_latency == (cas_latency - 2))
1229                 al = 2;
1230
1231         if (popts->quad_rank_present)
1232                 dic = 1;        /* output driver impedance 240/7 ohm */
1233
1234         /*
1235          * The esdmode value will also be used for writing
1236          * MR1 during write leveling for DDR3, although the
1237          * bits specifically related to the write leveling
1238          * scheme will be handled automatically by the DDR
1239          * controller. so we set the wrlvl_en = 0 here.
1240          */
1241         esdmode = (0
1242                 | ((qoff & 0x1) << 12)
1243                 | ((tdqs_en & 0x1) << 11)
1244                 | ((rtt & 0x7) << 8)
1245                 | ((wrlvl_en & 0x1) << 7)
1246                 | ((al & 0x3) << 3)
1247                 | ((dic & 0x3) << 1)   /* DIC field is split */
1248                 | ((dll_en & 0x1) << 0)
1249                 );
1250
1251         /*
1252          * DLL control for precharge PD
1253          * 0=slow exit DLL off (tXPDLL)
1254          * 1=fast exit DLL on (tXP)
1255          */
1256
1257         wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1258         if (wr_mclk <= 24) {
1259                 wr = wr_table[wr_mclk - 10];
1260         } else {
1261                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1262                        wr_mclk);
1263         }
1264
1265         dll_rst = 0;    /* dll no reset */
1266         mode = 0;       /* normal mode */
1267
1268         /* look up table to get the cas latency bits */
1269         if (cas_latency >= 9 && cas_latency <= 24)
1270                 caslat = cas_latency_table[cas_latency - 9];
1271         else
1272                 printf("Error: unsupported cas latency for mode register\n");
1273
1274         bt = 0; /* Nibble sequential */
1275
1276         switch (popts->burst_length) {
1277         case DDR_BL8:
1278                 bl = 0;
1279                 break;
1280         case DDR_OTF:
1281                 bl = 1;
1282                 break;
1283         case DDR_BC4:
1284                 bl = 2;
1285                 break;
1286         default:
1287                 printf("Error: invalid burst length of %u specified. ",
1288                        popts->burst_length);
1289                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1290                 bl = 1;
1291                 break;
1292         }
1293
1294         sdmode = (0
1295                   | ((wr & 0x7) << 9)
1296                   | ((dll_rst & 0x1) << 8)
1297                   | ((mode & 0x1) << 7)
1298                   | (((caslat >> 1) & 0x7) << 4)
1299                   | ((bt & 0x1) << 3)
1300                   | ((caslat & 1) << 2)
1301                   | ((bl & 0x3) << 0)
1302                   );
1303
1304         ddr->ddr_sdram_mode = (0
1305                                | ((esdmode & 0xFFFF) << 16)
1306                                | ((sdmode & 0xFFFF) << 0)
1307                                );
1308
1309         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1310
1311         if (unq_mrs_en) {       /* unique mode registers are supported */
1312                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1313                         if (popts->rtt_override)
1314                                 rtt = popts->rtt_override_value;
1315                         else
1316                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1317
1318                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1319                         esdmode |= (rtt & 0x7) << 8;
1320                         switch (i) {
1321                         case 1:
1322                                 ddr->ddr_sdram_mode_3 = (0
1323                                        | ((esdmode & 0xFFFF) << 16)
1324                                        | ((sdmode & 0xFFFF) << 0)
1325                                        );
1326                                 break;
1327                         case 2:
1328                                 ddr->ddr_sdram_mode_5 = (0
1329                                        | ((esdmode & 0xFFFF) << 16)
1330                                        | ((sdmode & 0xFFFF) << 0)
1331                                        );
1332                                 break;
1333                         case 3:
1334                                 ddr->ddr_sdram_mode_7 = (0
1335                                        | ((esdmode & 0xFFFF) << 16)
1336                                        | ((sdmode & 0xFFFF) << 0)
1337                                        );
1338                                 break;
1339                         }
1340                 }
1341                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1342                       ddr->ddr_sdram_mode_3);
1343                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1344                       ddr->ddr_sdram_mode_5);
1345                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1346                       ddr->ddr_sdram_mode_5);
1347         }
1348 }
1349
1350 #elif defined(CONFIG_SYS_FSL_DDR3)
1351 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1352 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1353                                const memctl_options_t *popts,
1354                                const common_timing_params_t *common_dimm,
1355                                unsigned int cas_latency,
1356                                unsigned int additive_latency,
1357                                const unsigned int unq_mrs_en)
1358 {
1359         int i;
1360         unsigned short esdmode;         /* Extended SDRAM mode */
1361         unsigned short sdmode;          /* SDRAM mode */
1362
1363         /* Mode Register - MR1 */
1364         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1365         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1366         unsigned int rtt;
1367         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1368         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1369         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1370         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1371                                                        1=Disable (Test/Debug) */
1372
1373         /* Mode Register - MR0 */
1374         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1375         unsigned int wr = 0;    /* Write Recovery */
1376         unsigned int dll_rst;   /* DLL Reset */
1377         unsigned int mode;      /* Normal=0 or Test=1 */
1378         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1379         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1380         unsigned int bt;
1381         unsigned int bl;        /* BL: Burst Length */
1382
1383         unsigned int wr_mclk;
1384         /*
1385          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1386          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1387          * for this table
1388          */
1389         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1390
1391         if (popts->rtt_override)
1392                 rtt = popts->rtt_override_value;
1393         else
1394                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1395
1396         if (additive_latency == (cas_latency - 1))
1397                 al = 1;
1398         if (additive_latency == (cas_latency - 2))
1399                 al = 2;
1400
1401         if (popts->quad_rank_present)
1402                 dic = 1;        /* output driver impedance 240/7 ohm */
1403
1404         /*
1405          * The esdmode value will also be used for writing
1406          * MR1 during write leveling for DDR3, although the
1407          * bits specifically related to the write leveling
1408          * scheme will be handled automatically by the DDR
1409          * controller. so we set the wrlvl_en = 0 here.
1410          */
1411         esdmode = (0
1412                 | ((qoff & 0x1) << 12)
1413                 | ((tdqs_en & 0x1) << 11)
1414                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1415                 | ((wrlvl_en & 0x1) << 7)
1416                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1417                 | ((dic & 0x2) << 4)   /* DIC field is split */
1418                 | ((al & 0x3) << 3)
1419                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1420                 | ((dic & 0x1) << 1)   /* DIC field is split */
1421                 | ((dll_en & 0x1) << 0)
1422                 );
1423
1424         /*
1425          * DLL control for precharge PD
1426          * 0=slow exit DLL off (tXPDLL)
1427          * 1=fast exit DLL on (tXP)
1428          */
1429         dll_on = 1;
1430
1431         wr_mclk = picos_to_mclk(common_dimm->twr_ps);
1432         if (wr_mclk <= 16) {
1433                 wr = wr_table[wr_mclk - 5];
1434         } else {
1435                 printf("Error: unsupported write recovery for mode register "
1436                        "wr_mclk = %d\n", wr_mclk);
1437         }
1438
1439         dll_rst = 0;    /* dll no reset */
1440         mode = 0;       /* normal mode */
1441
1442         /* look up table to get the cas latency bits */
1443         if (cas_latency >= 5 && cas_latency <= 16) {
1444                 unsigned char cas_latency_table[] = {
1445                         0x2,    /* 5 clocks */
1446                         0x4,    /* 6 clocks */
1447                         0x6,    /* 7 clocks */
1448                         0x8,    /* 8 clocks */
1449                         0xa,    /* 9 clocks */
1450                         0xc,    /* 10 clocks */
1451                         0xe,    /* 11 clocks */
1452                         0x1,    /* 12 clocks */
1453                         0x3,    /* 13 clocks */
1454                         0x5,    /* 14 clocks */
1455                         0x7,    /* 15 clocks */
1456                         0x9,    /* 16 clocks */
1457                 };
1458                 caslat = cas_latency_table[cas_latency - 5];
1459         } else {
1460                 printf("Error: unsupported cas latency for mode register\n");
1461         }
1462
1463         bt = 0; /* Nibble sequential */
1464
1465         switch (popts->burst_length) {
1466         case DDR_BL8:
1467                 bl = 0;
1468                 break;
1469         case DDR_OTF:
1470                 bl = 1;
1471                 break;
1472         case DDR_BC4:
1473                 bl = 2;
1474                 break;
1475         default:
1476                 printf("Error: invalid burst length of %u specified. "
1477                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1478                         popts->burst_length);
1479                 bl = 1;
1480                 break;
1481         }
1482
1483         sdmode = (0
1484                   | ((dll_on & 0x1) << 12)
1485                   | ((wr & 0x7) << 9)
1486                   | ((dll_rst & 0x1) << 8)
1487                   | ((mode & 0x1) << 7)
1488                   | (((caslat >> 1) & 0x7) << 4)
1489                   | ((bt & 0x1) << 3)
1490                   | ((caslat & 1) << 2)
1491                   | ((bl & 0x3) << 0)
1492                   );
1493
1494         ddr->ddr_sdram_mode = (0
1495                                | ((esdmode & 0xFFFF) << 16)
1496                                | ((sdmode & 0xFFFF) << 0)
1497                                );
1498
1499         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1500
1501         if (unq_mrs_en) {       /* unique mode registers are supported */
1502                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1503                         if (popts->rtt_override)
1504                                 rtt = popts->rtt_override_value;
1505                         else
1506                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1507
1508                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1509                         esdmode |= (0
1510                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1511                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1512                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1513                                 );
1514                         switch (i) {
1515                         case 1:
1516                                 ddr->ddr_sdram_mode_3 = (0
1517                                        | ((esdmode & 0xFFFF) << 16)
1518                                        | ((sdmode & 0xFFFF) << 0)
1519                                        );
1520                                 break;
1521                         case 2:
1522                                 ddr->ddr_sdram_mode_5 = (0
1523                                        | ((esdmode & 0xFFFF) << 16)
1524                                        | ((sdmode & 0xFFFF) << 0)
1525                                        );
1526                                 break;
1527                         case 3:
1528                                 ddr->ddr_sdram_mode_7 = (0
1529                                        | ((esdmode & 0xFFFF) << 16)
1530                                        | ((sdmode & 0xFFFF) << 0)
1531                                        );
1532                                 break;
1533                         }
1534                 }
1535                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1536                         ddr->ddr_sdram_mode_3);
1537                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1538                         ddr->ddr_sdram_mode_5);
1539                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1540                         ddr->ddr_sdram_mode_5);
1541         }
1542 }
1543
1544 #else /* !CONFIG_SYS_FSL_DDR3 */
1545
1546 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1547 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
1548                                const memctl_options_t *popts,
1549                                const common_timing_params_t *common_dimm,
1550                                unsigned int cas_latency,
1551                                unsigned int additive_latency,
1552                                const unsigned int unq_mrs_en)
1553 {
1554         unsigned short esdmode;         /* Extended SDRAM mode */
1555         unsigned short sdmode;          /* SDRAM mode */
1556
1557         /*
1558          * FIXME: This ought to be pre-calculated in a
1559          * technology-specific routine,
1560          * e.g. compute_DDR2_mode_register(), and then the
1561          * sdmode and esdmode passed in as part of common_dimm.
1562          */
1563
1564         /* Extended Mode Register */
1565         unsigned int mrs = 0;           /* Mode Register Set */
1566         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1567         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1568         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1569         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1570                                            0x7=OCD default state */
1571         unsigned int rtt;
1572         unsigned int al;                /* Posted CAS# additive latency (AL) */
1573         unsigned int ods = 0;           /* Output Drive Strength:
1574                                                 0 = Full strength (18ohm)
1575                                                 1 = Reduced strength (4ohm) */
1576         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1577                                                        1=Disable (Test/Debug) */
1578
1579         /* Mode Register (MR) */
1580         unsigned int mr;        /* Mode Register Definition */
1581         unsigned int pd;        /* Power-Down Mode */
1582         unsigned int wr;        /* Write Recovery */
1583         unsigned int dll_res;   /* DLL Reset */
1584         unsigned int mode;      /* Normal=0 or Test=1 */
1585         unsigned int caslat = 0;/* CAS# latency */
1586         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1587         unsigned int bt;
1588         unsigned int bl;        /* BL: Burst Length */
1589
1590         dqs_en = !popts->dqs_config;
1591         rtt = fsl_ddr_get_rtt();
1592
1593         al = additive_latency;
1594
1595         esdmode = (0
1596                 | ((mrs & 0x3) << 14)
1597                 | ((outputs & 0x1) << 12)
1598                 | ((rdqs_en & 0x1) << 11)
1599                 | ((dqs_en & 0x1) << 10)
1600                 | ((ocd & 0x7) << 7)
1601                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1602                 | ((al & 0x7) << 3)
1603                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1604                 | ((ods & 0x1) << 1)
1605                 | ((dll_en & 0x1) << 0)
1606                 );
1607
1608         mr = 0;          /* FIXME: CHECKME */
1609
1610         /*
1611          * 0 = Fast Exit (Normal)
1612          * 1 = Slow Exit (Low Power)
1613          */
1614         pd = 0;
1615
1616 #if defined(CONFIG_SYS_FSL_DDR1)
1617         wr = 0;       /* Historical */
1618 #elif defined(CONFIG_SYS_FSL_DDR2)
1619         wr = picos_to_mclk(common_dimm->twr_ps);
1620 #endif
1621         dll_res = 0;
1622         mode = 0;
1623
1624 #if defined(CONFIG_SYS_FSL_DDR1)
1625         if (1 <= cas_latency && cas_latency <= 4) {
1626                 unsigned char mode_caslat_table[4] = {
1627                         0x5,    /* 1.5 clocks */
1628                         0x2,    /* 2.0 clocks */
1629                         0x6,    /* 2.5 clocks */
1630                         0x3     /* 3.0 clocks */
1631                 };
1632                 caslat = mode_caslat_table[cas_latency - 1];
1633         } else {
1634                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1635         }
1636 #elif defined(CONFIG_SYS_FSL_DDR2)
1637         caslat = cas_latency;
1638 #endif
1639         bt = 0;
1640
1641         switch (popts->burst_length) {
1642         case DDR_BL4:
1643                 bl = 2;
1644                 break;
1645         case DDR_BL8:
1646                 bl = 3;
1647                 break;
1648         default:
1649                 printf("Error: invalid burst length of %u specified. "
1650                         " Defaulting to 4 beats.\n",
1651                         popts->burst_length);
1652                 bl = 2;
1653                 break;
1654         }
1655
1656         sdmode = (0
1657                   | ((mr & 0x3) << 14)
1658                   | ((pd & 0x1) << 12)
1659                   | ((wr & 0x7) << 9)
1660                   | ((dll_res & 0x1) << 8)
1661                   | ((mode & 0x1) << 7)
1662                   | ((caslat & 0x7) << 4)
1663                   | ((bt & 0x1) << 3)
1664                   | ((bl & 0x7) << 0)
1665                   );
1666
1667         ddr->ddr_sdram_mode = (0
1668                                | ((esdmode & 0xFFFF) << 16)
1669                                | ((sdmode & 0xFFFF) << 0)
1670                                );
1671         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1672 }
1673 #endif
1674
1675 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1676 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1677 {
1678         unsigned int init_value;        /* Initialization value */
1679
1680 #ifdef CONFIG_MEM_INIT_VALUE
1681         init_value = CONFIG_MEM_INIT_VALUE;
1682 #else
1683         init_value = 0xDEADBEEF;
1684 #endif
1685         ddr->ddr_data_init = init_value;
1686 }
1687
1688 /*
1689  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1690  * The old controller on the 8540/60 doesn't have this register.
1691  * Hope it's OK to set it (to 0) anyway.
1692  */
1693 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1694                                          const memctl_options_t *popts)
1695 {
1696         unsigned int clk_adjust;        /* Clock adjust */
1697
1698         clk_adjust = popts->clk_adjust;
1699         ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
1700         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1701 }
1702
1703 /* DDR Initialization Address (DDR_INIT_ADDR) */
1704 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1705 {
1706         unsigned int init_addr = 0;     /* Initialization address */
1707
1708         ddr->ddr_init_addr = init_addr;
1709 }
1710
1711 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1712 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1713 {
1714         unsigned int uia = 0;   /* Use initialization address */
1715         unsigned int init_ext_addr = 0; /* Initialization address */
1716
1717         ddr->ddr_init_ext_addr = (0
1718                                   | ((uia & 0x1) << 31)
1719                                   | (init_ext_addr & 0xF)
1720                                   );
1721 }
1722
1723 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1724 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1725                                 const memctl_options_t *popts)
1726 {
1727         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1728         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1729         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1730         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1731         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1732
1733 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1734         if (popts->burst_length == DDR_BL8) {
1735                 /* We set BL/2 for fixed BL8 */
1736                 rrt = 0;        /* BL/2 clocks */
1737                 wwt = 0;        /* BL/2 clocks */
1738         } else {
1739                 /* We need to set BL/2 + 2 to BC4 and OTF */
1740                 rrt = 2;        /* BL/2 + 2 clocks */
1741                 wwt = 2;        /* BL/2 + 2 clocks */
1742         }
1743 #endif
1744
1745 #ifdef CONFIG_SYS_FSL_DDR4
1746         dll_lock = 2;   /* tDLLK = 1024 clocks */
1747 #elif defined(CONFIG_SYS_FSL_DDR3)
1748         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1749 #endif
1750         ddr->timing_cfg_4 = (0
1751                              | ((rwt & 0xf) << 28)
1752                              | ((wrt & 0xf) << 24)
1753                              | ((rrt & 0xf) << 20)
1754                              | ((wwt & 0xf) << 16)
1755                              | (dll_lock & 0x3)
1756                              );
1757         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1758 }
1759
1760 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1761 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1762 {
1763         unsigned int rodt_on = 0;       /* Read to ODT on */
1764         unsigned int rodt_off = 0;      /* Read to ODT off */
1765         unsigned int wodt_on = 0;       /* Write to ODT on */
1766         unsigned int wodt_off = 0;      /* Write to ODT off */
1767
1768 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1769         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1770                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1771         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1772         if (cas_latency >= wr_lat)
1773                 rodt_on = cas_latency - wr_lat + 1;
1774         rodt_off = 4;   /*  4 clocks */
1775         wodt_on = 1;    /*  1 clocks */
1776         wodt_off = 4;   /*  4 clocks */
1777 #endif
1778
1779         ddr->timing_cfg_5 = (0
1780                              | ((rodt_on & 0x1f) << 24)
1781                              | ((rodt_off & 0x7) << 20)
1782                              | ((wodt_on & 0x1f) << 12)
1783                              | ((wodt_off & 0x7) << 8)
1784                              );
1785         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1786 }
1787
1788 #ifdef CONFIG_SYS_FSL_DDR4
1789 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1790 {
1791         unsigned int hs_caslat = 0;
1792         unsigned int hs_wrlat = 0;
1793         unsigned int hs_wrrec = 0;
1794         unsigned int hs_clkadj = 0;
1795         unsigned int hs_wrlvl_start = 0;
1796
1797         ddr->timing_cfg_6 = (0
1798                              | ((hs_caslat & 0x1f) << 24)
1799                              | ((hs_wrlat & 0x1f) << 19)
1800                              | ((hs_wrrec & 0x1f) << 12)
1801                              | ((hs_clkadj & 0x1f) << 6)
1802                              | ((hs_wrlvl_start & 0x1f) << 0)
1803                             );
1804         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1805 }
1806
1807 static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr,
1808                         const common_timing_params_t *common_dimm)
1809 {
1810         unsigned int txpr, tcksre, tcksrx;
1811         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1812
1813         txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000));
1814         tcksre = max(5U, picos_to_mclk(10000));
1815         tcksrx = max(5U, picos_to_mclk(10000));
1816         par_lat = 0;
1817         cs_to_cmd = 0;
1818
1819         if (txpr <= 200)
1820                 cke_rst = 0;
1821         else if (txpr <= 256)
1822                 cke_rst = 1;
1823         else if (txpr <= 512)
1824                 cke_rst = 2;
1825         else
1826                 cke_rst = 3;
1827
1828         if (tcksre <= 19)
1829                 cksre = tcksre - 5;
1830         else
1831                 cksre = 15;
1832
1833         if (tcksrx <= 19)
1834                 cksrx = tcksrx - 5;
1835         else
1836                 cksrx = 15;
1837
1838         ddr->timing_cfg_7 = (0
1839                              | ((cke_rst & 0x3) << 28)
1840                              | ((cksre & 0xf) << 24)
1841                              | ((cksrx & 0xf) << 20)
1842                              | ((par_lat & 0xf) << 16)
1843                              | ((cs_to_cmd & 0xf) << 4)
1844                             );
1845         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1846 }
1847
1848 static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
1849                              const memctl_options_t *popts,
1850                              const common_timing_params_t *common_dimm,
1851                              unsigned int cas_latency)
1852 {
1853         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1854         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1855         unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps);
1856         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1857                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1858
1859         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1860         if (rwt_bg < tccdl)
1861                 rwt_bg = tccdl - rwt_bg;
1862         else
1863                 rwt_bg = 0;
1864
1865         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1866         if (wrt_bg < tccdl)
1867                 wrt_bg = tccdl - wrt_bg;
1868         else
1869                 wrt_bg = 0;
1870
1871         if (popts->burst_length == DDR_BL8) {
1872                 rrt_bg = tccdl - 4;
1873                 wwt_bg = tccdl - 4;
1874         } else {
1875                 rrt_bg = tccdl - 2;
1876                 wwt_bg = tccdl - 4;
1877         }
1878
1879         acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
1880         wrtord_bg = max(4U, picos_to_mclk(7500));
1881         if (popts->otf_burst_chop_en)
1882                 wrtord_bg += 2;
1883
1884         pre_all_rec = 0;
1885
1886         ddr->timing_cfg_8 = (0
1887                              | ((rwt_bg & 0xf) << 28)
1888                              | ((wrt_bg & 0xf) << 24)
1889                              | ((rrt_bg & 0xf) << 20)
1890                              | ((wwt_bg & 0xf) << 16)
1891                              | ((acttoact_bg & 0xf) << 12)
1892                              | ((wrtord_bg & 0xf) << 8)
1893                              | ((pre_all_rec & 0x1f) << 0)
1894                             );
1895
1896         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1897 }
1898
1899 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1900 {
1901         ddr->timing_cfg_9 = 0;
1902         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1903 }
1904
1905 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1906 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1907                                const dimm_params_t *dimm_params)
1908 {
1909         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1910
1911         ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1912                         ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1913                         ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1914                         ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1915                         ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1916
1917         ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1918                         ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1919                         ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1920                         ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1921                         ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1922
1923         ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1924                         ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1925                         ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1926                         ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1927                         ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1928
1929         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
1930         ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
1931                         ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
1932                         (acc_ecc_en ? 0 :
1933                          (dimm_params->dq_mapping[9] & 0x3F) << 14) |
1934                         dimm_params->dq_mapping_ors;
1935
1936         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
1937         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
1938         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
1939         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
1940 }
1941 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
1942                                const memctl_options_t *popts)
1943 {
1944         int rd_pre;
1945
1946         rd_pre = popts->quad_rank_present ? 1 : 0;
1947
1948         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
1949
1950         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
1951 }
1952 #endif  /* CONFIG_SYS_FSL_DDR4 */
1953
1954 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
1955 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
1956 {
1957         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
1958         /* Normal Operation Full Calibration Time (tZQoper) */
1959         unsigned int zqoper = 0;
1960         /* Normal Operation Short Calibration Time (tZQCS) */
1961         unsigned int zqcs = 0;
1962 #ifdef CONFIG_SYS_FSL_DDR4
1963         unsigned int zqcs_init;
1964 #endif
1965
1966         if (zq_en) {
1967 #ifdef CONFIG_SYS_FSL_DDR4
1968                 zqinit = 10;    /* 1024 clocks */
1969                 zqoper = 9;     /* 512 clocks */
1970                 zqcs = 7;       /* 128 clocks */
1971                 zqcs_init = 5;  /* 1024 refresh sequences */
1972 #else
1973                 zqinit = 9;     /* 512 clocks */
1974                 zqoper = 8;     /* 256 clocks */
1975                 zqcs = 6;       /* 64 clocks */
1976 #endif
1977         }
1978
1979         ddr->ddr_zq_cntl = (0
1980                             | ((zq_en & 0x1) << 31)
1981                             | ((zqinit & 0xF) << 24)
1982                             | ((zqoper & 0xF) << 16)
1983                             | ((zqcs & 0xF) << 8)
1984 #ifdef CONFIG_SYS_FSL_DDR4
1985                             | ((zqcs_init & 0xF) << 0)
1986 #endif
1987                             );
1988         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
1989 }
1990
1991 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1992 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1993                                 const memctl_options_t *popts)
1994 {
1995         /*
1996          * First DQS pulse rising edge after margining mode
1997          * is programmed (tWL_MRD)
1998          */
1999         unsigned int wrlvl_mrd = 0;
2000         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2001         unsigned int wrlvl_odten = 0;
2002         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2003         unsigned int wrlvl_dqsen = 0;
2004         /* WRLVL_SMPL: Write leveling sample time */
2005         unsigned int wrlvl_smpl = 0;
2006         /* WRLVL_WLR: Write leveling repeition time */
2007         unsigned int wrlvl_wlr = 0;
2008         /* WRLVL_START: Write leveling start time */
2009         unsigned int wrlvl_start = 0;
2010
2011         /* suggest enable write leveling for DDR3 due to fly-by topology */
2012         if (wrlvl_en) {
2013                 /* tWL_MRD min = 40 nCK, we set it 64 */
2014                 wrlvl_mrd = 0x6;
2015                 /* tWL_ODTEN 128 */
2016                 wrlvl_odten = 0x7;
2017                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2018                 wrlvl_dqsen = 0x5;
2019                 /*
2020                  * Write leveling sample time at least need 6 clocks
2021                  * higher than tWLO to allow enough time for progagation
2022                  * delay and sampling the prime data bits.
2023                  */
2024                 wrlvl_smpl = 0xf;
2025                 /*
2026                  * Write leveling repetition time
2027                  * at least tWLO + 6 clocks clocks
2028                  * we set it 64
2029                  */
2030                 wrlvl_wlr = 0x6;
2031                 /*
2032                  * Write leveling start time
2033                  * The value use for the DQS_ADJUST for the first sample
2034                  * when write leveling is enabled. It probably needs to be
2035                  * overriden per platform.
2036                  */
2037                 wrlvl_start = 0x8;
2038                 /*
2039                  * Override the write leveling sample and start time
2040                  * according to specific board
2041                  */
2042                 if (popts->wrlvl_override) {
2043                         wrlvl_smpl = popts->wrlvl_sample;
2044                         wrlvl_start = popts->wrlvl_start;
2045                 }
2046         }
2047
2048         ddr->ddr_wrlvl_cntl = (0
2049                                | ((wrlvl_en & 0x1) << 31)
2050                                | ((wrlvl_mrd & 0x7) << 24)
2051                                | ((wrlvl_odten & 0x7) << 20)
2052                                | ((wrlvl_dqsen & 0x7) << 16)
2053                                | ((wrlvl_smpl & 0xf) << 12)
2054                                | ((wrlvl_wlr & 0x7) << 8)
2055                                | ((wrlvl_start & 0x1F) << 0)
2056                                );
2057         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2058         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2059         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2060         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2061         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2062
2063 }
2064
2065 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2066 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2067 {
2068         /* Self Refresh Idle Threshold */
2069         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2070 }
2071
2072 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2073 {
2074         if (popts->addr_hash) {
2075                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2076                 puts("Address hashing enabled.\n");
2077         }
2078 }
2079
2080 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2081 {
2082         ddr->ddr_cdr1 = popts->ddr_cdr1;
2083         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2084 }
2085
2086 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2087 {
2088         ddr->ddr_cdr2 = popts->ddr_cdr2;
2089         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2090 }
2091
2092 unsigned int
2093 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2094 {
2095         unsigned int res = 0;
2096
2097         /*
2098          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2099          * not set at the same time.
2100          */
2101         if (ddr->ddr_sdram_cfg & 0x10000000
2102             && ddr->ddr_sdram_cfg & 0x00008000) {
2103                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2104                                 " should not be set at the same time.\n");
2105                 res++;
2106         }
2107
2108         return res;
2109 }
2110
2111 unsigned int
2112 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
2113                                fsl_ddr_cfg_regs_t *ddr,
2114                                const common_timing_params_t *common_dimm,
2115                                const dimm_params_t *dimm_params,
2116                                unsigned int dbw_cap_adj,
2117                                unsigned int size_only)
2118 {
2119         unsigned int i;
2120         unsigned int cas_latency;
2121         unsigned int additive_latency;
2122         unsigned int sr_it;
2123         unsigned int zq_en;
2124         unsigned int wrlvl_en;
2125         unsigned int ip_rev = 0;
2126         unsigned int unq_mrs_en = 0;
2127         int cs_en = 1;
2128
2129         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2130
2131         if (common_dimm == NULL) {
2132                 printf("Error: subset DIMM params struct null pointer\n");
2133                 return 1;
2134         }
2135
2136         /*
2137          * Process overrides first.
2138          *
2139          * FIXME: somehow add dereated caslat to this
2140          */
2141         cas_latency = (popts->cas_latency_override)
2142                 ? popts->cas_latency_override_value
2143                 : common_dimm->lowest_common_spd_caslat;
2144
2145         additive_latency = (popts->additive_latency_override)
2146                 ? popts->additive_latency_override_value
2147                 : common_dimm->additive_latency;
2148
2149         sr_it = (popts->auto_self_refresh_en)
2150                 ? popts->sr_it
2151                 : 0;
2152         /* ZQ calibration */
2153         zq_en = (popts->zq_en) ? 1 : 0;
2154         /* write leveling */
2155         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2156
2157         /* Chip Select Memory Bounds (CSn_BNDS) */
2158         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2159                 unsigned long long ea, sa;
2160                 unsigned int cs_per_dimm
2161                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2162                 unsigned int dimm_number
2163                         = i / cs_per_dimm;
2164                 unsigned long long rank_density
2165                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2166
2167                 if (dimm_params[dimm_number].n_ranks == 0) {
2168                         debug("Skipping setup of CS%u "
2169                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2170                         continue;
2171                 }
2172                 if (popts->memctl_interleaving) {
2173                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2174                         case FSL_DDR_CS0_CS1_CS2_CS3:
2175                                 break;
2176                         case FSL_DDR_CS0_CS1:
2177                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2178                                 if (i > 1)
2179                                         cs_en = 0;
2180                                 break;
2181                         case FSL_DDR_CS2_CS3:
2182                         default:
2183                                 if (i > 0)
2184                                         cs_en = 0;
2185                                 break;
2186                         }
2187                         sa = common_dimm->base_address;
2188                         ea = sa + common_dimm->total_mem - 1;
2189                 } else if (!popts->memctl_interleaving) {
2190                         /*
2191                          * If memory interleaving between controllers is NOT
2192                          * enabled, the starting address for each memory
2193                          * controller is distinct.  However, because rank
2194                          * interleaving is enabled, the starting and ending
2195                          * addresses of the total memory on that memory
2196                          * controller needs to be programmed into its
2197                          * respective CS0_BNDS.
2198                          */
2199                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2200                         case FSL_DDR_CS0_CS1_CS2_CS3:
2201                                 sa = common_dimm->base_address;
2202                                 ea = sa + common_dimm->total_mem - 1;
2203                                 break;
2204                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2205                                 if ((i >= 2) && (dimm_number == 0)) {
2206                                         sa = dimm_params[dimm_number].base_address +
2207                                               2 * rank_density;
2208                                         ea = sa + 2 * rank_density - 1;
2209                                 } else {
2210                                         sa = dimm_params[dimm_number].base_address;
2211                                         ea = sa + 2 * rank_density - 1;
2212                                 }
2213                                 break;
2214                         case FSL_DDR_CS0_CS1:
2215                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2216                                         sa = dimm_params[dimm_number].base_address;
2217                                         ea = sa + rank_density - 1;
2218                                         if (i != 1)
2219                                                 sa += (i % cs_per_dimm) * rank_density;
2220                                         ea += (i % cs_per_dimm) * rank_density;
2221                                 } else {
2222                                         sa = 0;
2223                                         ea = 0;
2224                                 }
2225                                 if (i == 0)
2226                                         ea += rank_density;
2227                                 break;
2228                         case FSL_DDR_CS2_CS3:
2229                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2230                                         sa = dimm_params[dimm_number].base_address;
2231                                         ea = sa + rank_density - 1;
2232                                         if (i != 3)
2233                                                 sa += (i % cs_per_dimm) * rank_density;
2234                                         ea += (i % cs_per_dimm) * rank_density;
2235                                 } else {
2236                                         sa = 0;
2237                                         ea = 0;
2238                                 }
2239                                 if (i == 2)
2240                                         ea += (rank_density >> dbw_cap_adj);
2241                                 break;
2242                         default:  /* No bank(chip-select) interleaving */
2243                                 sa = dimm_params[dimm_number].base_address;
2244                                 ea = sa + rank_density - 1;
2245                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2246                                         sa += (i % cs_per_dimm) * rank_density;
2247                                         ea += (i % cs_per_dimm) * rank_density;
2248                                 } else {
2249                                         sa = 0;
2250                                         ea = 0;
2251                                 }
2252                                 break;
2253                         }
2254                 }
2255
2256                 sa >>= 24;
2257                 ea >>= 24;
2258
2259                 if (cs_en) {
2260                         ddr->cs[i].bnds = (0
2261                                 | ((sa & 0xffff) << 16) /* starting address */
2262                                 | ((ea & 0xffff) << 0)  /* ending address */
2263                                 );
2264                 } else {
2265                         /* setting bnds to 0xffffffff for inactive CS */
2266                         ddr->cs[i].bnds = 0xffffffff;
2267                 }
2268
2269                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2270                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2271                 set_csn_config_2(i, ddr);
2272         }
2273
2274         /*
2275          * In the case we only need to compute the ddr sdram size, we only need
2276          * to set csn registers, so return from here.
2277          */
2278         if (size_only)
2279                 return 0;
2280
2281         set_ddr_eor(ddr, popts);
2282
2283 #if !defined(CONFIG_SYS_FSL_DDR1)
2284         set_timing_cfg_0(ddr, popts, dimm_params);
2285 #endif
2286
2287         set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
2288                          additive_latency);
2289         set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
2290         set_timing_cfg_2(ddr, popts, common_dimm,
2291                                 cas_latency, additive_latency);
2292
2293         set_ddr_cdr1(ddr, popts);
2294         set_ddr_cdr2(ddr, popts);
2295         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2296         ip_rev = fsl_ddr_get_version();
2297         if (ip_rev > 0x40400)
2298                 unq_mrs_en = 1;
2299
2300         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2301                 ddr->debug[18] = popts->cswl_override;
2302
2303         set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
2304         set_ddr_sdram_mode(ddr, popts, common_dimm,
2305                                 cas_latency, additive_latency, unq_mrs_en);
2306         set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
2307 #ifdef CONFIG_SYS_FSL_DDR4
2308         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2309         set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en);
2310 #endif
2311         set_ddr_sdram_interval(ddr, popts, common_dimm);
2312         set_ddr_data_init(ddr);
2313         set_ddr_sdram_clk_cntl(ddr, popts);
2314         set_ddr_init_addr(ddr);
2315         set_ddr_init_ext_addr(ddr);
2316         set_timing_cfg_4(ddr, popts);
2317         set_timing_cfg_5(ddr, cas_latency);
2318 #ifdef CONFIG_SYS_FSL_DDR4
2319         set_ddr_sdram_cfg_3(ddr, popts);
2320         set_timing_cfg_6(ddr);
2321         set_timing_cfg_7(ddr, common_dimm);
2322         set_timing_cfg_8(ddr, popts, common_dimm, cas_latency);
2323         set_timing_cfg_9(ddr);
2324         set_ddr_dq_mapping(ddr, dimm_params);
2325 #endif
2326
2327         set_ddr_zq_cntl(ddr, zq_en);
2328         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2329
2330         set_ddr_sr_cntr(ddr, sr_it);
2331
2332         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2333
2334 #ifdef CONFIG_SYS_FSL_DDR_EMU
2335         /* disble DDR training for emulator */
2336         ddr->debug[2] = 0x00000400;
2337         ddr->debug[4] = 0xff800000;
2338 #endif
2339 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2340         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2341                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2342 #endif
2343
2344         return check_fsl_memctl_config_regs(ddr);
2345 }