4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
11 Select Freescale Multi Mode DDR controller (MMDC).
13 if SYS_FSL_DDR || SYS_FSL_MMDC
18 Access DDR registers in big-endian
23 Access DDR registers in little-endian
28 config FSL_DDR_INTERACTIVE
31 config FSL_DDR_SYNC_REFRESH
34 config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
37 menu "Freescale DDR controllers"
38 depends on SYS_FSL_DDR
40 config SYS_NUM_DDR_CTLRS
41 int "Maximum DDR controllers"
42 default 3 if ARCH_LS2080A || \
44 default 2 if ARCH_B4860 || \
52 config CHIP_SELECTS_PER_CTRL
53 int "Number of chip selects per controller"
56 config SYS_FSL_DDR_VER
58 default 50 if SYS_FSL_DDR_VER_50
59 default 47 if SYS_FSL_DDR_VER_47
60 default 46 if SYS_FSL_DDR_VER_46
61 default 44 if SYS_FSL_DDR_VER_44
63 config SYS_FSL_DDR_VER_50
66 config SYS_FSL_DDR_VER_47
69 config SYS_FSL_DDR_VER_46
72 config SYS_FSL_DDR_VER_44
75 config SYS_FSL_DDRC_GEN1
78 Enable Freescale DDR controller.
80 config SYS_FSL_DDRC_GEN2
84 Enable Freescale DDR2 controller.
86 config SYS_FSL_DDRC_GEN3
90 Enable Freescale DDR3 controller for PowerPC SoCs.
92 config SYS_FSL_DDRC_ARM_GEN3
96 Enable Freescale DDR3 controller for ARM SoCs.
98 config SYS_FSL_DDRC_GEN4
101 Enable Freescale DDR4 controller.
103 config SYS_FSL_HAS_DDR4
106 config SYS_FSL_HAS_DDR3
109 config SYS_FSL_HAS_DDR2
112 config SYS_FSL_HAS_DDR1
116 prompt "DDR technology"
117 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
118 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
119 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
120 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
123 bool "Freescale DDR4 controller"
124 depends on SYS_FSL_HAS_DDR4
126 select SYS_FSL_DDRC_GEN4
129 bool "Freescale DDR3 controller"
130 depends on SYS_FSL_HAS_DDR3
132 select SYS_FSL_DDRC_GEN3 if PPC
133 select SYS_FSL_DDRC_ARM_GEN3 if ARM
136 bool "Freescale DDR2 controller"
137 depends on SYS_FSL_HAS_DDR2
139 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
142 bool "Freescale DDR1 controller"
143 depends on SYS_FSL_HAS_DDR1
145 select SYS_FSL_DDRC_GEN1
152 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
155 bool "ECC DDR memory support"
158 bool "Access the ECC features of the memory controller"
159 depends on DDR_ECC && MPC83xx
162 config ECC_INIT_VIA_DDRCONTROLLER
163 bool "DDR Memory controller initializes memory."
165 Use the DDR controller to auto initialize memory. If not enabled,
166 the DMA controller is responsible for doing this.
170 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
171 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
173 config SYS_BR0_PRELIM_BOOL
176 config SYS_BR0_PRELIM
177 hex "Preliminary value for BR0"
178 depends on SYS_BR0_PRELIM_BOOL
180 config SYS_OR0_PRELIM
181 hex "Preliminary value for OR0"
182 depends on SYS_BR0_PRELIM_BOOL
184 config SYS_BR1_PRELIM_BOOL
187 config SYS_BR1_PRELIM
188 hex "Preliminary value for BR1"
189 depends on SYS_BR1_PRELIM_BOOL
191 config SYS_OR1_PRELIM
192 hex "Preliminary value for OR1"
193 depends on SYS_BR1_PRELIM_BOOL
195 config SYS_BR2_PRELIM_BOOL
198 config SYS_BR2_PRELIM
199 hex "Preliminary value for BR2"
200 depends on SYS_BR2_PRELIM_BOOL
202 config SYS_OR2_PRELIM
203 hex "Preliminary value for OR2"
204 depends on SYS_BR2_PRELIM_BOOL
206 config SYS_BR3_PRELIM_BOOL
209 config SYS_BR3_PRELIM
210 hex "Preliminary value for BR3"
211 depends on SYS_BR3_PRELIM_BOOL
213 config SYS_OR3_PRELIM
214 hex "Preliminary value for OR3"
215 depends on SYS_BR3_PRELIM_BOOL
217 config SYS_BR4_PRELIM_BOOL
220 config SYS_BR4_PRELIM
221 hex "Preliminary value for BR4"
222 depends on SYS_BR4_PRELIM_BOOL
224 config SYS_OR4_PRELIM
225 hex "Preliminary value for OR4"
226 depends on SYS_BR4_PRELIM_BOOL
228 config SYS_BR5_PRELIM_BOOL
231 config SYS_BR5_PRELIM
232 hex "Preliminary value for BR5"
233 depends on SYS_BR5_PRELIM_BOOL
235 config SYS_OR5_PRELIM
236 hex "Preliminary value for OR5"
237 depends on SYS_BR5_PRELIM_BOOL
239 config SYS_BR6_PRELIM_BOOL
242 config SYS_BR6_PRELIM
243 hex "Preliminary value for BR6"
244 depends on SYS_BR6_PRELIM_BOOL
246 config SYS_OR6_PRELIM
247 hex "Preliminary value for OR6"
248 depends on SYS_BR6_PRELIM_BOOL
250 config SYS_BR7_PRELIM_BOOL
253 config SYS_BR7_PRELIM
254 hex "Preliminary value for BR7"
255 depends on SYS_BR7_PRELIM_BOOL
257 config SYS_OR7_PRELIM
258 hex "Preliminary value for OR7"
259 depends on SYS_BR7_PRELIM_BOOL
262 config SYS_FSL_ERRATUM_A008378
265 config SYS_FSL_ERRATUM_A008109
268 config SYS_FSL_ERRATUM_A008511
271 config SYS_FSL_ERRATUM_A009663
274 config SYS_FSL_ERRATUM_A009801
277 config SYS_FSL_ERRATUM_A009803
280 config SYS_FSL_ERRATUM_A009942
283 config SYS_FSL_ERRATUM_A010165
286 config SYS_FSL_ERRATUM_NMG_DDR120
289 config SYS_FSL_ERRATUM_DDR_115
292 config SYS_FSL_ERRATUM_DDR111_DDR134
295 config SYS_FSL_ERRATUM_DDR_A003
298 config SYS_FSL_ERRATUM_DDR_A003474