4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
11 Select Freescale Multi Mode DDR controller (MMDC).
13 config SYS_FSL_DDR_EMU
16 Specify emulator support for DDR. Some DDR features such as deskew
17 training are not available.
19 if SYS_FSL_DDR || SYS_FSL_MMDC
24 Access DDR registers in big-endian
29 Access DDR registers in little-endian
34 config FSL_DDR_INTERACTIVE
37 config FSL_DDR_SYNC_REFRESH
40 config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
43 menu "Freescale DDR controllers"
44 depends on SYS_FSL_DDR
46 config SYS_NUM_DDR_CTLRS
47 int "Maximum DDR controllers"
48 default 3 if ARCH_LS2080A || \
50 default 2 if ARCH_B4860 || \
58 config CHIP_SELECTS_PER_CTRL
59 int "Number of chip selects per controller"
62 config DIMM_SLOTS_PER_CTLR
63 int "Number of DIMM slots per controller"
66 config SYS_FSL_DDR_VER
68 default 50 if SYS_FSL_DDR_VER_50
69 default 47 if SYS_FSL_DDR_VER_47
70 default 46 if SYS_FSL_DDR_VER_46
71 default 44 if SYS_FSL_DDR_VER_44
73 config SYS_FSL_DDR_VER_50
76 config SYS_FSL_DDR_VER_47
79 config SYS_FSL_DDR_VER_46
82 config SYS_FSL_DDR_VER_44
85 config SYS_FSL_DDRC_GEN1
88 Enable Freescale DDR controller.
90 config SYS_FSL_DDRC_GEN2
94 Enable Freescale DDR2 controller.
96 config SYS_FSL_DDRC_GEN3
100 Enable Freescale DDR3 controller for PowerPC SoCs.
102 config SYS_FSL_DDRC_ARM_GEN3
106 Enable Freescale DDR3 controller for ARM SoCs.
108 config SYS_FSL_DDRC_GEN4
111 Enable Freescale DDR4 controller.
113 config SYS_FSL_HAS_DDR4
116 config SYS_FSL_HAS_DDR3
119 config SYS_FSL_HAS_DDR2
122 config SYS_FSL_HAS_DDR1
126 prompt "DDR technology"
127 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
128 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
129 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
130 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
133 bool "Freescale DDR4 controller"
134 depends on SYS_FSL_HAS_DDR4
136 select SYS_FSL_DDRC_GEN4
139 bool "Freescale DDR3 controller"
140 depends on SYS_FSL_HAS_DDR3
142 select SYS_FSL_DDRC_GEN3 if PPC
143 select SYS_FSL_DDRC_ARM_GEN3 if ARM
146 bool "Freescale DDR2 controller"
147 depends on SYS_FSL_HAS_DDR2
149 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
152 bool "Freescale DDR1 controller"
153 depends on SYS_FSL_HAS_DDR1
155 select SYS_FSL_DDRC_GEN1
162 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
165 bool "ECC DDR memory support"
168 bool "Access the ECC features of the memory controller"
169 depends on DDR_ECC && MPC83xx
172 config ECC_INIT_VIA_DDRCONTROLLER
173 bool "DDR Memory controller initializes memory."
175 Use the DDR controller to auto initialize memory. If not enabled,
176 the DMA controller is responsible for doing this.
178 config SYS_DDR_RAW_TIMING
179 bool "Get DDR timing information from something other than SPD"
181 This is common with soldered DDR chips onboard without SPD. DDR raw
182 timing parameters are extracted from datasheet and hard-coded into
183 header files or board specific files.
187 menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
188 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
190 config SYS_BR0_PRELIM_BOOL
193 config SYS_BR0_PRELIM
194 hex "Preliminary value for BR0"
195 depends on SYS_BR0_PRELIM_BOOL
197 config SYS_OR0_PRELIM
198 hex "Preliminary value for OR0"
199 depends on SYS_BR0_PRELIM_BOOL
201 config SYS_BR1_PRELIM_BOOL
204 config SYS_BR1_PRELIM
205 hex "Preliminary value for BR1"
206 depends on SYS_BR1_PRELIM_BOOL
208 config SYS_OR1_PRELIM
209 hex "Preliminary value for OR1"
210 depends on SYS_BR1_PRELIM_BOOL
212 config SYS_BR2_PRELIM_BOOL
215 config SYS_BR2_PRELIM
216 hex "Preliminary value for BR2"
217 depends on SYS_BR2_PRELIM_BOOL
219 config SYS_OR2_PRELIM
220 hex "Preliminary value for OR2"
221 depends on SYS_BR2_PRELIM_BOOL
223 config SYS_BR3_PRELIM_BOOL
226 config SYS_BR3_PRELIM
227 hex "Preliminary value for BR3"
228 depends on SYS_BR3_PRELIM_BOOL
230 config SYS_OR3_PRELIM
231 hex "Preliminary value for OR3"
232 depends on SYS_BR3_PRELIM_BOOL
234 config SYS_BR4_PRELIM_BOOL
237 config SYS_BR4_PRELIM
238 hex "Preliminary value for BR4"
239 depends on SYS_BR4_PRELIM_BOOL
241 config SYS_OR4_PRELIM
242 hex "Preliminary value for OR4"
243 depends on SYS_BR4_PRELIM_BOOL
245 config SYS_BR5_PRELIM_BOOL
248 config SYS_BR5_PRELIM
249 hex "Preliminary value for BR5"
250 depends on SYS_BR5_PRELIM_BOOL
252 config SYS_OR5_PRELIM
253 hex "Preliminary value for OR5"
254 depends on SYS_BR5_PRELIM_BOOL
256 config SYS_BR6_PRELIM_BOOL
259 config SYS_BR6_PRELIM
260 hex "Preliminary value for BR6"
261 depends on SYS_BR6_PRELIM_BOOL
263 config SYS_OR6_PRELIM
264 hex "Preliminary value for OR6"
265 depends on SYS_BR6_PRELIM_BOOL
267 config SYS_BR7_PRELIM_BOOL
270 config SYS_BR7_PRELIM
271 hex "Preliminary value for BR7"
272 depends on SYS_BR7_PRELIM_BOOL
274 config SYS_OR7_PRELIM
275 hex "Preliminary value for OR7"
276 depends on SYS_BR7_PRELIM_BOOL
279 if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
280 TARGET_P1020RDB_PD || TARGET_P2020RDB
282 config COMMON_INIT_DDR
283 bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
285 config SPL_COMMON_INIT_DDR
286 bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
288 config TPL_COMMON_INIT_DDR
289 bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
293 config SYS_FSL_ERRATUM_A008378
296 config SYS_FSL_ERRATUM_A008109
299 config SYS_FSL_ERRATUM_A008511
302 config SYS_FSL_ERRATUM_A009663
305 config SYS_FSL_ERRATUM_A009801
308 config SYS_FSL_ERRATUM_A009803
311 config SYS_FSL_ERRATUM_A009942
314 config SYS_FSL_ERRATUM_A010165
317 config SYS_FSL_ERRATUM_NMG_DDR120
320 config SYS_FSL_ERRATUM_DDR_115
323 config SYS_FSL_ERRATUM_DDR111_DDR134
326 config SYS_FSL_ERRATUM_DDR_A003
329 config SYS_FSL_ERRATUM_DDR_A003474