2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1174 * @rank_bgn: Rank number
1175 * @group: Read/Write group
1176 * @num_tries: Number of retries of the test
1177 * @all_correct: All bits must be correct in the mask
1178 * @bit_chk: Resulting bit mask after the test
1179 * @all_groups: Test all R/W groups
1180 * @all_ranks: Test all ranks
1182 * Try a read and see if it returns correct data back. Test has dummy reads
1183 * inserted into the mix used to align DQS enable. Test has more thorough
1184 * checks than the regular read test.
1187 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1188 const u32 num_tries, const u32 all_correct,
1190 const u32 all_groups, const u32 all_ranks)
1192 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1193 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1194 const u32 quick_read_mode =
1195 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1196 ENABLE_SUPER_QUICK_CALIBRATION);
1197 u32 correct_mask_vg = param->read_correct_mask_vg;
1204 *bit_chk = param->read_correct_mask;
1206 for (r = rank_bgn; r < rank_end; r++) {
1207 if (param->skip_ranks[r])
1208 /* request to skip the rank */
1212 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1214 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1216 writel(RW_MGR_READ_B2B_WAIT1,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1219 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1220 writel(RW_MGR_READ_B2B_WAIT2,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1223 if (quick_read_mode)
1224 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1225 /* need at least two (1+1) reads to capture failures */
1226 else if (all_groups)
1227 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1229 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1231 writel(RW_MGR_READ_B2B,
1232 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1234 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1235 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1236 &sdr_rw_load_mgr_regs->load_cntr3);
1238 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1240 writel(RW_MGR_READ_B2B,
1241 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1244 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1246 /* Reset the FIFOs to get pointers to known state. */
1247 writel(0, &phy_mgr_cmd->fifo_reset);
1248 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1249 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1252 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1253 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1255 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1256 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1259 writel(RW_MGR_READ_B2B, addr +
1260 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1263 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1264 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1265 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1266 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1269 *bit_chk &= tmp_bit_chk;
1272 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1273 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1275 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1278 ret = (*bit_chk == param->read_correct_mask);
1279 debug_cond(DLEVEL == 2,
1280 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1281 __func__, __LINE__, group, all_groups, *bit_chk,
1282 param->read_correct_mask, ret);
1284 ret = (*bit_chk != 0x00);
1285 debug_cond(DLEVEL == 2,
1286 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1287 __func__, __LINE__, group, all_groups, *bit_chk,
1295 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1296 * @grp: Read/Write group
1297 * @num_tries: Number of retries of the test
1298 * @all_correct: All bits must be correct in the mask
1299 * @all_groups: Test all R/W groups
1301 * Perform a READ test across all memory ranks.
1304 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1305 const u32 all_correct,
1306 const u32 all_groups)
1309 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1310 &bit_chk, all_groups, 1);
1314 * rw_mgr_incr_vfifo() - Increase VFIFO value
1315 * @grp: Read/Write group
1317 * Increase VFIFO value.
1319 static void rw_mgr_incr_vfifo(const u32 grp)
1321 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1325 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1326 * @grp: Read/Write group
1328 * Decrease VFIFO value.
1330 static void rw_mgr_decr_vfifo(const u32 grp)
1334 for (i = 0; i < VFIFO_SIZE - 1; i++)
1335 rw_mgr_incr_vfifo(grp);
1339 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1340 * @grp: Read/Write group
1342 * Push VFIFO until a failing read happens.
1344 static int find_vfifo_failing_read(const u32 grp)
1346 u32 v, ret, fail_cnt = 0;
1348 for (v = 0; v < VFIFO_SIZE; v++) {
1349 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1350 __func__, __LINE__, v);
1351 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1360 /* Fiddle with FIFO. */
1361 rw_mgr_incr_vfifo(grp);
1364 /* No failing read found! Something must have gone wrong. */
1365 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1370 * sdr_find_phase_delay() - Find DQS enable phase or delay
1371 * @working: If 1, look for working phase/delay, if 0, look for non-working
1372 * @delay: If 1, look for delay, if 0, look for phase
1373 * @grp: Read/Write group
1374 * @work: Working window position
1375 * @work_inc: Working window increment
1376 * @pd: DQS Phase/Delay Iterator
1378 * Find working or non-working DQS enable phase setting.
1380 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1381 u32 *work, const u32 work_inc, u32 *pd)
1383 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1386 for (; *pd <= max; (*pd)++) {
1388 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1390 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1392 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1407 * sdr_find_phase() - Find DQS enable phase
1408 * @working: If 1, look for working phase, if 0, look for non-working phase
1409 * @grp: Read/Write group
1410 * @work: Working window position
1412 * @p: DQS Phase Iterator
1414 * Find working or non-working DQS enable phase setting.
1416 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1419 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1422 for (; *i < end; (*i)++) {
1426 ret = sdr_find_phase_delay(working, 0, grp, work,
1427 IO_DELAY_PER_OPA_TAP, p);
1431 if (*p > IO_DQS_EN_PHASE_MAX) {
1432 /* Fiddle with FIFO. */
1433 rw_mgr_incr_vfifo(grp);
1443 * sdr_working_phase() - Find working DQS enable phase
1444 * @grp: Read/Write group
1445 * @work_bgn: Working window start position
1446 * @d: dtaps output value
1447 * @p: DQS Phase Iterator
1450 * Find working DQS enable phase setting.
1452 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1455 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1456 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1461 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1463 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1464 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1467 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1470 /* Cannot find working solution */
1471 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1472 __func__, __LINE__);
1477 * sdr_backup_phase() - Find DQS enable backup phase
1478 * @grp: Read/Write group
1479 * @work_bgn: Working window start position
1480 * @p: DQS Phase Iterator
1482 * Find DQS enable backup phase setting.
1484 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1489 /* Special case code for backing up a phase */
1491 *p = IO_DQS_EN_PHASE_MAX;
1492 rw_mgr_decr_vfifo(grp);
1496 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1497 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1499 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1500 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1502 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1505 *work_bgn = tmp_delay;
1509 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1512 /* Restore VFIFO to old state before we decremented it (if needed). */
1514 if (*p > IO_DQS_EN_PHASE_MAX) {
1516 rw_mgr_incr_vfifo(grp);
1519 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1523 * sdr_nonworking_phase() - Find non-working DQS enable phase
1524 * @grp: Read/Write group
1525 * @work_end: Working window end position
1526 * @p: DQS Phase Iterator
1529 * Find non-working DQS enable phase setting.
1531 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1536 *work_end += IO_DELAY_PER_OPA_TAP;
1537 if (*p > IO_DQS_EN_PHASE_MAX) {
1538 /* Fiddle with FIFO. */
1540 rw_mgr_incr_vfifo(grp);
1543 ret = sdr_find_phase(0, grp, work_end, i, p);
1545 /* Cannot see edge of failing read. */
1546 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1547 __func__, __LINE__);
1554 * sdr_find_window_center() - Find center of the working DQS window.
1555 * @grp: Read/Write group
1556 * @work_bgn: First working settings
1557 * @work_end: Last working settings
1559 * Find center of the working DQS enable window.
1561 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1568 work_mid = (work_bgn + work_end) / 2;
1570 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1571 work_bgn, work_end, work_mid);
1572 /* Get the middle delay to be less than a VFIFO delay */
1573 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1575 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1576 work_mid %= tmp_delay;
1577 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1579 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1580 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1581 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1582 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1584 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1586 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1587 if (d > IO_DQS_EN_DELAY_MAX)
1588 d = IO_DQS_EN_DELAY_MAX;
1589 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1591 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1593 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1594 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1597 * push vfifo until we can successfully calibrate. We can do this
1598 * because the largest possible margin in 1 VFIFO cycle.
1600 for (i = 0; i < VFIFO_SIZE; i++) {
1601 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1602 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1605 debug_cond(DLEVEL == 2,
1606 "%s:%d center: found: ptap=%u dtap=%u\n",
1607 __func__, __LINE__, p, d);
1611 /* Fiddle with FIFO. */
1612 rw_mgr_incr_vfifo(grp);
1615 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1616 __func__, __LINE__);
1621 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1622 * @grp: Read/Write Group
1624 * Find a good DQS enable to use.
1626 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1630 u32 work_bgn, work_end;
1631 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1634 debug("%s:%d %u\n", __func__, __LINE__, grp);
1636 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1638 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1639 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1641 /* Step 0: Determine number of delay taps for each phase tap. */
1642 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1644 /* Step 1: First push vfifo until we get a failing read. */
1645 find_vfifo_failing_read(grp);
1647 /* Step 2: Find first working phase, increment in ptaps. */
1649 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1653 work_end = work_bgn;
1656 * If d is 0 then the working window covers a phase tap and we can
1657 * follow the old procedure. Otherwise, we've found the beginning
1658 * and we need to increment the dtaps until we find the end.
1662 * Step 3a: If we have room, back off by one and
1663 * increment in dtaps.
1665 sdr_backup_phase(grp, &work_bgn, &p);
1668 * Step 4a: go forward from working phase to non working
1669 * phase, increment in ptaps.
1671 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1675 /* Step 5a: Back off one from last, increment in dtaps. */
1677 /* Special case code for backing up a phase */
1679 p = IO_DQS_EN_PHASE_MAX;
1680 rw_mgr_decr_vfifo(grp);
1685 work_end -= IO_DELAY_PER_OPA_TAP;
1686 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1690 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1691 __func__, __LINE__, p);
1694 /* The dtap increment to find the failing edge is done here. */
1695 sdr_find_phase_delay(0, 1, grp, &work_end,
1696 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1698 /* Go back to working dtap */
1700 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1702 debug_cond(DLEVEL == 2,
1703 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1704 __func__, __LINE__, p, d - 1, work_end);
1706 if (work_end < work_bgn) {
1708 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1709 __func__, __LINE__);
1713 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1714 __func__, __LINE__, work_bgn, work_end);
1717 * We need to calculate the number of dtaps that equal a ptap.
1718 * To do that we'll back up a ptap and re-find the edge of the
1719 * window using dtaps
1721 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1722 __func__, __LINE__);
1724 /* Special case code for backing up a phase */
1726 p = IO_DQS_EN_PHASE_MAX;
1727 rw_mgr_decr_vfifo(grp);
1728 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1729 __func__, __LINE__, p);
1732 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1733 __func__, __LINE__, p);
1736 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1739 * Increase dtap until we first see a passing read (in case the
1740 * window is smaller than a ptap), and then a failing read to
1741 * mark the edge of the window again.
1744 /* Find a passing read. */
1745 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1746 __func__, __LINE__);
1748 initial_failing_dtap = d;
1750 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1751 if (found_passing_read) {
1752 /* Find a failing read. */
1753 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1754 __func__, __LINE__);
1756 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1759 debug_cond(DLEVEL == 1,
1760 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1761 __func__, __LINE__);
1765 * The dynamically calculated dtaps_per_ptap is only valid if we
1766 * found a passing/failing read. If we didn't, it means d hit the max
1767 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1768 * statically calculated value.
1770 if (found_passing_read && found_failing_read)
1771 dtaps_per_ptap = d - initial_failing_dtap;
1773 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1774 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1775 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1777 /* Step 6: Find the centre of the window. */
1778 ret = sdr_find_window_center(grp, work_bgn, work_end);
1784 * search_stop_check() - Check if the detected edge is valid
1785 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1787 * @rank_bgn: Rank number
1788 * @write_group: Write Group
1789 * @read_group: Read Group
1790 * @bit_chk: Resulting bit mask after the test
1791 * @sticky_bit_chk: Resulting sticky bit mask after the test
1792 * @use_read_test: Perform read test
1794 * Test if the found edge is valid.
1796 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1797 const u32 write_group, const u32 read_group,
1798 u32 *bit_chk, u32 *sticky_bit_chk,
1799 const u32 use_read_test)
1801 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
1802 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
1803 const u32 correct_mask = write ? param->write_correct_mask :
1804 param->read_correct_mask;
1805 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1806 RW_MGR_MEM_DQ_PER_READ_DQS;
1809 * Stop searching when the read test doesn't pass AND when
1810 * we've seen a passing read on every bit.
1812 if (write) { /* WRITE-ONLY */
1813 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1816 } else if (use_read_test) { /* READ-ONLY */
1817 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
1819 PASS_ONE_BIT, bit_chk,
1821 } else { /* READ-ONLY */
1822 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
1823 PASS_ONE_BIT, bit_chk, 0);
1824 *bit_chk = *bit_chk >> (per_dqs *
1825 (read_group - (write_group * ratio)));
1826 ret = (*bit_chk == 0);
1828 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
1829 ret = ret && (*sticky_bit_chk == correct_mask);
1830 debug_cond(DLEVEL == 2,
1831 "%s:%d center(left): dtap=%u => %u == %u && %u",
1832 __func__, __LINE__, d,
1833 *sticky_bit_chk, correct_mask, ret);
1838 * search_left_edge() - Find left edge of DQ/DQS working phase
1839 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1840 * @rank_bgn: Rank number
1841 * @write_group: Write Group
1842 * @read_group: Read Group
1843 * @test_bgn: Rank number to begin the test
1844 * @sticky_bit_chk: Resulting sticky bit mask after the test
1845 * @left_edge: Left edge of the DQ/DQS phase
1846 * @right_edge: Right edge of the DQ/DQS phase
1847 * @use_read_test: Perform read test
1849 * Find left edge of DQ/DQS working phase.
1851 static void search_left_edge(const int write, const int rank_bgn,
1852 const u32 write_group, const u32 read_group, const u32 test_bgn,
1853 u32 *sticky_bit_chk,
1854 int *left_edge, int *right_edge, const u32 use_read_test)
1856 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1857 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1858 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1859 RW_MGR_MEM_DQ_PER_READ_DQS;
1863 for (d = 0; d <= dqs_max; d++) {
1865 scc_mgr_apply_group_dq_out1_delay(d);
1867 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
1869 writel(0, &sdr_scc_mgr->update);
1871 stop = search_stop_check(write, d, rank_bgn, write_group,
1872 read_group, &bit_chk, sticky_bit_chk,
1878 for (i = 0; i < per_dqs; i++) {
1881 * Remember a passing test as
1887 * If a left edge has not been seen
1888 * yet, then a future passing test
1889 * will mark this edge as the right
1892 if (left_edge[i] == delay_max + 1)
1893 right_edge[i] = -(d + 1);
1899 /* Reset DQ delay chains to 0 */
1901 scc_mgr_apply_group_dq_out1_delay(0);
1903 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1905 *sticky_bit_chk = 0;
1906 for (i = per_dqs - 1; i >= 0; i--) {
1907 debug_cond(DLEVEL == 2,
1908 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
1909 __func__, __LINE__, i, left_edge[i],
1913 * Check for cases where we haven't found the left edge,
1914 * which makes our assignment of the the right edge invalid.
1915 * Reset it to the illegal value.
1917 if ((left_edge[i] == delay_max + 1) &&
1918 (right_edge[i] != delay_max + 1)) {
1919 right_edge[i] = delay_max + 1;
1920 debug_cond(DLEVEL == 2,
1921 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
1922 __func__, __LINE__, i, right_edge[i]);
1927 * READ: except for bits where we have seen both
1928 * the left and right edge.
1929 * WRITE: except for bits where we have seen the
1932 *sticky_bit_chk <<= 1;
1934 if (left_edge[i] != delay_max + 1)
1935 *sticky_bit_chk |= 1;
1937 if ((left_edge[i] != delay_max + 1) &&
1938 (right_edge[i] != delay_max + 1))
1939 *sticky_bit_chk |= 1;
1947 * search_right_edge() - Find right edge of DQ/DQS working phase
1948 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1949 * @rank_bgn: Rank number
1950 * @write_group: Write Group
1951 * @read_group: Read Group
1952 * @start_dqs: DQS start phase
1953 * @start_dqs_en: DQS enable start phase
1954 * @sticky_bit_chk: Resulting sticky bit mask after the test
1955 * @left_edge: Left edge of the DQ/DQS phase
1956 * @right_edge: Right edge of the DQ/DQS phase
1957 * @use_read_test: Perform read test
1959 * Find right edge of DQ/DQS working phase.
1961 static int search_right_edge(const int write, const int rank_bgn,
1962 const u32 write_group, const u32 read_group,
1963 const int start_dqs, const int start_dqs_en,
1964 u32 *sticky_bit_chk,
1965 int *left_edge, int *right_edge, const u32 use_read_test)
1967 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
1968 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
1969 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
1970 RW_MGR_MEM_DQ_PER_READ_DQS;
1974 for (d = 0; d <= dqs_max - start_dqs; d++) {
1975 if (write) { /* WRITE-ONLY */
1976 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
1978 } else { /* READ-ONLY */
1979 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1980 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1981 uint32_t delay = d + start_dqs_en;
1982 if (delay > IO_DQS_EN_DELAY_MAX)
1983 delay = IO_DQS_EN_DELAY_MAX;
1984 scc_mgr_set_dqs_en_delay(read_group, delay);
1986 scc_mgr_load_dqs(read_group);
1989 writel(0, &sdr_scc_mgr->update);
1991 stop = search_stop_check(write, d, rank_bgn, write_group,
1992 read_group, &bit_chk, sticky_bit_chk,
1995 if (write && (d == 0)) { /* WRITE-ONLY */
1996 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
1998 * d = 0 failed, but it passed when
1999 * testing the left edge, so it must be
2000 * marginal, set it to -1
2002 if (right_edge[i] == delay_max + 1 &&
2003 left_edge[i] != delay_max + 1)
2011 for (i = 0; i < per_dqs; i++) {
2014 * Remember a passing test as
2021 * If a right edge has not
2022 * been seen yet, then a future
2023 * passing test will mark this
2024 * edge as the left edge.
2026 if (right_edge[i] == delay_max + 1)
2027 left_edge[i] = -(d + 1);
2030 * d = 0 failed, but it passed
2031 * when testing the left edge,
2032 * so it must be marginal, set
2035 if (right_edge[i] == delay_max + 1 &&
2036 left_edge[i] != delay_max + 1)
2039 * If a right edge has not been
2040 * seen yet, then a future
2041 * passing test will mark this
2042 * edge as the left edge.
2044 else if (right_edge[i] == delay_max + 1)
2045 left_edge[i] = -(d + 1);
2049 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2050 __func__, __LINE__, d);
2051 debug_cond(DLEVEL == 2,
2052 "bit_chk_test=%i left_edge[%u]: %d ",
2053 bit_chk & 1, i, left_edge[i]);
2054 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2060 /* Check that all bits have a window */
2061 for (i = 0; i < per_dqs; i++) {
2062 debug_cond(DLEVEL == 2,
2063 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2064 __func__, __LINE__, i, left_edge[i],
2066 if ((left_edge[i] == dqs_max + 1) ||
2067 (right_edge[i] == dqs_max + 1))
2068 return i + 1; /* FIXME: If we fail, retval > 0 */
2075 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2076 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2077 * @left_edge: Left edge of the DQ/DQS phase
2078 * @right_edge: Right edge of the DQ/DQS phase
2079 * @mid_min: Best DQ/DQS phase middle setting
2081 * Find index and value of the middle of the DQ/DQS working phase.
2083 static int get_window_mid_index(const int write, int *left_edge,
2084 int *right_edge, int *mid_min)
2086 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2087 RW_MGR_MEM_DQ_PER_READ_DQS;
2088 int i, mid, min_index;
2090 /* Find middle of window for each DQ bit */
2091 *mid_min = left_edge[0] - right_edge[0];
2093 for (i = 1; i < per_dqs; i++) {
2094 mid = left_edge[i] - right_edge[i];
2095 if (mid < *mid_min) {
2102 * -mid_min/2 represents the amount that we need to move DQS.
2103 * If mid_min is odd and positive we'll need to add one to make
2104 * sure the rounding in further calculations is correct (always
2105 * bias to the right), so just add 1 for all positive values.
2109 *mid_min = *mid_min / 2;
2111 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2112 __func__, __LINE__, *mid_min, min_index);
2117 * center_dq_windows() - Center the DQ/DQS windows
2118 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2119 * @left_edge: Left edge of the DQ/DQS phase
2120 * @right_edge: Right edge of the DQ/DQS phase
2121 * @mid_min: Adjusted DQ/DQS phase middle setting
2122 * @orig_mid_min: Original DQ/DQS phase middle setting
2123 * @min_index: DQ/DQS phase middle setting index
2124 * @test_bgn: Rank number to begin the test
2125 * @dq_margin: Amount of shift for the DQ
2126 * @dqs_margin: Amount of shift for the DQS
2128 * Align the DQ/DQS windows in each group.
2130 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2131 const int mid_min, const int orig_mid_min,
2132 const int min_index, const int test_bgn,
2133 int *dq_margin, int *dqs_margin)
2135 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2136 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2137 RW_MGR_MEM_DQ_PER_READ_DQS;
2138 const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2139 SCC_MGR_IO_IN_DELAY_OFFSET;
2140 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2142 u32 temp_dq_io_delay1, temp_dq_io_delay2;
2145 /* Initialize data for export structures */
2146 *dqs_margin = delay_max + 1;
2147 *dq_margin = delay_max + 1;
2149 /* add delay to bring centre of all DQ windows to the same "level" */
2150 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2151 /* Use values before divide by 2 to reduce round off error */
2152 shift_dq = (left_edge[i] - right_edge[i] -
2153 (left_edge[min_index] - right_edge[min_index]))/2 +
2154 (orig_mid_min - mid_min);
2156 debug_cond(DLEVEL == 2,
2157 "vfifo_center: before: shift_dq[%u]=%d\n",
2160 temp_dq_io_delay1 = readl(addr + (p << 2));
2161 temp_dq_io_delay2 = readl(addr + (i << 2));
2163 if (shift_dq + temp_dq_io_delay1 > delay_max)
2164 shift_dq = delay_max - temp_dq_io_delay2;
2165 else if (shift_dq + temp_dq_io_delay1 < 0)
2166 shift_dq = -temp_dq_io_delay1;
2168 debug_cond(DLEVEL == 2,
2169 "vfifo_center: after: shift_dq[%u]=%d\n",
2173 scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
2175 scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
2179 debug_cond(DLEVEL == 2,
2180 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2181 left_edge[i] - shift_dq + (-mid_min),
2182 right_edge[i] + shift_dq - (-mid_min));
2184 /* To determine values for export structures */
2185 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2186 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2188 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2189 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2195 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2196 * @rank_bgn: Rank number
2197 * @rw_group: Read/Write Group
2198 * @test_bgn: Rank at which the test begins
2199 * @use_read_test: Perform a read test
2200 * @update_fom: Update FOM
2202 * Per-bit deskew DQ and centering.
2204 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2205 const u32 rw_group, const u32 test_bgn,
2206 const int use_read_test, const int update_fom)
2209 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2212 * Store these as signed since there are comparisons with
2215 uint32_t sticky_bit_chk;
2216 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2217 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2218 int32_t orig_mid_min, mid_min;
2219 int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
2220 int32_t dq_margin, dqs_margin;
2224 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2226 start_dqs = readl(addr);
2227 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2228 start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
2230 /* set the left and right edge of each bit to an illegal value */
2231 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2233 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2234 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2235 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2238 /* Search for the left edge of the window for each bit */
2239 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2241 left_edge, right_edge, use_read_test);
2244 /* Search for the right edge of the window for each bit */
2245 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2246 start_dqs, start_dqs_en,
2248 left_edge, right_edge, use_read_test);
2251 * Restore delay chain settings before letting the loop
2252 * in rw_mgr_mem_calibrate_vfifo to retry different
2253 * dqs/ck relationships.
2255 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2256 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2257 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2259 scc_mgr_load_dqs(rw_group);
2260 writel(0, &sdr_scc_mgr->update);
2262 debug_cond(DLEVEL == 1,
2263 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2264 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2265 if (use_read_test) {
2266 set_failing_group_stage(rw_group *
2267 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2269 CAL_SUBSTAGE_VFIFO_CENTER);
2271 set_failing_group_stage(rw_group *
2272 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2273 CAL_STAGE_VFIFO_AFTER_WRITES,
2274 CAL_SUBSTAGE_VFIFO_CENTER);
2279 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2281 /* Determine the amount we can change DQS (which is -mid_min) */
2282 orig_mid_min = mid_min;
2283 new_dqs = start_dqs - mid_min;
2284 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2285 new_dqs = IO_DQS_IN_DELAY_MAX;
2286 else if (new_dqs < 0)
2289 mid_min = start_dqs - new_dqs;
2290 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2293 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2294 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2295 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2296 else if (start_dqs_en - mid_min < 0)
2297 mid_min += start_dqs_en - mid_min;
2299 new_dqs = start_dqs - mid_min;
2301 debug_cond(DLEVEL == 1,
2302 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2304 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2307 /* Add delay to bring centre of all DQ windows to the same "level". */
2308 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2309 min_index, test_bgn, &dq_margin, &dqs_margin);
2312 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2313 final_dqs_en = start_dqs_en - mid_min;
2314 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2315 scc_mgr_load_dqs(rw_group);
2319 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2320 scc_mgr_load_dqs(rw_group);
2321 debug_cond(DLEVEL == 2,
2322 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2323 __func__, __LINE__, dq_margin, dqs_margin);
2326 * Do not remove this line as it makes sure all of our decisions
2327 * have been applied. Apply the update bit.
2329 writel(0, &sdr_scc_mgr->update);
2331 if ((dq_margin < 0) || (dqs_margin < 0))
2338 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2339 * @rw_group: Read/Write Group
2340 * @phase: DQ/DQS phase
2342 * Because initially no communication ca be reliably performed with the memory
2343 * device, the sequencer uses a guaranteed write mechanism to write data into
2344 * the memory device.
2346 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2351 /* Set a particular DQ/DQS phase. */
2352 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2354 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2355 __func__, __LINE__, rw_group, phase);
2358 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2359 * Load up the patterns used by read calibration using the
2360 * current DQDQS phase.
2362 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2364 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2368 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2369 * Back-to-Back reads of the patterns used for calibration.
2371 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2373 debug_cond(DLEVEL == 1,
2374 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2375 __func__, __LINE__, rw_group, phase);
2380 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2381 * @rw_group: Read/Write Group
2382 * @test_bgn: Rank at which the test begins
2384 * DQS enable calibration ensures reliable capture of the DQ signal without
2385 * glitches on the DQS line.
2387 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2391 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2392 * DQS and DQS Eanble Signal Relationships.
2395 /* We start at zero, so have one less dq to devide among */
2396 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2397 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2401 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2403 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2404 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2405 r += NUM_RANKS_PER_SHADOW_REG) {
2406 for (i = 0, p = test_bgn, d = 0;
2407 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2408 i++, p++, d += delay_step) {
2409 debug_cond(DLEVEL == 1,
2410 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2411 __func__, __LINE__, rw_group, r, i, p, d);
2413 scc_mgr_set_dq_in_delay(p, d);
2417 writel(0, &sdr_scc_mgr->update);
2421 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2422 * dq_in_delay values
2424 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2426 debug_cond(DLEVEL == 1,
2427 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2428 __func__, __LINE__, rw_group, !ret);
2430 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2431 r += NUM_RANKS_PER_SHADOW_REG) {
2432 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2433 writel(0, &sdr_scc_mgr->update);
2440 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2441 * @rw_group: Read/Write Group
2442 * @test_bgn: Rank at which the test begins
2443 * @use_read_test: Perform a read test
2444 * @update_fom: Update FOM
2446 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2450 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2451 const int use_read_test,
2452 const int update_fom)
2455 int ret, grp_calibrated;
2459 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2460 * Read per-bit deskew can be done on a per shadow register basis.
2463 for (rank_bgn = 0, sr = 0;
2464 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2465 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2466 /* Check if this set of ranks should be skipped entirely. */
2467 if (param->skip_shadow_regs[sr])
2470 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2480 if (!grp_calibrated)
2487 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2488 * @rw_group: Read/Write Group
2489 * @test_bgn: Rank at which the test begins
2491 * Stage 1: Calibrate the read valid prediction FIFO.
2493 * This function implements UniPHY calibration Stage 1, as explained in
2494 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2496 * - read valid prediction will consist of finding:
2497 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2498 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2499 * - we also do a per-bit deskew on the DQ lines.
2501 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2504 uint32_t dtaps_per_ptap;
2505 uint32_t failed_substage;
2509 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2511 /* Update info for sims */
2512 reg_file_set_group(rw_group);
2513 reg_file_set_stage(CAL_STAGE_VFIFO);
2514 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2516 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2518 /* USER Determine number of delay taps for each phase tap. */
2519 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2520 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2522 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2524 * In RLDRAMX we may be messing the delay of pins in
2525 * the same write rw_group but outside of the current read
2526 * the rw_group, but that's ok because we haven't calibrated
2530 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2534 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2535 /* 1) Guaranteed Write */
2536 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2540 /* 2) DQS Enable Calibration */
2541 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2544 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2548 /* 3) Centering DQ/DQS */
2550 * If doing read after write calibration, do not update
2551 * FOM now. Do it then.
2553 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2556 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2565 /* Calibration Stage 1 failed. */
2566 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2569 /* Calibration Stage 1 completed OK. */
2572 * Reset the delay chains back to zero if they have moved > 1
2573 * (check for > 1 because loop will increase d even when pass in
2577 scc_mgr_zero_group(rw_group, 1);
2582 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2583 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2586 uint32_t rank_bgn, sr;
2587 uint32_t grp_calibrated;
2588 uint32_t write_group;
2590 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2592 /* update info for sims */
2594 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2595 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2597 write_group = read_group;
2599 /* update info for sims */
2600 reg_file_set_group(read_group);
2603 /* Read per-bit deskew can be done on a per shadow register basis */
2604 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2605 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2606 /* Determine if this set of ranks should be skipped entirely */
2607 if (!param->skip_shadow_regs[sr]) {
2608 /* This is the last calibration round, update FOM here */
2609 if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2619 if (grp_calibrated == 0) {
2620 set_failing_group_stage(write_group,
2621 CAL_STAGE_VFIFO_AFTER_WRITES,
2622 CAL_SUBSTAGE_VFIFO_CENTER);
2629 /* Calibrate LFIFO to find smallest read latency */
2630 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2634 debug("%s:%d\n", __func__, __LINE__);
2636 /* update info for sims */
2637 reg_file_set_stage(CAL_STAGE_LFIFO);
2638 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2640 /* Load up the patterns used by read calibration for all ranks */
2641 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2645 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2646 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2647 __func__, __LINE__, gbl->curr_read_lat);
2649 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2657 /* reduce read latency and see if things are working */
2659 gbl->curr_read_lat--;
2660 } while (gbl->curr_read_lat > 0);
2662 /* reset the fifos to get pointers to known state */
2664 writel(0, &phy_mgr_cmd->fifo_reset);
2667 /* add a fudge factor to the read latency that was determined */
2668 gbl->curr_read_lat += 2;
2669 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2670 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2671 read_lat=%u\n", __func__, __LINE__,
2672 gbl->curr_read_lat);
2675 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2676 CAL_SUBSTAGE_READ_LATENCY);
2678 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2679 read_lat=%u\n", __func__, __LINE__,
2680 gbl->curr_read_lat);
2686 * issue write test command.
2687 * two variants are provided. one that just tests a write pattern and
2688 * another that tests datamask functionality.
2690 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2693 uint32_t mcc_instruction;
2694 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2695 ENABLE_SUPER_QUICK_CALIBRATION);
2696 uint32_t rw_wl_nop_cycles;
2700 * Set counter and jump addresses for the right
2701 * number of NOP cycles.
2702 * The number of supported NOP cycles can range from -1 to infinity
2703 * Three different cases are handled:
2705 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2706 * mechanism will be used to insert the right number of NOPs
2708 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2709 * issuing the write command will jump straight to the
2710 * micro-instruction that turns on DQS (for DDRx), or outputs write
2711 * data (for RLD), skipping
2712 * the NOP micro-instruction all together
2714 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2715 * turned on in the same micro-instruction that issues the write
2716 * command. Then we need
2717 * to directly jump to the micro-instruction that sends out the data
2719 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2720 * (2 and 3). One jump-counter (0) is used to perform multiple
2721 * write-read operations.
2722 * one counter left to issue this command in "multiple-group" mode
2725 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2727 if (rw_wl_nop_cycles == -1) {
2729 * CNTR 2 - We want to execute the special write operation that
2730 * turns on DQS right away and then skip directly to the
2731 * instruction that sends out the data. We set the counter to a
2732 * large number so that the jump is always taken.
2734 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2736 /* CNTR 3 - Not used */
2738 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2739 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2740 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2741 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2742 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2744 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2745 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2746 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2747 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2748 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2750 } else if (rw_wl_nop_cycles == 0) {
2752 * CNTR 2 - We want to skip the NOP operation and go straight
2753 * to the DQS enable instruction. We set the counter to a large
2754 * number so that the jump is always taken.
2756 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2758 /* CNTR 3 - Not used */
2760 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2761 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2762 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2764 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2765 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2766 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2770 * CNTR 2 - In this case we want to execute the next instruction
2771 * and NOT take the jump. So we set the counter to 0. The jump
2772 * address doesn't count.
2774 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2775 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2778 * CNTR 3 - Set the nop counter to the number of cycles we
2779 * need to loop for, minus 1.
2781 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2783 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2784 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2785 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2787 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2788 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2789 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2793 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2794 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2796 if (quick_write_mode)
2797 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2799 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2801 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2804 * CNTR 1 - This is used to ensure enough time elapses
2805 * for read data to come back.
2807 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2810 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2811 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2813 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2814 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2817 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2818 writel(mcc_instruction, addr + (group << 2));
2821 /* Test writes, can check for a single bit pass or multiple bit pass */
2822 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2823 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2824 uint32_t *bit_chk, uint32_t all_ranks)
2827 uint32_t correct_mask_vg;
2828 uint32_t tmp_bit_chk;
2830 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2831 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2832 uint32_t addr_rw_mgr;
2833 uint32_t base_rw_mgr;
2835 *bit_chk = param->write_correct_mask;
2836 correct_mask_vg = param->write_correct_mask_vg;
2838 for (r = rank_bgn; r < rank_end; r++) {
2839 if (param->skip_ranks[r]) {
2840 /* request to skip the rank */
2845 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2848 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2849 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2850 /* reset the fifos to get pointers to known state */
2851 writel(0, &phy_mgr_cmd->fifo_reset);
2853 tmp_bit_chk = tmp_bit_chk <<
2854 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2855 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2856 rw_mgr_mem_calibrate_write_test_issue(write_group *
2857 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2860 base_rw_mgr = readl(addr_rw_mgr);
2861 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2865 *bit_chk &= tmp_bit_chk;
2869 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2870 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2871 %u => %lu", write_group, use_dm,
2872 *bit_chk, param->write_correct_mask,
2873 (long unsigned int)(*bit_chk ==
2874 param->write_correct_mask));
2875 return *bit_chk == param->write_correct_mask;
2877 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2878 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2879 write_group, use_dm, *bit_chk);
2880 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2881 (long unsigned int)(*bit_chk != 0));
2882 return *bit_chk != 0x00;
2887 * search_window() - Search for the/part of the window with DM/DQS shift
2888 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2889 * @rank_bgn: Rank number
2890 * @write_group: Write Group
2891 * @bgn_curr: Current window begin
2892 * @end_curr: Current window end
2893 * @bgn_best: Current best window begin
2894 * @end_best: Current best window end
2895 * @win_best: Size of the best window
2896 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2898 * Search for the/part of the window with DM/DQS shift.
2900 static void search_window(const int search_dm,
2901 const u32 rank_bgn, const u32 write_group,
2902 int *bgn_curr, int *end_curr, int *bgn_best,
2903 int *end_best, int *win_best, int new_dqs)
2906 const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
2909 /* Search for the/part of the window with DM/DQS shift. */
2910 for (di = max; di >= 0; di -= DELTA_D) {
2913 scc_mgr_apply_group_dm_out1_delay(d);
2915 /* For DQS, we go from 0...max */
2918 * Note: This only shifts DQS, so are we limiting ourselve to
2919 * width of DQ unnecessarily.
2921 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2925 writel(0, &sdr_scc_mgr->update);
2927 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2928 PASS_ALL_BITS, &bit_chk,
2930 /* Set current end of the window. */
2931 *end_curr = search_dm ? -d : d;
2934 * If a starting edge of our window has not been seen
2935 * this is our current start of the DM window.
2937 if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2938 *bgn_curr = search_dm ? -d : d;
2941 * If current window is bigger than best seen.
2942 * Set best seen to be current window.
2944 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2945 *win_best = *end_curr - *bgn_curr + 1;
2946 *bgn_best = *bgn_curr;
2947 *end_best = *end_curr;
2950 /* We just saw a failing test. Reset temp edge. */
2951 *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2952 *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2954 /* Early exit is only applicable to DQS. */
2959 * Early exit optimization: if the remaining delay
2960 * chain space is less than already seen largest
2961 * window we can exit.
2963 if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
2970 * center all windows. do per-bit-deskew to possibly increase size of
2974 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2980 int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2981 int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2983 int mid_min, orig_mid_min;
2984 int new_dqs, start_dqs;
2985 int dq_margin, dqs_margin, dm_margin;
2986 int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2987 int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2988 int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2989 int end_best = IO_IO_OUT1_DELAY_MAX + 1;
2994 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2998 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
2999 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
3000 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
3002 /* Per-bit deskew. */
3005 * Set the left and right edge of each bit to an illegal value.
3006 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3009 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
3010 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3011 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3014 /* Search for the left edge of the window for each bit. */
3015 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
3017 left_edge, right_edge, 0);
3019 /* Search for the right edge of the window for each bit. */
3020 ret = search_right_edge(1, rank_bgn, write_group, 0,
3023 left_edge, right_edge, 0);
3025 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
3026 CAL_SUBSTAGE_WRITES_CENTER);
3030 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3032 /* Determine the amount we can change DQS (which is -mid_min). */
3033 orig_mid_min = mid_min;
3034 new_dqs = start_dqs;
3036 debug_cond(DLEVEL == 1,
3037 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3038 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3040 /* Add delay to bring centre of all DQ windows to the same "level". */
3041 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3042 min_index, 0, &dq_margin, &dqs_margin);
3045 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3046 writel(0, &sdr_scc_mgr->update);
3049 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3052 * Set the left and right edge of each bit to an illegal value.
3053 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3055 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3056 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3058 /* Search for the/part of the window with DM shift. */
3059 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3060 &bgn_best, &end_best, &win_best, 0);
3062 /* Reset DM delay chains to 0. */
3063 scc_mgr_apply_group_dm_out1_delay(0);
3066 * Check to see if the current window nudges up aganist 0 delay.
3067 * If so we need to continue the search by shifting DQS otherwise DQS
3068 * search begins as a new search.
3070 if (end_curr != 0) {
3071 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3072 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3075 /* Search for the/part of the window with DQS shifts. */
3076 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3077 &bgn_best, &end_best, &win_best, new_dqs);
3079 /* Assign left and right edge for cal and reporting. */
3080 left_edge[0] = -1 * bgn_best;
3081 right_edge[0] = end_best;
3083 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
3084 __func__, __LINE__, left_edge[0], right_edge[0]);
3086 /* Move DQS (back to orig). */
3087 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3091 /* Find middle of window for the DM bit. */
3092 mid = (left_edge[0] - right_edge[0]) / 2;
3094 /* Only move right, since we are not moving DQS/DQ. */
3098 /* dm_marign should fail if we never find a window. */
3102 dm_margin = left_edge[0] - mid;
3104 scc_mgr_apply_group_dm_out1_delay(mid);
3105 writel(0, &sdr_scc_mgr->update);
3107 debug_cond(DLEVEL == 2,
3108 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3109 __func__, __LINE__, left_edge[0], right_edge[0],
3111 /* Export values. */
3112 gbl->fom_out += dq_margin + dqs_margin;
3114 debug_cond(DLEVEL == 2,
3115 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3116 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3119 * Do not remove this line as it makes sure all of our
3120 * decisions have been applied.
3122 writel(0, &sdr_scc_mgr->update);
3124 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3128 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3129 * @rank_bgn: Rank number
3130 * @group: Read/Write Group
3131 * @test_bgn: Rank at which the test begins
3133 * Stage 2: Write Calibration Part One.
3135 * This function implements UniPHY calibration Stage 2, as explained in
3136 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3138 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3143 /* Update info for sims */
3144 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3146 reg_file_set_group(group);
3147 reg_file_set_stage(CAL_STAGE_WRITES);
3148 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3150 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3152 set_failing_group_stage(group, CAL_STAGE_WRITES,
3153 CAL_SUBSTAGE_WRITES_CENTER);
3161 * mem_precharge_and_activate() - Precharge all banks and activate
3163 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3165 static void mem_precharge_and_activate(void)
3169 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3170 /* Test if the rank should be skipped. */
3171 if (param->skip_ranks[r])
3175 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3177 /* Precharge all banks. */
3178 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3179 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3181 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3182 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3183 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3185 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3186 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3187 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3189 /* Activate rows. */
3190 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3191 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3196 * mem_init_latency() - Configure memory RLAT and WLAT settings
3198 * Configure memory RLAT and WLAT parameters.
3200 static void mem_init_latency(void)
3203 * For AV/CV, LFIFO is hardened and always runs at full rate
3204 * so max latency in AFI clocks, used here, is correspondingly
3207 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3210 debug("%s:%d\n", __func__, __LINE__);
3213 * Read in write latency.
3214 * WL for Hard PHY does not include additive latency.
3216 wlat = readl(&data_mgr->t_wl_add);
3217 wlat += readl(&data_mgr->mem_t_add);
3219 gbl->rw_wl_nop_cycles = wlat - 1;
3221 /* Read in readl latency. */
3222 rlat = readl(&data_mgr->t_rl_add);
3224 /* Set a pretty high read latency initially. */
3225 gbl->curr_read_lat = rlat + 16;
3226 if (gbl->curr_read_lat > max_latency)
3227 gbl->curr_read_lat = max_latency;
3229 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3231 /* Advertise write latency. */
3232 writel(wlat, &phy_mgr_cfg->afi_wlat);
3236 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3238 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3240 static void mem_skip_calibrate(void)
3242 uint32_t vfifo_offset;
3245 debug("%s:%d\n", __func__, __LINE__);
3246 /* Need to update every shadow register set used by the interface */
3247 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3248 r += NUM_RANKS_PER_SHADOW_REG) {
3250 * Set output phase alignment settings appropriate for
3253 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3254 scc_mgr_set_dqs_en_phase(i, 0);
3255 #if IO_DLL_CHAIN_LENGTH == 6
3256 scc_mgr_set_dqdqs_output_phase(i, 6);
3258 scc_mgr_set_dqdqs_output_phase(i, 7);
3263 * Write data arrives to the I/O two cycles before write
3264 * latency is reached (720 deg).
3265 * -> due to bit-slip in a/c bus
3266 * -> to allow board skew where dqs is longer than ck
3267 * -> how often can this happen!?
3268 * -> can claim back some ptaps for high freq
3269 * support if we can relax this, but i digress...
3271 * The write_clk leads mem_ck by 90 deg
3272 * The minimum ptap of the OPA is 180 deg
3273 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3274 * The write_clk is always delayed by 2 ptaps
3276 * Hence, to make DQS aligned to CK, we need to delay
3278 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3280 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3281 * gives us the number of ptaps, which simplies to:
3283 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3285 scc_mgr_set_dqdqs_output_phase(i,
3286 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3288 writel(0xff, &sdr_scc_mgr->dqs_ena);
3289 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3291 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3292 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3293 SCC_MGR_GROUP_COUNTER_OFFSET);
3295 writel(0xff, &sdr_scc_mgr->dq_ena);
3296 writel(0xff, &sdr_scc_mgr->dm_ena);
3297 writel(0, &sdr_scc_mgr->update);
3300 /* Compensate for simulation model behaviour */
3301 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3302 scc_mgr_set_dqs_bus_in_delay(i, 10);
3303 scc_mgr_load_dqs(i);
3305 writel(0, &sdr_scc_mgr->update);
3308 * ArriaV has hard FIFOs that can only be initialized by incrementing
3311 vfifo_offset = CALIB_VFIFO_OFFSET;
3312 for (j = 0; j < vfifo_offset; j++)
3313 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3314 writel(0, &phy_mgr_cmd->fifo_reset);
3317 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3318 * setting from generation-time constant.
3320 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3321 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3325 * mem_calibrate() - Memory calibration entry point.
3327 * Perform memory calibration.
3329 static uint32_t mem_calibrate(void)
3332 uint32_t rank_bgn, sr;
3333 uint32_t write_group, write_test_bgn;
3334 uint32_t read_group, read_test_bgn;
3335 uint32_t run_groups, current_run;
3336 uint32_t failing_groups = 0;
3337 uint32_t group_failed = 0;
3339 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3340 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3342 debug("%s:%d\n", __func__, __LINE__);
3344 /* Initialize the data settings */
3345 gbl->error_substage = CAL_SUBSTAGE_NIL;
3346 gbl->error_stage = CAL_STAGE_NIL;
3347 gbl->error_group = 0xff;
3351 /* Initialize WLAT and RLAT. */
3354 /* Initialize bit slips. */
3355 mem_precharge_and_activate();
3357 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3358 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3359 SCC_MGR_GROUP_COUNTER_OFFSET);
3360 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3362 scc_mgr_set_hhp_extras();
3364 scc_set_bypass_mode(i);
3367 /* Calibration is skipped. */
3368 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3370 * Set VFIFO and LFIFO to instant-on settings in skip
3373 mem_skip_calibrate();
3376 * Do not remove this line as it makes sure all of our
3377 * decisions have been applied.
3379 writel(0, &sdr_scc_mgr->update);
3383 /* Calibration is not skipped. */
3384 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3386 * Zero all delay chain/phase settings for all
3387 * groups and all shadow register sets.
3391 run_groups = ~param->skip_groups;
3393 for (write_group = 0, write_test_bgn = 0; write_group
3394 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3395 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3397 /* Initialize the group failure */
3400 current_run = run_groups & ((1 <<
3401 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3402 run_groups = run_groups >>
3403 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3405 if (current_run == 0)
3408 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3409 SCC_MGR_GROUP_COUNTER_OFFSET);
3410 scc_mgr_zero_group(write_group, 0);
3412 for (read_group = write_group * rwdqs_ratio,
3414 read_group < (write_group + 1) * rwdqs_ratio;
3416 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3417 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3420 /* Calibrate the VFIFO */
3421 if (rw_mgr_mem_calibrate_vfifo(read_group,
3425 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3428 /* The group failed, we're done. */
3432 /* Calibrate the output side */
3433 for (rank_bgn = 0, sr = 0;
3434 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3435 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3436 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3439 /* Not needed in quick mode! */
3440 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3444 * Determine if this set of ranks
3445 * should be skipped entirely.
3447 if (param->skip_shadow_regs[sr])
3450 /* Calibrate WRITEs */
3451 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3452 write_group, write_test_bgn))
3456 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3460 /* Some group failed, we're done. */
3464 for (read_group = write_group * rwdqs_ratio,
3466 read_group < (write_group + 1) * rwdqs_ratio;
3468 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3469 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3472 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3476 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3479 /* The group failed, we're done. */
3483 /* No group failed, continue as usual. */
3486 grp_failed: /* A group failed, increment the counter. */
3491 * USER If there are any failing groups then report
3494 if (failing_groups != 0)
3497 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3501 * If we're skipping groups as part of debug,
3502 * don't calibrate LFIFO.
3504 if (param->skip_groups != 0)
3507 /* Calibrate the LFIFO */
3508 if (!rw_mgr_mem_calibrate_lfifo())
3513 * Do not remove this line as it makes sure all of our decisions
3514 * have been applied.
3516 writel(0, &sdr_scc_mgr->update);
3521 * run_mem_calibrate() - Perform memory calibration
3523 * This function triggers the entire memory calibration procedure.
3525 static int run_mem_calibrate(void)
3529 debug("%s:%d\n", __func__, __LINE__);
3531 /* Reset pass/fail status shown on afi_cal_success/fail */
3532 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3534 /* Stop tracking manager. */
3535 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3537 phy_mgr_initialize();
3538 rw_mgr_mem_initialize();
3540 /* Perform the actual memory calibration. */
3541 pass = mem_calibrate();
3543 mem_precharge_and_activate();
3544 writel(0, &phy_mgr_cmd->fifo_reset);
3547 rw_mgr_mem_handoff();
3549 * In Hard PHY this is a 2-bit control:
3551 * 1: DDIO Mux Select
3553 writel(0x2, &phy_mgr_cfg->mux_sel);
3555 /* Start tracking manager. */
3556 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3562 * debug_mem_calibrate() - Report result of memory calibration
3563 * @pass: Value indicating whether calibration passed or failed
3565 * This function reports the results of the memory calibration
3566 * and writes debug information into the register file.
3568 static void debug_mem_calibrate(int pass)
3570 uint32_t debug_info;
3573 printf("%s: CALIBRATION PASSED\n", __FILE__);
3578 if (gbl->fom_in > 0xff)
3581 if (gbl->fom_out > 0xff)
3582 gbl->fom_out = 0xff;
3584 /* Update the FOM in the register file */
3585 debug_info = gbl->fom_in;
3586 debug_info |= gbl->fom_out << 8;
3587 writel(debug_info, &sdr_reg_file->fom);
3589 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3590 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3592 printf("%s: CALIBRATION FAILED\n", __FILE__);
3594 debug_info = gbl->error_stage;
3595 debug_info |= gbl->error_substage << 8;
3596 debug_info |= gbl->error_group << 16;
3598 writel(debug_info, &sdr_reg_file->failing_stage);
3599 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3600 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3602 /* Update the failing group/stage in the register file */
3603 debug_info = gbl->error_stage;
3604 debug_info |= gbl->error_substage << 8;
3605 debug_info |= gbl->error_group << 16;
3606 writel(debug_info, &sdr_reg_file->failing_stage);
3609 printf("%s: Calibration complete\n", __FILE__);
3613 * hc_initialize_rom_data() - Initialize ROM data
3615 * Initialize ROM data.
3617 static void hc_initialize_rom_data(void)
3621 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3622 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3623 writel(inst_rom_init[i], addr + (i << 2));
3625 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3626 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3627 writel(ac_rom_init[i], addr + (i << 2));
3631 * initialize_reg_file() - Initialize SDR register file
3633 * Initialize SDR register file.
3635 static void initialize_reg_file(void)
3637 /* Initialize the register file with the correct data */
3638 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3639 writel(0, &sdr_reg_file->debug_data_addr);
3640 writel(0, &sdr_reg_file->cur_stage);
3641 writel(0, &sdr_reg_file->fom);
3642 writel(0, &sdr_reg_file->failing_stage);
3643 writel(0, &sdr_reg_file->debug1);
3644 writel(0, &sdr_reg_file->debug2);
3648 * initialize_hps_phy() - Initialize HPS PHY
3650 * Initialize HPS PHY.
3652 static void initialize_hps_phy(void)
3656 * Tracking also gets configured here because it's in the
3659 uint32_t trk_sample_count = 7500;
3660 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3662 * Format is number of outer loops in the 16 MSB, sample
3667 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3669 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3670 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3671 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3672 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3674 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3675 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3677 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3678 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3680 writel(reg, &sdr_ctrl->phy_ctrl0);
3683 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3685 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3686 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3687 trk_long_idle_sample_count);
3688 writel(reg, &sdr_ctrl->phy_ctrl1);
3691 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3692 trk_long_idle_sample_count >>
3693 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3694 writel(reg, &sdr_ctrl->phy_ctrl2);
3698 * initialize_tracking() - Initialize tracking
3700 * Initialize the register file with usable initial data.
3702 static void initialize_tracking(void)
3705 * Initialize the register file with the correct data.
3706 * Compute usable version of value in case we skip full
3707 * computation later.
3709 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3710 &sdr_reg_file->dtaps_per_ptap);
3712 /* trk_sample_count */
3713 writel(7500, &sdr_reg_file->trk_sample_count);
3715 /* longidle outer loop [15:0] */
3716 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3719 * longidle sample count [31:24]
3720 * trfc, worst case of 933Mhz 4Gb [23:16]
3721 * trcd, worst case [15:8]
3724 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3725 &sdr_reg_file->delays);
3728 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3729 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3730 &sdr_reg_file->trk_rw_mgr_addr);
3732 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3733 &sdr_reg_file->trk_read_dqs_width);
3736 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3737 &sdr_reg_file->trk_rfsh);
3740 int sdram_calibration_full(void)
3742 struct param_type my_param;
3743 struct gbl_type my_gbl;
3746 memset(&my_param, 0, sizeof(my_param));
3747 memset(&my_gbl, 0, sizeof(my_gbl));
3752 /* Set the calibration enabled by default */
3753 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3755 * Only sweep all groups (regardless of fail state) by default
3756 * Set enabled read test by default.
3758 #if DISABLE_GUARANTEED_READ
3759 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3761 /* Initialize the register file */
3762 initialize_reg_file();
3764 /* Initialize any PHY CSR */
3765 initialize_hps_phy();
3767 scc_mgr_initialize();
3769 initialize_tracking();
3771 printf("%s: Preparing to start memory calibration\n", __FILE__);
3773 debug("%s:%d\n", __func__, __LINE__);
3774 debug_cond(DLEVEL == 1,
3775 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3776 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3777 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3778 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3779 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3780 debug_cond(DLEVEL == 1,
3781 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3782 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3783 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3784 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3785 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3786 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3787 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3788 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3789 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3790 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3791 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3792 IO_IO_OUT2_DELAY_MAX);
3793 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3794 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3796 hc_initialize_rom_data();
3798 /* update info for sims */
3799 reg_file_set_stage(CAL_STAGE_NIL);
3800 reg_file_set_group(0);
3803 * Load global needed for those actions that require
3804 * some dynamic calibration support.
3806 dyn_calib_steps = STATIC_CALIB_STEPS;
3808 * Load global to allow dynamic selection of delay loop settings
3809 * based on calibration mode.
3811 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3812 skip_delay_mask = 0xff;
3814 skip_delay_mask = 0x0;
3816 pass = run_mem_calibrate();
3817 debug_mem_calibrate(pass);