2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static void set_failing_group_stage(uint32_t group, uint32_t stage,
87 * Only set the global stage if there was not been any other
90 if (gbl->error_stage == CAL_STAGE_NIL) {
91 gbl->error_substage = substage;
92 gbl->error_stage = stage;
93 gbl->error_group = group;
97 static void reg_file_set_group(u16 set_group)
99 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
102 static void reg_file_set_stage(u8 set_stage)
104 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
107 static void reg_file_set_sub_stage(u8 set_sub_stage)
109 set_sub_stage &= 0xff;
110 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
114 * phy_mgr_initialize() - Initialize PHY Manager
116 * Initialize PHY Manager.
118 static void phy_mgr_initialize(void)
122 debug("%s:%d\n", __func__, __LINE__);
123 /* Calibration has control over path to memory */
125 * In Hard PHY this is a 2-bit control:
129 writel(0x3, &phy_mgr_cfg->mux_sel);
131 /* USER memory clock is not stable we begin initialization */
132 writel(0, &phy_mgr_cfg->reset_mem_stbl);
134 /* USER calibration status all set to zero */
135 writel(0, &phy_mgr_cfg->cal_status);
137 writel(0, &phy_mgr_cfg->cal_debug_info);
139 /* Init params only if we do NOT skip calibration. */
140 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
143 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
144 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
145 param->read_correct_mask_vg = (1 << ratio) - 1;
146 param->write_correct_mask_vg = (1 << ratio) - 1;
147 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
148 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
149 ratio = RW_MGR_MEM_DATA_WIDTH /
150 RW_MGR_MEM_DATA_MASK_WIDTH;
151 param->dm_correct_mask = (1 << ratio) - 1;
155 * set_rank_and_odt_mask() - Set Rank and ODT mask
157 * @odt_mode: ODT mode, OFF or READ_WRITE
159 * Set Rank and ODT mask (On-Die Termination).
161 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
167 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
170 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
171 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
173 /* Read: ODT = 0 ; Write: ODT = 1 */
177 case 2: /* 2 Ranks */
178 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
180 * - Dual-Slot , Single-Rank (1 CS per DIMM)
182 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
184 * Since MEM_NUMBER_OF_RANKS is 2, they
185 * are both single rank with 2 CS each
186 * (special for RDIMM).
188 * Read: Turn on ODT on the opposite rank
189 * Write: Turn on ODT on all ranks
191 odt_mask_0 = 0x3 & ~(1 << rank);
195 * - Single-Slot , Dual-Rank (2 CS per DIMM)
197 * Read: Turn on ODT off on all ranks
198 * Write: Turn on ODT on active rank
201 odt_mask_1 = 0x3 & (1 << rank);
204 case 4: /* 4 Ranks */
206 * ----------+-----------------------+
208 * Read From +-----------------------+
209 * Rank | 3 | 2 | 1 | 0 |
210 * ----------+-----+-----+-----+-----+
211 * 0 | 0 | 1 | 0 | 0 |
212 * 1 | 1 | 0 | 0 | 0 |
213 * 2 | 0 | 0 | 0 | 1 |
214 * 3 | 0 | 0 | 1 | 0 |
215 * ----------+-----+-----+-----+-----+
218 * ----------+-----------------------+
220 * Write To +-----------------------+
221 * Rank | 3 | 2 | 1 | 0 |
222 * ----------+-----+-----+-----+-----+
223 * 0 | 0 | 1 | 0 | 1 |
224 * 1 | 1 | 0 | 1 | 0 |
225 * 2 | 0 | 1 | 0 | 1 |
226 * 3 | 1 | 0 | 1 | 0 |
227 * ----------+-----+-----+-----+-----+
251 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
252 ((0xFF & odt_mask_0) << 8) |
253 ((0xFF & odt_mask_1) << 16);
254 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
255 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
259 * scc_mgr_set() - Set SCC Manager register
260 * @off: Base offset in SCC Manager space
261 * @grp: Read/Write group
262 * @val: Value to be set
264 * This function sets the SCC Manager (Scan Chain Control Manager) register.
266 static void scc_mgr_set(u32 off, u32 grp, u32 val)
268 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
272 * scc_mgr_initialize() - Initialize SCC Manager registers
274 * Initialize SCC Manager registers.
276 static void scc_mgr_initialize(void)
279 * Clear register file for HPS. 16 (2^4) is the size of the
280 * full register file in the scc mgr:
281 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
282 * MEM_IF_READ_DQS_WIDTH - 1);
286 for (i = 0; i < 16; i++) {
287 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
288 __func__, __LINE__, i);
289 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
293 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
295 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
298 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
300 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
303 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
305 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
308 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
310 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
313 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
315 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
319 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
329 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
335 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
337 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
338 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
342 /* load up dqs config settings */
343 static void scc_mgr_load_dqs(uint32_t dqs)
345 writel(dqs, &sdr_scc_mgr->dqs_ena);
348 /* load up dqs io config settings */
349 static void scc_mgr_load_dqs_io(void)
351 writel(0, &sdr_scc_mgr->dqs_io_ena);
354 /* load up dq config settings */
355 static void scc_mgr_load_dq(uint32_t dq_in_group)
357 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
360 /* load up dm config settings */
361 static void scc_mgr_load_dm(uint32_t dm)
363 writel(dm, &sdr_scc_mgr->dm_ena);
367 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
368 * @off: Base offset in SCC Manager space
369 * @grp: Read/Write group
370 * @val: Value to be set
371 * @update: If non-zero, trigger SCC Manager update for all ranks
373 * This function sets the SCC Manager (Scan Chain Control Manager) register
374 * and optionally triggers the SCC update for all ranks.
376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
382 r += NUM_RANKS_PER_SHADOW_REG) {
383 scc_mgr_set(off, grp, val);
385 if (update || (r == 0)) {
386 writel(grp, &sdr_scc_mgr->dqs_ena);
387 writel(0, &sdr_scc_mgr->update);
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
395 * USER although the h/w doesn't support different phases per
396 * shadow register, for simplicity our scc manager modeling
397 * keeps different phase settings per shadow reg, and it's
398 * important for us to keep them in sync to match h/w.
399 * for efficiency, the scan chain update should occur only
402 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
403 read_group, phase, 0);
406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
410 * USER although the h/w doesn't support different phases per
411 * shadow register, for simplicity our scc manager modeling
412 * keeps different phase settings per shadow reg, and it's
413 * important for us to keep them in sync to match h/w.
414 * for efficiency, the scan chain update should occur only
417 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
418 write_group, phase, 0);
421 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
425 * In shadow register mode, the T11 settings are stored in
426 * registers in the core, which are updated by the DQS_ENA
427 * signals. Not issuing the SCC_MGR_UPD command allows us to
428 * save lots of rank switching overhead, by calling
429 * select_shadow_regs_for_update with update_scan_chains
432 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
433 read_group, delay, 1);
434 writel(0, &sdr_scc_mgr->update);
438 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
439 * @write_group: Write group
440 * @delay: Delay value
442 * This function sets the OCT output delay in SCC manager.
444 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
446 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
447 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
448 const int base = write_group * ratio;
451 * Load the setting in the SCC manager
452 * Although OCT affects only write data, the OCT delay is controlled
453 * by the DQS logic block which is instantiated once per read group.
454 * For protocols where a write group consists of multiple read groups,
455 * the setting must be set multiple times.
457 for (i = 0; i < ratio; i++)
458 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
462 * scc_mgr_set_hhp_extras() - Set HHP extras.
464 * Load the fixed setting in the SCC manager HHP extras.
466 static void scc_mgr_set_hhp_extras(void)
469 * Load the fixed setting in the SCC manager
470 * bits: 0:0 = 1'b1 - DQS bypass
471 * bits: 1:1 = 1'b1 - DQ bypass
472 * bits: 4:2 = 3'b001 - rfifo_mode
473 * bits: 6:5 = 2'b01 - rfifo clock_select
474 * bits: 7:7 = 1'b0 - separate gating from ungating setting
475 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
477 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
478 (1 << 2) | (1 << 1) | (1 << 0);
479 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
480 SCC_MGR_HHP_GLOBALS_OFFSET |
481 SCC_MGR_HHP_EXTRAS_OFFSET;
483 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
486 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
491 * scc_mgr_zero_all() - Zero all DQS config
493 * Zero all DQS config.
495 static void scc_mgr_zero_all(void)
500 * USER Zero all DQS config settings, across all groups and all
503 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
504 r += NUM_RANKS_PER_SHADOW_REG) {
505 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
507 * The phases actually don't exist on a per-rank basis,
508 * but there's no harm updating them several times, so
509 * let's keep the code simple.
511 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
512 scc_mgr_set_dqs_en_phase(i, 0);
513 scc_mgr_set_dqs_en_delay(i, 0);
516 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
517 scc_mgr_set_dqdqs_output_phase(i, 0);
518 /* Arria V/Cyclone V don't have out2. */
519 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
523 /* Multicast to all DQS group enables. */
524 writel(0xff, &sdr_scc_mgr->dqs_ena);
525 writel(0, &sdr_scc_mgr->update);
529 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
530 * @write_group: Write group
532 * Set bypass mode and trigger SCC update.
534 static void scc_set_bypass_mode(const u32 write_group)
536 /* Multicast to all DQ enables. */
537 writel(0xff, &sdr_scc_mgr->dq_ena);
538 writel(0xff, &sdr_scc_mgr->dm_ena);
540 /* Update current DQS IO enable. */
541 writel(0, &sdr_scc_mgr->dqs_io_ena);
543 /* Update the DQS logic. */
544 writel(write_group, &sdr_scc_mgr->dqs_ena);
547 writel(0, &sdr_scc_mgr->update);
551 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
552 * @write_group: Write group
554 * Load DQS settings for Write Group, do not trigger SCC update.
556 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
558 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
559 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
560 const int base = write_group * ratio;
563 * Load the setting in the SCC manager
564 * Although OCT affects only write data, the OCT delay is controlled
565 * by the DQS logic block which is instantiated once per read group.
566 * For protocols where a write group consists of multiple read groups,
567 * the setting must be set multiple times.
569 for (i = 0; i < ratio; i++)
570 writel(base + i, &sdr_scc_mgr->dqs_ena);
574 * scc_mgr_zero_group() - Zero all configs for a group
576 * Zero DQ, DM, DQS and OCT configs for a group.
578 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
582 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
583 r += NUM_RANKS_PER_SHADOW_REG) {
584 /* Zero all DQ config settings. */
585 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
586 scc_mgr_set_dq_out1_delay(i, 0);
588 scc_mgr_set_dq_in_delay(i, 0);
591 /* Multicast to all DQ enables. */
592 writel(0xff, &sdr_scc_mgr->dq_ena);
594 /* Zero all DM config settings. */
595 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
596 scc_mgr_set_dm_out1_delay(i, 0);
598 /* Multicast to all DM enables. */
599 writel(0xff, &sdr_scc_mgr->dm_ena);
601 /* Zero all DQS IO settings. */
603 scc_mgr_set_dqs_io_in_delay(0);
605 /* Arria V/Cyclone V don't have out2. */
606 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
607 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
608 scc_mgr_load_dqs_for_write_group(write_group);
610 /* Multicast to all DQS IO enables (only 1 in total). */
611 writel(0, &sdr_scc_mgr->dqs_io_ena);
613 /* Hit update to zero everything. */
614 writel(0, &sdr_scc_mgr->update);
619 * apply and load a particular input delay for the DQ pins in a group
620 * group_bgn is the index of the first dq pin (in the write group)
622 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
626 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
627 scc_mgr_set_dq_in_delay(p, delay);
633 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
634 * @delay: Delay value
636 * Apply and load a particular output delay for the DQ pins in a group.
638 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
642 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
643 scc_mgr_set_dq_out1_delay(i, delay);
648 /* apply and load a particular output delay for the DM pins in a group */
649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
653 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
654 scc_mgr_set_dm_out1_delay(i, delay1);
660 /* apply and load delay on both DQS and OCT out1 */
661 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
664 scc_mgr_set_dqs_out1_delay(delay);
665 scc_mgr_load_dqs_io();
667 scc_mgr_set_oct_out1_delay(write_group, delay);
668 scc_mgr_load_dqs_for_write_group(write_group);
672 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
673 * @write_group: Write group
674 * @delay: Delay value
676 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
678 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
684 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
688 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
692 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
693 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
694 debug_cond(DLEVEL == 1,
695 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
696 __func__, __LINE__, write_group, delay, new_delay,
697 IO_IO_OUT2_DELAY_MAX,
698 new_delay - IO_IO_OUT2_DELAY_MAX);
699 new_delay -= IO_IO_OUT2_DELAY_MAX;
700 scc_mgr_set_dqs_out1_delay(new_delay);
703 scc_mgr_load_dqs_io();
706 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
707 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
708 debug_cond(DLEVEL == 1,
709 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
710 __func__, __LINE__, write_group, delay,
711 new_delay, IO_IO_OUT2_DELAY_MAX,
712 new_delay - IO_IO_OUT2_DELAY_MAX);
713 new_delay -= IO_IO_OUT2_DELAY_MAX;
714 scc_mgr_set_oct_out1_delay(write_group, new_delay);
717 scc_mgr_load_dqs_for_write_group(write_group);
721 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
722 * @write_group: Write group
723 * @delay: Delay value
725 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
728 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
733 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
734 r += NUM_RANKS_PER_SHADOW_REG) {
735 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
736 writel(0, &sdr_scc_mgr->update);
741 * set_jump_as_return() - Return instruction optimization
743 * Optimization used to recover some slots in ddr3 inst_rom could be
744 * applied to other protocols if we wanted to
746 static void set_jump_as_return(void)
749 * To save space, we replace return with jump to special shared
750 * RETURN instruction so we set the counter to large value so that
753 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
754 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
758 * should always use constants as argument to ensure all computations are
759 * performed at compile time
761 static void delay_for_n_mem_clocks(const uint32_t clocks)
768 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
771 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
772 /* scale (rounding up) to get afi clocks */
775 * Note, we don't bother accounting for being off a little bit
776 * because of a few extra instructions in outer loops
777 * Note, the loops have a test at the end, and do the test before
778 * the decrement, and so always perform the loop
779 * 1 time more than the counter value
781 if (afi_clocks == 0) {
783 } else if (afi_clocks <= 0x100) {
784 inner = afi_clocks-1;
787 } else if (afi_clocks <= 0x10000) {
789 outer = (afi_clocks-1) >> 8;
794 c_loop = (afi_clocks-1) >> 16;
798 * rom instructions are structured as follows:
800 * IDLE_LOOP2: jnz cntr0, TARGET_A
801 * IDLE_LOOP1: jnz cntr1, TARGET_B
804 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
805 * TARGET_B is set to IDLE_LOOP2 as well
807 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
808 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
810 * a little confusing, but it helps save precious space in the inst_rom
811 * and sequencer rom and keeps the delays more accurate and reduces
814 if (afi_clocks <= 0x100) {
815 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
816 &sdr_rw_load_mgr_regs->load_cntr1);
818 writel(RW_MGR_IDLE_LOOP1,
819 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
821 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
822 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
824 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
825 &sdr_rw_load_mgr_regs->load_cntr0);
827 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
828 &sdr_rw_load_mgr_regs->load_cntr1);
830 writel(RW_MGR_IDLE_LOOP2,
831 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
833 writel(RW_MGR_IDLE_LOOP2,
834 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
836 /* hack to get around compiler not being smart enough */
837 if (afi_clocks <= 0x10000) {
838 /* only need to run once */
839 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
840 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
843 writel(RW_MGR_IDLE_LOOP2,
844 SDR_PHYGRP_RWMGRGRP_ADDRESS |
845 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
846 } while (c_loop-- != 0);
849 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
853 * rw_mgr_mem_init_load_regs() - Load instruction registers
854 * @cntr0: Counter 0 value
855 * @cntr1: Counter 1 value
856 * @cntr2: Counter 2 value
857 * @jump: Jump instruction value
859 * Load instruction registers.
861 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
863 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
864 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
867 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
868 &sdr_rw_load_mgr_regs->load_cntr0);
869 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
870 &sdr_rw_load_mgr_regs->load_cntr1);
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
872 &sdr_rw_load_mgr_regs->load_cntr2);
874 /* Load jump address */
875 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
876 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
877 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
879 /* Execute count instruction */
880 writel(jump, grpaddr);
884 * rw_mgr_mem_load_user() - Load user calibration values
885 * @fin1: Final instruction 1
886 * @fin2: Final instruction 2
887 * @precharge: If 1, precharge the banks at the end
889 * Load user calibration values and optionally precharge the banks.
891 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
894 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
895 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
898 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
899 if (param->skip_ranks[r]) {
900 /* request to skip the rank */
905 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
907 /* precharge all banks ... */
909 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
912 * USER Use Mirror-ed commands for odd ranks if address
915 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
916 set_jump_as_return();
917 writel(RW_MGR_MRS2_MIRR, grpaddr);
918 delay_for_n_mem_clocks(4);
919 set_jump_as_return();
920 writel(RW_MGR_MRS3_MIRR, grpaddr);
921 delay_for_n_mem_clocks(4);
922 set_jump_as_return();
923 writel(RW_MGR_MRS1_MIRR, grpaddr);
924 delay_for_n_mem_clocks(4);
925 set_jump_as_return();
926 writel(fin1, grpaddr);
928 set_jump_as_return();
929 writel(RW_MGR_MRS2, grpaddr);
930 delay_for_n_mem_clocks(4);
931 set_jump_as_return();
932 writel(RW_MGR_MRS3, grpaddr);
933 delay_for_n_mem_clocks(4);
934 set_jump_as_return();
935 writel(RW_MGR_MRS1, grpaddr);
936 set_jump_as_return();
937 writel(fin2, grpaddr);
943 set_jump_as_return();
944 writel(RW_MGR_ZQCL, grpaddr);
946 /* tZQinit = tDLLK = 512 ck cycles */
947 delay_for_n_mem_clocks(512);
952 * rw_mgr_mem_initialize() - Initialize RW Manager
954 * Initialize RW Manager.
956 static void rw_mgr_mem_initialize(void)
958 debug("%s:%d\n", __func__, __LINE__);
960 /* The reset / cke part of initialization is broadcasted to all ranks */
961 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
962 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
965 * Here's how you load register for a loop
966 * Counters are located @ 0x800
967 * Jump address are located @ 0xC00
968 * For both, registers 0 to 3 are selected using bits 3 and 2, like
969 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
970 * I know this ain't pretty, but Avalon bus throws away the 2 least
974 /* Start with memory RESET activated */
979 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
980 * If a and b are the number of iteration in 2 nested loops
981 * it takes the following number of cycles to complete the operation:
982 * number_of_cycles = ((2 + n) * a + 2) * b
983 * where n is the number of instruction in the inner loop
984 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
987 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
989 RW_MGR_INIT_RESET_0_CKE_0);
991 /* Indicate that memory is stable. */
992 writel(1, &phy_mgr_cfg->reset_mem_stbl);
995 * transition the RESET to high
1000 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1001 * If a and b are the number of iteration in 2 nested loops
1002 * it takes the following number of cycles to complete the operation
1003 * number_of_cycles = ((2 + n) * a + 2) * b
1004 * where n is the number of instruction in the inner loop
1005 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1008 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1009 SEQ_TRESET_CNTR2_VAL,
1010 RW_MGR_INIT_RESET_1_CKE_0);
1012 /* Bring up clock enable. */
1014 /* tXRP < 250 ck cycles */
1015 delay_for_n_mem_clocks(250);
1017 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022 * At the end of calibration we have to program the user settings in, and
1023 * USER hand off the memory to the user.
1025 static void rw_mgr_mem_handoff(void)
1027 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1029 * USER need to wait tMOD (12CK or 15ns) time before issuing
1030 * other commands, but we will have plenty of NIOS cycles before
1031 * actual handoff so its okay.
1037 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1038 * @group: Write Group
1041 * Issue write test command. Two variants are provided, one that just tests
1042 * a write pattern and another that tests datamask functionality.
1044 static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
1047 const u32 quick_write_mode =
1048 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1049 ENABLE_SUPER_QUICK_CALIBRATION;
1050 u32 mcc_instruction;
1051 u32 rw_wl_nop_cycles;
1054 * Set counter and jump addresses for the right
1055 * number of NOP cycles.
1056 * The number of supported NOP cycles can range from -1 to infinity
1057 * Three different cases are handled:
1059 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1060 * mechanism will be used to insert the right number of NOPs
1062 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1063 * issuing the write command will jump straight to the
1064 * micro-instruction that turns on DQS (for DDRx), or outputs write
1065 * data (for RLD), skipping
1066 * the NOP micro-instruction all together
1068 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1069 * turned on in the same micro-instruction that issues the write
1070 * command. Then we need
1071 * to directly jump to the micro-instruction that sends out the data
1073 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1074 * (2 and 3). One jump-counter (0) is used to perform multiple
1075 * write-read operations.
1076 * one counter left to issue this command in "multiple-group" mode
1079 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
1081 if (rw_wl_nop_cycles == -1) {
1083 * CNTR 2 - We want to execute the special write operation that
1084 * turns on DQS right away and then skip directly to the
1085 * instruction that sends out the data. We set the counter to a
1086 * large number so that the jump is always taken.
1088 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1090 /* CNTR 3 - Not used */
1092 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
1093 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
1094 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1095 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1096 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1098 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
1099 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
1100 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1101 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1102 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1104 } else if (rw_wl_nop_cycles == 0) {
1106 * CNTR 2 - We want to skip the NOP operation and go straight
1107 * to the DQS enable instruction. We set the counter to a large
1108 * number so that the jump is always taken.
1110 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1112 /* CNTR 3 - Not used */
1114 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1115 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
1116 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1118 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1119 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
1120 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1124 * CNTR 2 - In this case we want to execute the next instruction
1125 * and NOT take the jump. So we set the counter to 0. The jump
1126 * address doesn't count.
1128 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1129 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1132 * CNTR 3 - Set the nop counter to the number of cycles we
1133 * need to loop for, minus 1.
1135 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1137 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
1138 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
1139 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1141 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
1142 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
1143 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1147 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1148 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1150 if (quick_write_mode)
1151 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1153 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1155 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1158 * CNTR 1 - This is used to ensure enough time elapses
1159 * for read data to come back.
1161 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1164 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
1165 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1167 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
1168 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1171 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1172 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1177 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
1178 * @rank_bgn: Rank number
1179 * @write_group: Write Group
1181 * @all_correct: All bits must be correct in the mask
1182 * @bit_chk: Resulting bit mask after the test
1183 * @all_ranks: Test all ranks
1185 * Test writes, can check for a single bit pass or multiple bit pass.
1188 rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
1189 const u32 use_dm, const u32 all_correct,
1190 u32 *bit_chk, const u32 all_ranks)
1192 const u32 rank_end = all_ranks ?
1193 RW_MGR_MEM_NUMBER_OF_RANKS :
1194 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1195 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_WRITE_DQS /
1196 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS;
1197 const u32 correct_mask_vg = param->write_correct_mask_vg;
1199 u32 tmp_bit_chk, base_rw_mgr;
1202 *bit_chk = param->write_correct_mask;
1204 for (r = rank_bgn; r < rank_end; r++) {
1205 /* Request to skip the rank */
1206 if (param->skip_ranks[r])
1210 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1213 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;
1215 /* Reset the FIFOs to get pointers to known state. */
1216 writel(0, &phy_mgr_cmd->fifo_reset);
1218 rw_mgr_mem_calibrate_write_test_issue(
1220 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS + vg,
1223 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1224 tmp_bit_chk <<= shift_ratio;
1225 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1228 *bit_chk &= tmp_bit_chk;
1231 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1233 debug_cond(DLEVEL == 2,
1234 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1235 write_group, use_dm, *bit_chk,
1236 param->write_correct_mask,
1237 *bit_chk == param->write_correct_mask);
1238 return *bit_chk == param->write_correct_mask;
1240 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1241 debug_cond(DLEVEL == 2,
1242 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1243 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1244 return *bit_chk != 0x00;
1249 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1250 * @rank_bgn: Rank number
1251 * @group: Read/Write Group
1252 * @all_ranks: Test all ranks
1254 * Performs a guaranteed read on the patterns we are going to use during a
1255 * read test to ensure memory works.
1258 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1259 const u32 all_ranks)
1261 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1262 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1263 const u32 addr_offset =
1264 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1265 const u32 rank_end = all_ranks ?
1266 RW_MGR_MEM_NUMBER_OF_RANKS :
1267 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1268 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1269 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1270 const u32 correct_mask_vg = param->read_correct_mask_vg;
1272 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1276 bit_chk = param->read_correct_mask;
1278 for (r = rank_bgn; r < rank_end; r++) {
1279 /* Request to skip the rank */
1280 if (param->skip_ranks[r])
1284 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1286 /* Load up a constant bursts of read commands */
1287 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1288 writel(RW_MGR_GUARANTEED_READ,
1289 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1291 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1292 writel(RW_MGR_GUARANTEED_READ_CONT,
1293 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1296 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1298 /* Reset the FIFOs to get pointers to known state. */
1299 writel(0, &phy_mgr_cmd->fifo_reset);
1300 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1301 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1302 writel(RW_MGR_GUARANTEED_READ,
1303 addr + addr_offset + (vg << 2));
1305 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1306 tmp_bit_chk <<= shift_ratio;
1307 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1310 bit_chk &= tmp_bit_chk;
1313 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1315 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1317 if (bit_chk != param->read_correct_mask)
1320 debug_cond(DLEVEL == 1,
1321 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1322 __func__, __LINE__, group, bit_chk,
1323 param->read_correct_mask, ret);
1329 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1330 * @rank_bgn: Rank number
1331 * @all_ranks: Test all ranks
1333 * Load up the patterns we are going to use during a read test.
1335 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1336 const int all_ranks)
1338 const u32 rank_end = all_ranks ?
1339 RW_MGR_MEM_NUMBER_OF_RANKS :
1340 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1343 debug("%s:%d\n", __func__, __LINE__);
1345 for (r = rank_bgn; r < rank_end; r++) {
1346 if (param->skip_ranks[r])
1347 /* request to skip the rank */
1351 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1353 /* Load up a constant bursts */
1354 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1356 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1357 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1359 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1361 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1362 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1364 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1366 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1367 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1369 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1371 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1372 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1374 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1375 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1378 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1382 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1383 * @rank_bgn: Rank number
1384 * @group: Read/Write group
1385 * @num_tries: Number of retries of the test
1386 * @all_correct: All bits must be correct in the mask
1387 * @bit_chk: Resulting bit mask after the test
1388 * @all_groups: Test all R/W groups
1389 * @all_ranks: Test all ranks
1391 * Try a read and see if it returns correct data back. Test has dummy reads
1392 * inserted into the mix used to align DQS enable. Test has more thorough
1393 * checks than the regular read test.
1396 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1397 const u32 num_tries, const u32 all_correct,
1399 const u32 all_groups, const u32 all_ranks)
1401 const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1402 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1403 const u32 quick_read_mode =
1404 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1405 ENABLE_SUPER_QUICK_CALIBRATION);
1406 u32 correct_mask_vg = param->read_correct_mask_vg;
1413 *bit_chk = param->read_correct_mask;
1415 for (r = rank_bgn; r < rank_end; r++) {
1416 if (param->skip_ranks[r])
1417 /* request to skip the rank */
1421 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1423 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1425 writel(RW_MGR_READ_B2B_WAIT1,
1426 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1428 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1429 writel(RW_MGR_READ_B2B_WAIT2,
1430 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1432 if (quick_read_mode)
1433 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1434 /* need at least two (1+1) reads to capture failures */
1435 else if (all_groups)
1436 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1438 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1440 writel(RW_MGR_READ_B2B,
1441 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1443 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1444 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1445 &sdr_rw_load_mgr_regs->load_cntr3);
1447 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1449 writel(RW_MGR_READ_B2B,
1450 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1453 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1455 /* Reset the FIFOs to get pointers to known state. */
1456 writel(0, &phy_mgr_cmd->fifo_reset);
1457 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1458 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1461 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1462 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1464 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1465 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1468 writel(RW_MGR_READ_B2B, addr +
1469 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1472 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1473 tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1474 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1475 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1478 *bit_chk &= tmp_bit_chk;
1481 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1482 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1484 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1487 ret = (*bit_chk == param->read_correct_mask);
1488 debug_cond(DLEVEL == 2,
1489 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1490 __func__, __LINE__, group, all_groups, *bit_chk,
1491 param->read_correct_mask, ret);
1493 ret = (*bit_chk != 0x00);
1494 debug_cond(DLEVEL == 2,
1495 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1496 __func__, __LINE__, group, all_groups, *bit_chk,
1504 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1505 * @grp: Read/Write group
1506 * @num_tries: Number of retries of the test
1507 * @all_correct: All bits must be correct in the mask
1508 * @all_groups: Test all R/W groups
1510 * Perform a READ test across all memory ranks.
1513 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1514 const u32 all_correct,
1515 const u32 all_groups)
1518 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1519 &bit_chk, all_groups, 1);
1523 * rw_mgr_incr_vfifo() - Increase VFIFO value
1524 * @grp: Read/Write group
1526 * Increase VFIFO value.
1528 static void rw_mgr_incr_vfifo(const u32 grp)
1530 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1534 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1535 * @grp: Read/Write group
1537 * Decrease VFIFO value.
1539 static void rw_mgr_decr_vfifo(const u32 grp)
1543 for (i = 0; i < VFIFO_SIZE - 1; i++)
1544 rw_mgr_incr_vfifo(grp);
1548 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1549 * @grp: Read/Write group
1551 * Push VFIFO until a failing read happens.
1553 static int find_vfifo_failing_read(const u32 grp)
1555 u32 v, ret, fail_cnt = 0;
1557 for (v = 0; v < VFIFO_SIZE; v++) {
1558 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1559 __func__, __LINE__, v);
1560 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1569 /* Fiddle with FIFO. */
1570 rw_mgr_incr_vfifo(grp);
1573 /* No failing read found! Something must have gone wrong. */
1574 debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1579 * sdr_find_phase_delay() - Find DQS enable phase or delay
1580 * @working: If 1, look for working phase/delay, if 0, look for non-working
1581 * @delay: If 1, look for delay, if 0, look for phase
1582 * @grp: Read/Write group
1583 * @work: Working window position
1584 * @work_inc: Working window increment
1585 * @pd: DQS Phase/Delay Iterator
1587 * Find working or non-working DQS enable phase setting.
1589 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1590 u32 *work, const u32 work_inc, u32 *pd)
1592 const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1595 for (; *pd <= max; (*pd)++) {
1597 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1599 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1601 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1616 * sdr_find_phase() - Find DQS enable phase
1617 * @working: If 1, look for working phase, if 0, look for non-working phase
1618 * @grp: Read/Write group
1619 * @work: Working window position
1621 * @p: DQS Phase Iterator
1623 * Find working or non-working DQS enable phase setting.
1625 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1628 const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1631 for (; *i < end; (*i)++) {
1635 ret = sdr_find_phase_delay(working, 0, grp, work,
1636 IO_DELAY_PER_OPA_TAP, p);
1640 if (*p > IO_DQS_EN_PHASE_MAX) {
1641 /* Fiddle with FIFO. */
1642 rw_mgr_incr_vfifo(grp);
1652 * sdr_working_phase() - Find working DQS enable phase
1653 * @grp: Read/Write group
1654 * @work_bgn: Working window start position
1655 * @d: dtaps output value
1656 * @p: DQS Phase Iterator
1659 * Find working DQS enable phase setting.
1661 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1664 const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1665 IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1670 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1672 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1673 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1676 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1679 /* Cannot find working solution */
1680 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1681 __func__, __LINE__);
1686 * sdr_backup_phase() - Find DQS enable backup phase
1687 * @grp: Read/Write group
1688 * @work_bgn: Working window start position
1689 * @p: DQS Phase Iterator
1691 * Find DQS enable backup phase setting.
1693 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1698 /* Special case code for backing up a phase */
1700 *p = IO_DQS_EN_PHASE_MAX;
1701 rw_mgr_decr_vfifo(grp);
1705 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1706 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1708 for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1709 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1711 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1714 *work_bgn = tmp_delay;
1718 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1721 /* Restore VFIFO to old state before we decremented it (if needed). */
1723 if (*p > IO_DQS_EN_PHASE_MAX) {
1725 rw_mgr_incr_vfifo(grp);
1728 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1732 * sdr_nonworking_phase() - Find non-working DQS enable phase
1733 * @grp: Read/Write group
1734 * @work_end: Working window end position
1735 * @p: DQS Phase Iterator
1738 * Find non-working DQS enable phase setting.
1740 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1745 *work_end += IO_DELAY_PER_OPA_TAP;
1746 if (*p > IO_DQS_EN_PHASE_MAX) {
1747 /* Fiddle with FIFO. */
1749 rw_mgr_incr_vfifo(grp);
1752 ret = sdr_find_phase(0, grp, work_end, i, p);
1754 /* Cannot see edge of failing read. */
1755 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1756 __func__, __LINE__);
1763 * sdr_find_window_center() - Find center of the working DQS window.
1764 * @grp: Read/Write group
1765 * @work_bgn: First working settings
1766 * @work_end: Last working settings
1768 * Find center of the working DQS enable window.
1770 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1777 work_mid = (work_bgn + work_end) / 2;
1779 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1780 work_bgn, work_end, work_mid);
1781 /* Get the middle delay to be less than a VFIFO delay */
1782 tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1784 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1785 work_mid %= tmp_delay;
1786 debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1788 tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1789 if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1790 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1791 p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1793 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1795 d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1796 if (d > IO_DQS_EN_DELAY_MAX)
1797 d = IO_DQS_EN_DELAY_MAX;
1798 tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1800 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1802 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1803 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1806 * push vfifo until we can successfully calibrate. We can do this
1807 * because the largest possible margin in 1 VFIFO cycle.
1809 for (i = 0; i < VFIFO_SIZE; i++) {
1810 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1811 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1814 debug_cond(DLEVEL == 2,
1815 "%s:%d center: found: ptap=%u dtap=%u\n",
1816 __func__, __LINE__, p, d);
1820 /* Fiddle with FIFO. */
1821 rw_mgr_incr_vfifo(grp);
1824 debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1825 __func__, __LINE__);
1830 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1831 * @grp: Read/Write Group
1833 * Find a good DQS enable to use.
1835 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1839 u32 work_bgn, work_end;
1840 u32 found_passing_read, found_failing_read, initial_failing_dtap;
1843 debug("%s:%d %u\n", __func__, __LINE__, grp);
1845 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1847 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1848 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1850 /* Step 0: Determine number of delay taps for each phase tap. */
1851 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1853 /* Step 1: First push vfifo until we get a failing read. */
1854 find_vfifo_failing_read(grp);
1856 /* Step 2: Find first working phase, increment in ptaps. */
1858 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1862 work_end = work_bgn;
1865 * If d is 0 then the working window covers a phase tap and we can
1866 * follow the old procedure. Otherwise, we've found the beginning
1867 * and we need to increment the dtaps until we find the end.
1871 * Step 3a: If we have room, back off by one and
1872 * increment in dtaps.
1874 sdr_backup_phase(grp, &work_bgn, &p);
1877 * Step 4a: go forward from working phase to non working
1878 * phase, increment in ptaps.
1880 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1884 /* Step 5a: Back off one from last, increment in dtaps. */
1886 /* Special case code for backing up a phase */
1888 p = IO_DQS_EN_PHASE_MAX;
1889 rw_mgr_decr_vfifo(grp);
1894 work_end -= IO_DELAY_PER_OPA_TAP;
1895 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1899 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1900 __func__, __LINE__, p);
1903 /* The dtap increment to find the failing edge is done here. */
1904 sdr_find_phase_delay(0, 1, grp, &work_end,
1905 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1907 /* Go back to working dtap */
1909 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1911 debug_cond(DLEVEL == 2,
1912 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1913 __func__, __LINE__, p, d - 1, work_end);
1915 if (work_end < work_bgn) {
1917 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1918 __func__, __LINE__);
1922 debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1923 __func__, __LINE__, work_bgn, work_end);
1926 * We need to calculate the number of dtaps that equal a ptap.
1927 * To do that we'll back up a ptap and re-find the edge of the
1928 * window using dtaps
1930 debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1931 __func__, __LINE__);
1933 /* Special case code for backing up a phase */
1935 p = IO_DQS_EN_PHASE_MAX;
1936 rw_mgr_decr_vfifo(grp);
1937 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1938 __func__, __LINE__, p);
1941 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1942 __func__, __LINE__, p);
1945 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1948 * Increase dtap until we first see a passing read (in case the
1949 * window is smaller than a ptap), and then a failing read to
1950 * mark the edge of the window again.
1953 /* Find a passing read. */
1954 debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1955 __func__, __LINE__);
1957 initial_failing_dtap = d;
1959 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1960 if (found_passing_read) {
1961 /* Find a failing read. */
1962 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1963 __func__, __LINE__);
1965 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1968 debug_cond(DLEVEL == 1,
1969 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1970 __func__, __LINE__);
1974 * The dynamically calculated dtaps_per_ptap is only valid if we
1975 * found a passing/failing read. If we didn't, it means d hit the max
1976 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1977 * statically calculated value.
1979 if (found_passing_read && found_failing_read)
1980 dtaps_per_ptap = d - initial_failing_dtap;
1982 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1983 debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1984 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1986 /* Step 6: Find the centre of the window. */
1987 ret = sdr_find_window_center(grp, work_bgn, work_end);
1993 * search_stop_check() - Check if the detected edge is valid
1994 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1996 * @rank_bgn: Rank number
1997 * @write_group: Write Group
1998 * @read_group: Read Group
1999 * @bit_chk: Resulting bit mask after the test
2000 * @sticky_bit_chk: Resulting sticky bit mask after the test
2001 * @use_read_test: Perform read test
2003 * Test if the found edge is valid.
2005 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
2006 const u32 write_group, const u32 read_group,
2007 u32 *bit_chk, u32 *sticky_bit_chk,
2008 const u32 use_read_test)
2010 const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
2011 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
2012 const u32 correct_mask = write ? param->write_correct_mask :
2013 param->read_correct_mask;
2014 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2015 RW_MGR_MEM_DQ_PER_READ_DQS;
2018 * Stop searching when the read test doesn't pass AND when
2019 * we've seen a passing read on every bit.
2021 if (write) { /* WRITE-ONLY */
2022 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2025 } else if (use_read_test) { /* READ-ONLY */
2026 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
2028 PASS_ONE_BIT, bit_chk,
2030 } else { /* READ-ONLY */
2031 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
2032 PASS_ONE_BIT, bit_chk, 0);
2033 *bit_chk = *bit_chk >> (per_dqs *
2034 (read_group - (write_group * ratio)));
2035 ret = (*bit_chk == 0);
2037 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2038 ret = ret && (*sticky_bit_chk == correct_mask);
2039 debug_cond(DLEVEL == 2,
2040 "%s:%d center(left): dtap=%u => %u == %u && %u",
2041 __func__, __LINE__, d,
2042 *sticky_bit_chk, correct_mask, ret);
2047 * search_left_edge() - Find left edge of DQ/DQS working phase
2048 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2049 * @rank_bgn: Rank number
2050 * @write_group: Write Group
2051 * @read_group: Read Group
2052 * @test_bgn: Rank number to begin the test
2053 * @sticky_bit_chk: Resulting sticky bit mask after the test
2054 * @left_edge: Left edge of the DQ/DQS phase
2055 * @right_edge: Right edge of the DQ/DQS phase
2056 * @use_read_test: Perform read test
2058 * Find left edge of DQ/DQS working phase.
2060 static void search_left_edge(const int write, const int rank_bgn,
2061 const u32 write_group, const u32 read_group, const u32 test_bgn,
2062 u32 *sticky_bit_chk,
2063 int *left_edge, int *right_edge, const u32 use_read_test)
2065 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2066 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2067 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2068 RW_MGR_MEM_DQ_PER_READ_DQS;
2072 for (d = 0; d <= dqs_max; d++) {
2074 scc_mgr_apply_group_dq_out1_delay(d);
2076 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
2078 writel(0, &sdr_scc_mgr->update);
2080 stop = search_stop_check(write, d, rank_bgn, write_group,
2081 read_group, &bit_chk, sticky_bit_chk,
2087 for (i = 0; i < per_dqs; i++) {
2090 * Remember a passing test as
2096 * If a left edge has not been seen
2097 * yet, then a future passing test
2098 * will mark this edge as the right
2101 if (left_edge[i] == delay_max + 1)
2102 right_edge[i] = -(d + 1);
2108 /* Reset DQ delay chains to 0 */
2110 scc_mgr_apply_group_dq_out1_delay(0);
2112 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2114 *sticky_bit_chk = 0;
2115 for (i = per_dqs - 1; i >= 0; i--) {
2116 debug_cond(DLEVEL == 2,
2117 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2118 __func__, __LINE__, i, left_edge[i],
2122 * Check for cases where we haven't found the left edge,
2123 * which makes our assignment of the the right edge invalid.
2124 * Reset it to the illegal value.
2126 if ((left_edge[i] == delay_max + 1) &&
2127 (right_edge[i] != delay_max + 1)) {
2128 right_edge[i] = delay_max + 1;
2129 debug_cond(DLEVEL == 2,
2130 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2131 __func__, __LINE__, i, right_edge[i]);
2136 * READ: except for bits where we have seen both
2137 * the left and right edge.
2138 * WRITE: except for bits where we have seen the
2141 *sticky_bit_chk <<= 1;
2143 if (left_edge[i] != delay_max + 1)
2144 *sticky_bit_chk |= 1;
2146 if ((left_edge[i] != delay_max + 1) &&
2147 (right_edge[i] != delay_max + 1))
2148 *sticky_bit_chk |= 1;
2156 * search_right_edge() - Find right edge of DQ/DQS working phase
2157 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2158 * @rank_bgn: Rank number
2159 * @write_group: Write Group
2160 * @read_group: Read Group
2161 * @start_dqs: DQS start phase
2162 * @start_dqs_en: DQS enable start phase
2163 * @sticky_bit_chk: Resulting sticky bit mask after the test
2164 * @left_edge: Left edge of the DQ/DQS phase
2165 * @right_edge: Right edge of the DQ/DQS phase
2166 * @use_read_test: Perform read test
2168 * Find right edge of DQ/DQS working phase.
2170 static int search_right_edge(const int write, const int rank_bgn,
2171 const u32 write_group, const u32 read_group,
2172 const int start_dqs, const int start_dqs_en,
2173 u32 *sticky_bit_chk,
2174 int *left_edge, int *right_edge, const u32 use_read_test)
2176 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2177 const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
2178 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2179 RW_MGR_MEM_DQ_PER_READ_DQS;
2183 for (d = 0; d <= dqs_max - start_dqs; d++) {
2184 if (write) { /* WRITE-ONLY */
2185 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2187 } else { /* READ-ONLY */
2188 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2189 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2190 uint32_t delay = d + start_dqs_en;
2191 if (delay > IO_DQS_EN_DELAY_MAX)
2192 delay = IO_DQS_EN_DELAY_MAX;
2193 scc_mgr_set_dqs_en_delay(read_group, delay);
2195 scc_mgr_load_dqs(read_group);
2198 writel(0, &sdr_scc_mgr->update);
2200 stop = search_stop_check(write, d, rank_bgn, write_group,
2201 read_group, &bit_chk, sticky_bit_chk,
2204 if (write && (d == 0)) { /* WRITE-ONLY */
2205 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2207 * d = 0 failed, but it passed when
2208 * testing the left edge, so it must be
2209 * marginal, set it to -1
2211 if (right_edge[i] == delay_max + 1 &&
2212 left_edge[i] != delay_max + 1)
2220 for (i = 0; i < per_dqs; i++) {
2223 * Remember a passing test as
2230 * If a right edge has not
2231 * been seen yet, then a future
2232 * passing test will mark this
2233 * edge as the left edge.
2235 if (right_edge[i] == delay_max + 1)
2236 left_edge[i] = -(d + 1);
2239 * d = 0 failed, but it passed
2240 * when testing the left edge,
2241 * so it must be marginal, set
2244 if (right_edge[i] == delay_max + 1 &&
2245 left_edge[i] != delay_max + 1)
2248 * If a right edge has not been
2249 * seen yet, then a future
2250 * passing test will mark this
2251 * edge as the left edge.
2253 else if (right_edge[i] == delay_max + 1)
2254 left_edge[i] = -(d + 1);
2258 debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
2259 __func__, __LINE__, d);
2260 debug_cond(DLEVEL == 2,
2261 "bit_chk_test=%i left_edge[%u]: %d ",
2262 bit_chk & 1, i, left_edge[i]);
2263 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2269 /* Check that all bits have a window */
2270 for (i = 0; i < per_dqs; i++) {
2271 debug_cond(DLEVEL == 2,
2272 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2273 __func__, __LINE__, i, left_edge[i],
2275 if ((left_edge[i] == dqs_max + 1) ||
2276 (right_edge[i] == dqs_max + 1))
2277 return i + 1; /* FIXME: If we fail, retval > 0 */
2284 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2285 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2286 * @left_edge: Left edge of the DQ/DQS phase
2287 * @right_edge: Right edge of the DQ/DQS phase
2288 * @mid_min: Best DQ/DQS phase middle setting
2290 * Find index and value of the middle of the DQ/DQS working phase.
2292 static int get_window_mid_index(const int write, int *left_edge,
2293 int *right_edge, int *mid_min)
2295 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2296 RW_MGR_MEM_DQ_PER_READ_DQS;
2297 int i, mid, min_index;
2299 /* Find middle of window for each DQ bit */
2300 *mid_min = left_edge[0] - right_edge[0];
2302 for (i = 1; i < per_dqs; i++) {
2303 mid = left_edge[i] - right_edge[i];
2304 if (mid < *mid_min) {
2311 * -mid_min/2 represents the amount that we need to move DQS.
2312 * If mid_min is odd and positive we'll need to add one to make
2313 * sure the rounding in further calculations is correct (always
2314 * bias to the right), so just add 1 for all positive values.
2318 *mid_min = *mid_min / 2;
2320 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2321 __func__, __LINE__, *mid_min, min_index);
2326 * center_dq_windows() - Center the DQ/DQS windows
2327 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2328 * @left_edge: Left edge of the DQ/DQS phase
2329 * @right_edge: Right edge of the DQ/DQS phase
2330 * @mid_min: Adjusted DQ/DQS phase middle setting
2331 * @orig_mid_min: Original DQ/DQS phase middle setting
2332 * @min_index: DQ/DQS phase middle setting index
2333 * @test_bgn: Rank number to begin the test
2334 * @dq_margin: Amount of shift for the DQ
2335 * @dqs_margin: Amount of shift for the DQS
2337 * Align the DQ/DQS windows in each group.
2339 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2340 const int mid_min, const int orig_mid_min,
2341 const int min_index, const int test_bgn,
2342 int *dq_margin, int *dqs_margin)
2344 const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
2345 const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
2346 RW_MGR_MEM_DQ_PER_READ_DQS;
2347 const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2348 SCC_MGR_IO_IN_DELAY_OFFSET;
2349 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2351 u32 temp_dq_io_delay1, temp_dq_io_delay2;
2354 /* Initialize data for export structures */
2355 *dqs_margin = delay_max + 1;
2356 *dq_margin = delay_max + 1;
2358 /* add delay to bring centre of all DQ windows to the same "level" */
2359 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2360 /* Use values before divide by 2 to reduce round off error */
2361 shift_dq = (left_edge[i] - right_edge[i] -
2362 (left_edge[min_index] - right_edge[min_index]))/2 +
2363 (orig_mid_min - mid_min);
2365 debug_cond(DLEVEL == 2,
2366 "vfifo_center: before: shift_dq[%u]=%d\n",
2369 temp_dq_io_delay1 = readl(addr + (p << 2));
2370 temp_dq_io_delay2 = readl(addr + (i << 2));
2372 if (shift_dq + temp_dq_io_delay1 > delay_max)
2373 shift_dq = delay_max - temp_dq_io_delay2;
2374 else if (shift_dq + temp_dq_io_delay1 < 0)
2375 shift_dq = -temp_dq_io_delay1;
2377 debug_cond(DLEVEL == 2,
2378 "vfifo_center: after: shift_dq[%u]=%d\n",
2382 scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
2384 scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
2388 debug_cond(DLEVEL == 2,
2389 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2390 left_edge[i] - shift_dq + (-mid_min),
2391 right_edge[i] + shift_dq - (-mid_min));
2393 /* To determine values for export structures */
2394 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2395 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2397 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2398 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2404 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2405 * @rank_bgn: Rank number
2406 * @rw_group: Read/Write Group
2407 * @test_bgn: Rank at which the test begins
2408 * @use_read_test: Perform a read test
2409 * @update_fom: Update FOM
2411 * Per-bit deskew DQ and centering.
2413 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2414 const u32 rw_group, const u32 test_bgn,
2415 const int use_read_test, const int update_fom)
2418 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2421 * Store these as signed since there are comparisons with
2424 uint32_t sticky_bit_chk;
2425 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2426 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
2427 int32_t orig_mid_min, mid_min;
2428 int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
2429 int32_t dq_margin, dqs_margin;
2433 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2435 start_dqs = readl(addr);
2436 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2437 start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
2439 /* set the left and right edge of each bit to an illegal value */
2440 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
2442 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2443 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2444 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
2447 /* Search for the left edge of the window for each bit */
2448 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2450 left_edge, right_edge, use_read_test);
2453 /* Search for the right edge of the window for each bit */
2454 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2455 start_dqs, start_dqs_en,
2457 left_edge, right_edge, use_read_test);
2460 * Restore delay chain settings before letting the loop
2461 * in rw_mgr_mem_calibrate_vfifo to retry different
2462 * dqs/ck relationships.
2464 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2465 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2466 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2468 scc_mgr_load_dqs(rw_group);
2469 writel(0, &sdr_scc_mgr->update);
2471 debug_cond(DLEVEL == 1,
2472 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2473 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2474 if (use_read_test) {
2475 set_failing_group_stage(rw_group *
2476 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2478 CAL_SUBSTAGE_VFIFO_CENTER);
2480 set_failing_group_stage(rw_group *
2481 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2482 CAL_STAGE_VFIFO_AFTER_WRITES,
2483 CAL_SUBSTAGE_VFIFO_CENTER);
2488 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2490 /* Determine the amount we can change DQS (which is -mid_min) */
2491 orig_mid_min = mid_min;
2492 new_dqs = start_dqs - mid_min;
2493 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2494 new_dqs = IO_DQS_IN_DELAY_MAX;
2495 else if (new_dqs < 0)
2498 mid_min = start_dqs - new_dqs;
2499 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2502 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2503 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2504 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2505 else if (start_dqs_en - mid_min < 0)
2506 mid_min += start_dqs_en - mid_min;
2508 new_dqs = start_dqs - mid_min;
2510 debug_cond(DLEVEL == 1,
2511 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2513 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2516 /* Add delay to bring centre of all DQ windows to the same "level". */
2517 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2518 min_index, test_bgn, &dq_margin, &dqs_margin);
2521 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2522 final_dqs_en = start_dqs_en - mid_min;
2523 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2524 scc_mgr_load_dqs(rw_group);
2528 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2529 scc_mgr_load_dqs(rw_group);
2530 debug_cond(DLEVEL == 2,
2531 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2532 __func__, __LINE__, dq_margin, dqs_margin);
2535 * Do not remove this line as it makes sure all of our decisions
2536 * have been applied. Apply the update bit.
2538 writel(0, &sdr_scc_mgr->update);
2540 if ((dq_margin < 0) || (dqs_margin < 0))
2547 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2548 * @rw_group: Read/Write Group
2549 * @phase: DQ/DQS phase
2551 * Because initially no communication ca be reliably performed with the memory
2552 * device, the sequencer uses a guaranteed write mechanism to write data into
2553 * the memory device.
2555 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2560 /* Set a particular DQ/DQS phase. */
2561 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2563 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2564 __func__, __LINE__, rw_group, phase);
2567 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2568 * Load up the patterns used by read calibration using the
2569 * current DQDQS phase.
2571 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2573 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2577 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2578 * Back-to-Back reads of the patterns used for calibration.
2580 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2582 debug_cond(DLEVEL == 1,
2583 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2584 __func__, __LINE__, rw_group, phase);
2589 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2590 * @rw_group: Read/Write Group
2591 * @test_bgn: Rank at which the test begins
2593 * DQS enable calibration ensures reliable capture of the DQ signal without
2594 * glitches on the DQS line.
2596 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2600 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2601 * DQS and DQS Eanble Signal Relationships.
2604 /* We start at zero, so have one less dq to devide among */
2605 const u32 delay_step = IO_IO_IN_DELAY_MAX /
2606 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2610 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2612 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2613 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2614 r += NUM_RANKS_PER_SHADOW_REG) {
2615 for (i = 0, p = test_bgn, d = 0;
2616 i < RW_MGR_MEM_DQ_PER_READ_DQS;
2617 i++, p++, d += delay_step) {
2618 debug_cond(DLEVEL == 1,
2619 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2620 __func__, __LINE__, rw_group, r, i, p, d);
2622 scc_mgr_set_dq_in_delay(p, d);
2626 writel(0, &sdr_scc_mgr->update);
2630 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2631 * dq_in_delay values
2633 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2635 debug_cond(DLEVEL == 1,
2636 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2637 __func__, __LINE__, rw_group, !ret);
2639 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2640 r += NUM_RANKS_PER_SHADOW_REG) {
2641 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2642 writel(0, &sdr_scc_mgr->update);
2649 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2650 * @rw_group: Read/Write Group
2651 * @test_bgn: Rank at which the test begins
2652 * @use_read_test: Perform a read test
2653 * @update_fom: Update FOM
2655 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2659 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2660 const int use_read_test,
2661 const int update_fom)
2664 int ret, grp_calibrated;
2668 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2669 * Read per-bit deskew can be done on a per shadow register basis.
2672 for (rank_bgn = 0, sr = 0;
2673 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2674 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2675 /* Check if this set of ranks should be skipped entirely. */
2676 if (param->skip_shadow_regs[sr])
2679 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2689 if (!grp_calibrated)
2696 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2697 * @rw_group: Read/Write Group
2698 * @test_bgn: Rank at which the test begins
2700 * Stage 1: Calibrate the read valid prediction FIFO.
2702 * This function implements UniPHY calibration Stage 1, as explained in
2703 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2705 * - read valid prediction will consist of finding:
2706 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2707 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2708 * - we also do a per-bit deskew on the DQ lines.
2710 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2713 uint32_t dtaps_per_ptap;
2714 uint32_t failed_substage;
2718 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2720 /* Update info for sims */
2721 reg_file_set_group(rw_group);
2722 reg_file_set_stage(CAL_STAGE_VFIFO);
2723 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2725 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2727 /* USER Determine number of delay taps for each phase tap. */
2728 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2729 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2731 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2733 * In RLDRAMX we may be messing the delay of pins in
2734 * the same write rw_group but outside of the current read
2735 * the rw_group, but that's ok because we haven't calibrated
2739 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2743 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2744 /* 1) Guaranteed Write */
2745 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2749 /* 2) DQS Enable Calibration */
2750 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2753 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2757 /* 3) Centering DQ/DQS */
2759 * If doing read after write calibration, do not update
2760 * FOM now. Do it then.
2762 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2765 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2774 /* Calibration Stage 1 failed. */
2775 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2778 /* Calibration Stage 1 completed OK. */
2781 * Reset the delay chains back to zero if they have moved > 1
2782 * (check for > 1 because loop will increase d even when pass in
2786 scc_mgr_zero_group(rw_group, 1);
2792 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2793 * @rw_group: Read/Write Group
2794 * @test_bgn: Rank at which the test begins
2796 * Stage 3: DQ/DQS Centering.
2798 * This function implements UniPHY calibration Stage 3, as explained in
2799 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2801 static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
2806 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2808 /* Update info for sims. */
2809 reg_file_set_group(rw_group);
2810 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2811 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2813 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
2815 set_failing_group_stage(rw_group,
2816 CAL_STAGE_VFIFO_AFTER_WRITES,
2817 CAL_SUBSTAGE_VFIFO_CENTER);
2821 /* Calibrate LFIFO to find smallest read latency */
2822 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2826 debug("%s:%d\n", __func__, __LINE__);
2828 /* update info for sims */
2829 reg_file_set_stage(CAL_STAGE_LFIFO);
2830 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2832 /* Load up the patterns used by read calibration for all ranks */
2833 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2837 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2838 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2839 __func__, __LINE__, gbl->curr_read_lat);
2841 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2849 /* reduce read latency and see if things are working */
2851 gbl->curr_read_lat--;
2852 } while (gbl->curr_read_lat > 0);
2854 /* reset the fifos to get pointers to known state */
2856 writel(0, &phy_mgr_cmd->fifo_reset);
2859 /* add a fudge factor to the read latency that was determined */
2860 gbl->curr_read_lat += 2;
2861 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2862 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2863 read_lat=%u\n", __func__, __LINE__,
2864 gbl->curr_read_lat);
2867 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2868 CAL_SUBSTAGE_READ_LATENCY);
2870 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2871 read_lat=%u\n", __func__, __LINE__,
2872 gbl->curr_read_lat);
2878 * search_window() - Search for the/part of the window with DM/DQS shift
2879 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2880 * @rank_bgn: Rank number
2881 * @write_group: Write Group
2882 * @bgn_curr: Current window begin
2883 * @end_curr: Current window end
2884 * @bgn_best: Current best window begin
2885 * @end_best: Current best window end
2886 * @win_best: Size of the best window
2887 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2889 * Search for the/part of the window with DM/DQS shift.
2891 static void search_window(const int search_dm,
2892 const u32 rank_bgn, const u32 write_group,
2893 int *bgn_curr, int *end_curr, int *bgn_best,
2894 int *end_best, int *win_best, int new_dqs)
2897 const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
2900 /* Search for the/part of the window with DM/DQS shift. */
2901 for (di = max; di >= 0; di -= DELTA_D) {
2904 scc_mgr_apply_group_dm_out1_delay(d);
2906 /* For DQS, we go from 0...max */
2909 * Note: This only shifts DQS, so are we limiting ourselve to
2910 * width of DQ unnecessarily.
2912 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2916 writel(0, &sdr_scc_mgr->update);
2918 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2919 PASS_ALL_BITS, &bit_chk,
2921 /* Set current end of the window. */
2922 *end_curr = search_dm ? -d : d;
2925 * If a starting edge of our window has not been seen
2926 * this is our current start of the DM window.
2928 if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2929 *bgn_curr = search_dm ? -d : d;
2932 * If current window is bigger than best seen.
2933 * Set best seen to be current window.
2935 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2936 *win_best = *end_curr - *bgn_curr + 1;
2937 *bgn_best = *bgn_curr;
2938 *end_best = *end_curr;
2941 /* We just saw a failing test. Reset temp edge. */
2942 *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2943 *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2945 /* Early exit is only applicable to DQS. */
2950 * Early exit optimization: if the remaining delay
2951 * chain space is less than already seen largest
2952 * window we can exit.
2954 if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
2961 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2962 * @rank_bgn: Rank number
2963 * @write_group: Write group
2964 * @test_bgn: Rank at which the test begins
2966 * Center all windows. Do per-bit-deskew to possibly increase size of
2970 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2976 int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2977 int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2979 int mid_min, orig_mid_min;
2980 int new_dqs, start_dqs;
2981 int dq_margin, dqs_margin, dm_margin;
2982 int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2983 int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2984 int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2985 int end_best = IO_IO_OUT1_DELAY_MAX + 1;
2990 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2994 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
2995 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
2996 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2998 /* Per-bit deskew. */
3001 * Set the left and right edge of each bit to an illegal value.
3002 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3005 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
3006 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3007 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
3010 /* Search for the left edge of the window for each bit. */
3011 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
3013 left_edge, right_edge, 0);
3015 /* Search for the right edge of the window for each bit. */
3016 ret = search_right_edge(1, rank_bgn, write_group, 0,
3019 left_edge, right_edge, 0);
3021 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
3022 CAL_SUBSTAGE_WRITES_CENTER);
3026 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3028 /* Determine the amount we can change DQS (which is -mid_min). */
3029 orig_mid_min = mid_min;
3030 new_dqs = start_dqs;
3032 debug_cond(DLEVEL == 1,
3033 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3034 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3036 /* Add delay to bring centre of all DQ windows to the same "level". */
3037 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3038 min_index, 0, &dq_margin, &dqs_margin);
3041 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3042 writel(0, &sdr_scc_mgr->update);
3045 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3048 * Set the left and right edge of each bit to an illegal value.
3049 * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
3051 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3052 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3054 /* Search for the/part of the window with DM shift. */
3055 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3056 &bgn_best, &end_best, &win_best, 0);
3058 /* Reset DM delay chains to 0. */
3059 scc_mgr_apply_group_dm_out1_delay(0);
3062 * Check to see if the current window nudges up aganist 0 delay.
3063 * If so we need to continue the search by shifting DQS otherwise DQS
3064 * search begins as a new search.
3066 if (end_curr != 0) {
3067 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3068 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3071 /* Search for the/part of the window with DQS shifts. */
3072 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3073 &bgn_best, &end_best, &win_best, new_dqs);
3075 /* Assign left and right edge for cal and reporting. */
3076 left_edge[0] = -1 * bgn_best;
3077 right_edge[0] = end_best;
3079 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
3080 __func__, __LINE__, left_edge[0], right_edge[0]);
3082 /* Move DQS (back to orig). */
3083 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3087 /* Find middle of window for the DM bit. */
3088 mid = (left_edge[0] - right_edge[0]) / 2;
3090 /* Only move right, since we are not moving DQS/DQ. */
3094 /* dm_marign should fail if we never find a window. */
3098 dm_margin = left_edge[0] - mid;
3100 scc_mgr_apply_group_dm_out1_delay(mid);
3101 writel(0, &sdr_scc_mgr->update);
3103 debug_cond(DLEVEL == 2,
3104 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3105 __func__, __LINE__, left_edge[0], right_edge[0],
3107 /* Export values. */
3108 gbl->fom_out += dq_margin + dqs_margin;
3110 debug_cond(DLEVEL == 2,
3111 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3112 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3115 * Do not remove this line as it makes sure all of our
3116 * decisions have been applied.
3118 writel(0, &sdr_scc_mgr->update);
3120 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3127 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3128 * @rank_bgn: Rank number
3129 * @group: Read/Write Group
3130 * @test_bgn: Rank at which the test begins
3132 * Stage 2: Write Calibration Part One.
3134 * This function implements UniPHY calibration Stage 2, as explained in
3135 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3137 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3142 /* Update info for sims */
3143 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3145 reg_file_set_group(group);
3146 reg_file_set_stage(CAL_STAGE_WRITES);
3147 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3149 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3151 set_failing_group_stage(group, CAL_STAGE_WRITES,
3152 CAL_SUBSTAGE_WRITES_CENTER);
3158 * mem_precharge_and_activate() - Precharge all banks and activate
3160 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3162 static void mem_precharge_and_activate(void)
3166 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3167 /* Test if the rank should be skipped. */
3168 if (param->skip_ranks[r])
3172 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3174 /* Precharge all banks. */
3175 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3176 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3178 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3179 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3180 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3182 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3183 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3184 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3186 /* Activate rows. */
3187 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3188 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3193 * mem_init_latency() - Configure memory RLAT and WLAT settings
3195 * Configure memory RLAT and WLAT parameters.
3197 static void mem_init_latency(void)
3200 * For AV/CV, LFIFO is hardened and always runs at full rate
3201 * so max latency in AFI clocks, used here, is correspondingly
3204 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3207 debug("%s:%d\n", __func__, __LINE__);
3210 * Read in write latency.
3211 * WL for Hard PHY does not include additive latency.
3213 wlat = readl(&data_mgr->t_wl_add);
3214 wlat += readl(&data_mgr->mem_t_add);
3216 gbl->rw_wl_nop_cycles = wlat - 1;
3218 /* Read in readl latency. */
3219 rlat = readl(&data_mgr->t_rl_add);
3221 /* Set a pretty high read latency initially. */
3222 gbl->curr_read_lat = rlat + 16;
3223 if (gbl->curr_read_lat > max_latency)
3224 gbl->curr_read_lat = max_latency;
3226 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3228 /* Advertise write latency. */
3229 writel(wlat, &phy_mgr_cfg->afi_wlat);
3233 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3235 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3237 static void mem_skip_calibrate(void)
3239 uint32_t vfifo_offset;
3242 debug("%s:%d\n", __func__, __LINE__);
3243 /* Need to update every shadow register set used by the interface */
3244 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3245 r += NUM_RANKS_PER_SHADOW_REG) {
3247 * Set output phase alignment settings appropriate for
3250 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3251 scc_mgr_set_dqs_en_phase(i, 0);
3252 #if IO_DLL_CHAIN_LENGTH == 6
3253 scc_mgr_set_dqdqs_output_phase(i, 6);
3255 scc_mgr_set_dqdqs_output_phase(i, 7);
3260 * Write data arrives to the I/O two cycles before write
3261 * latency is reached (720 deg).
3262 * -> due to bit-slip in a/c bus
3263 * -> to allow board skew where dqs is longer than ck
3264 * -> how often can this happen!?
3265 * -> can claim back some ptaps for high freq
3266 * support if we can relax this, but i digress...
3268 * The write_clk leads mem_ck by 90 deg
3269 * The minimum ptap of the OPA is 180 deg
3270 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3271 * The write_clk is always delayed by 2 ptaps
3273 * Hence, to make DQS aligned to CK, we need to delay
3275 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3277 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3278 * gives us the number of ptaps, which simplies to:
3280 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3282 scc_mgr_set_dqdqs_output_phase(i,
3283 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3285 writel(0xff, &sdr_scc_mgr->dqs_ena);
3286 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3288 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3289 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3290 SCC_MGR_GROUP_COUNTER_OFFSET);
3292 writel(0xff, &sdr_scc_mgr->dq_ena);
3293 writel(0xff, &sdr_scc_mgr->dm_ena);
3294 writel(0, &sdr_scc_mgr->update);
3297 /* Compensate for simulation model behaviour */
3298 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3299 scc_mgr_set_dqs_bus_in_delay(i, 10);
3300 scc_mgr_load_dqs(i);
3302 writel(0, &sdr_scc_mgr->update);
3305 * ArriaV has hard FIFOs that can only be initialized by incrementing
3308 vfifo_offset = CALIB_VFIFO_OFFSET;
3309 for (j = 0; j < vfifo_offset; j++)
3310 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3311 writel(0, &phy_mgr_cmd->fifo_reset);
3314 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3315 * setting from generation-time constant.
3317 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3318 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3322 * mem_calibrate() - Memory calibration entry point.
3324 * Perform memory calibration.
3326 static uint32_t mem_calibrate(void)
3329 uint32_t rank_bgn, sr;
3330 uint32_t write_group, write_test_bgn;
3331 uint32_t read_group, read_test_bgn;
3332 uint32_t run_groups, current_run;
3333 uint32_t failing_groups = 0;
3334 uint32_t group_failed = 0;
3336 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3337 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3339 debug("%s:%d\n", __func__, __LINE__);
3341 /* Initialize the data settings */
3342 gbl->error_substage = CAL_SUBSTAGE_NIL;
3343 gbl->error_stage = CAL_STAGE_NIL;
3344 gbl->error_group = 0xff;
3348 /* Initialize WLAT and RLAT. */
3351 /* Initialize bit slips. */
3352 mem_precharge_and_activate();
3354 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3355 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3356 SCC_MGR_GROUP_COUNTER_OFFSET);
3357 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3359 scc_mgr_set_hhp_extras();
3361 scc_set_bypass_mode(i);
3364 /* Calibration is skipped. */
3365 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3367 * Set VFIFO and LFIFO to instant-on settings in skip
3370 mem_skip_calibrate();
3373 * Do not remove this line as it makes sure all of our
3374 * decisions have been applied.
3376 writel(0, &sdr_scc_mgr->update);
3380 /* Calibration is not skipped. */
3381 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3383 * Zero all delay chain/phase settings for all
3384 * groups and all shadow register sets.
3388 run_groups = ~param->skip_groups;
3390 for (write_group = 0, write_test_bgn = 0; write_group
3391 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3392 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3394 /* Initialize the group failure */
3397 current_run = run_groups & ((1 <<
3398 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3399 run_groups = run_groups >>
3400 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3402 if (current_run == 0)
3405 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3406 SCC_MGR_GROUP_COUNTER_OFFSET);
3407 scc_mgr_zero_group(write_group, 0);
3409 for (read_group = write_group * rwdqs_ratio,
3411 read_group < (write_group + 1) * rwdqs_ratio;
3413 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3414 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3417 /* Calibrate the VFIFO */
3418 if (rw_mgr_mem_calibrate_vfifo(read_group,
3422 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3425 /* The group failed, we're done. */
3429 /* Calibrate the output side */
3430 for (rank_bgn = 0, sr = 0;
3431 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3432 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3433 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3436 /* Not needed in quick mode! */
3437 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3441 * Determine if this set of ranks
3442 * should be skipped entirely.
3444 if (param->skip_shadow_regs[sr])
3447 /* Calibrate WRITEs */
3448 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3449 write_group, write_test_bgn))
3453 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3457 /* Some group failed, we're done. */
3461 for (read_group = write_group * rwdqs_ratio,
3463 read_group < (write_group + 1) * rwdqs_ratio;
3465 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3466 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3469 if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
3473 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3476 /* The group failed, we're done. */
3480 /* No group failed, continue as usual. */
3483 grp_failed: /* A group failed, increment the counter. */
3488 * USER If there are any failing groups then report
3491 if (failing_groups != 0)
3494 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3498 * If we're skipping groups as part of debug,
3499 * don't calibrate LFIFO.
3501 if (param->skip_groups != 0)
3504 /* Calibrate the LFIFO */
3505 if (!rw_mgr_mem_calibrate_lfifo())
3510 * Do not remove this line as it makes sure all of our decisions
3511 * have been applied.
3513 writel(0, &sdr_scc_mgr->update);
3518 * run_mem_calibrate() - Perform memory calibration
3520 * This function triggers the entire memory calibration procedure.
3522 static int run_mem_calibrate(void)
3526 debug("%s:%d\n", __func__, __LINE__);
3528 /* Reset pass/fail status shown on afi_cal_success/fail */
3529 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3531 /* Stop tracking manager. */
3532 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3534 phy_mgr_initialize();
3535 rw_mgr_mem_initialize();
3537 /* Perform the actual memory calibration. */
3538 pass = mem_calibrate();
3540 mem_precharge_and_activate();
3541 writel(0, &phy_mgr_cmd->fifo_reset);
3544 rw_mgr_mem_handoff();
3546 * In Hard PHY this is a 2-bit control:
3548 * 1: DDIO Mux Select
3550 writel(0x2, &phy_mgr_cfg->mux_sel);
3552 /* Start tracking manager. */
3553 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3559 * debug_mem_calibrate() - Report result of memory calibration
3560 * @pass: Value indicating whether calibration passed or failed
3562 * This function reports the results of the memory calibration
3563 * and writes debug information into the register file.
3565 static void debug_mem_calibrate(int pass)
3567 uint32_t debug_info;
3570 printf("%s: CALIBRATION PASSED\n", __FILE__);
3575 if (gbl->fom_in > 0xff)
3578 if (gbl->fom_out > 0xff)
3579 gbl->fom_out = 0xff;
3581 /* Update the FOM in the register file */
3582 debug_info = gbl->fom_in;
3583 debug_info |= gbl->fom_out << 8;
3584 writel(debug_info, &sdr_reg_file->fom);
3586 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3587 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3589 printf("%s: CALIBRATION FAILED\n", __FILE__);
3591 debug_info = gbl->error_stage;
3592 debug_info |= gbl->error_substage << 8;
3593 debug_info |= gbl->error_group << 16;
3595 writel(debug_info, &sdr_reg_file->failing_stage);
3596 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3597 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3599 /* Update the failing group/stage in the register file */
3600 debug_info = gbl->error_stage;
3601 debug_info |= gbl->error_substage << 8;
3602 debug_info |= gbl->error_group << 16;
3603 writel(debug_info, &sdr_reg_file->failing_stage);
3606 printf("%s: Calibration complete\n", __FILE__);
3610 * hc_initialize_rom_data() - Initialize ROM data
3612 * Initialize ROM data.
3614 static void hc_initialize_rom_data(void)
3618 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3619 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3620 writel(inst_rom_init[i], addr + (i << 2));
3622 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3623 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3624 writel(ac_rom_init[i], addr + (i << 2));
3628 * initialize_reg_file() - Initialize SDR register file
3630 * Initialize SDR register file.
3632 static void initialize_reg_file(void)
3634 /* Initialize the register file with the correct data */
3635 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3636 writel(0, &sdr_reg_file->debug_data_addr);
3637 writel(0, &sdr_reg_file->cur_stage);
3638 writel(0, &sdr_reg_file->fom);
3639 writel(0, &sdr_reg_file->failing_stage);
3640 writel(0, &sdr_reg_file->debug1);
3641 writel(0, &sdr_reg_file->debug2);
3645 * initialize_hps_phy() - Initialize HPS PHY
3647 * Initialize HPS PHY.
3649 static void initialize_hps_phy(void)
3653 * Tracking also gets configured here because it's in the
3656 uint32_t trk_sample_count = 7500;
3657 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3659 * Format is number of outer loops in the 16 MSB, sample
3664 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3666 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3667 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3669 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3671 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3672 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3674 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3675 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3677 writel(reg, &sdr_ctrl->phy_ctrl0);
3680 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3682 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3683 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3684 trk_long_idle_sample_count);
3685 writel(reg, &sdr_ctrl->phy_ctrl1);
3688 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3689 trk_long_idle_sample_count >>
3690 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3691 writel(reg, &sdr_ctrl->phy_ctrl2);
3695 * initialize_tracking() - Initialize tracking
3697 * Initialize the register file with usable initial data.
3699 static void initialize_tracking(void)
3702 * Initialize the register file with the correct data.
3703 * Compute usable version of value in case we skip full
3704 * computation later.
3706 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3707 &sdr_reg_file->dtaps_per_ptap);
3709 /* trk_sample_count */
3710 writel(7500, &sdr_reg_file->trk_sample_count);
3712 /* longidle outer loop [15:0] */
3713 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3716 * longidle sample count [31:24]
3717 * trfc, worst case of 933Mhz 4Gb [23:16]
3718 * trcd, worst case [15:8]
3721 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3722 &sdr_reg_file->delays);
3725 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3726 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3727 &sdr_reg_file->trk_rw_mgr_addr);
3729 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3730 &sdr_reg_file->trk_read_dqs_width);
3733 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3734 &sdr_reg_file->trk_rfsh);
3737 int sdram_calibration_full(void)
3739 struct param_type my_param;
3740 struct gbl_type my_gbl;
3743 memset(&my_param, 0, sizeof(my_param));
3744 memset(&my_gbl, 0, sizeof(my_gbl));
3749 /* Set the calibration enabled by default */
3750 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3752 * Only sweep all groups (regardless of fail state) by default
3753 * Set enabled read test by default.
3755 #if DISABLE_GUARANTEED_READ
3756 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3758 /* Initialize the register file */
3759 initialize_reg_file();
3761 /* Initialize any PHY CSR */
3762 initialize_hps_phy();
3764 scc_mgr_initialize();
3766 initialize_tracking();
3768 printf("%s: Preparing to start memory calibration\n", __FILE__);
3770 debug("%s:%d\n", __func__, __LINE__);
3771 debug_cond(DLEVEL == 1,
3772 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3773 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3774 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3775 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3776 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3777 debug_cond(DLEVEL == 1,
3778 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3779 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3780 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3781 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3782 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3783 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3784 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3785 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3786 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3787 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3788 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3789 IO_IO_OUT2_DELAY_MAX);
3790 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3791 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3793 hc_initialize_rom_data();
3795 /* update info for sims */
3796 reg_file_set_stage(CAL_STAGE_NIL);
3797 reg_file_set_group(0);
3800 * Load global needed for those actions that require
3801 * some dynamic calibration support.
3803 dyn_calib_steps = STATIC_CALIB_STEPS;
3805 * Load global to allow dynamic selection of delay loop settings
3806 * based on calibration mode.
3808 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3809 skip_delay_mask = 0xff;
3811 skip_delay_mask = 0x0;
3813 pass = run_mem_calibrate();
3814 debug_mem_calibrate(pass);