1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
18 #include "sdram_soc64.h"
20 #include <asm/arch/firewall.h>
21 #include <asm/arch/system_manager.h>
22 #include <asm/arch/reset_manager.h>
23 #include <asm/cache.h>
25 #include <dm/device_compat.h>
26 #include <linux/sizes.h>
28 #define PGTABLE_OFF 0x4000
30 u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
32 return readl(plat->iomhc + reg);
35 u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
37 return readl(plat->hmc + reg);
40 u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
43 return writel(data, plat->hmc + reg);
46 u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
49 return writel(data, plat->ddr_sch + reg);
52 int emif_clear(struct altera_sdram_platdata *plat)
54 hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
56 return wait_for_bit_le32((const void *)(plat->hmc +
58 DDR_HMC_RSTHANDSHAKE_MASK,
62 int emif_reset(struct altera_sdram_platdata *plat)
66 c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
67 s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
69 debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
70 c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
71 hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
72 hmc_readl(plat, DRAMSTS));
74 if (s2c && emif_clear(plat)) {
75 printf("DDR: emif_clear() failed\n");
79 debug("DDR: Triggerring emif reset\n");
80 hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
82 /* if seq2core[3] = 0, we are good */
83 ret = wait_for_bit_le32((const void *)(plat->hmc +
85 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
88 printf("DDR: failed to get ack from EMIF\n");
92 ret = emif_clear(plat);
94 printf("DDR: emif_clear() failed\n");
98 debug("DDR: %s triggered successly\n", __func__);
102 int poll_hmc_clock_status(void)
104 return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
105 SYSMGR_SOC64_HMC_CLK),
106 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
109 void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
113 if (addr % CONFIG_SYS_CACHELINE_SIZE) {
114 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
119 if (size % CONFIG_SYS_CACHELINE_SIZE) {
120 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
125 /* Use DC ZVA instruction to clear memory to zeros by a cache line */
126 for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
127 asm volatile("dc zva, %0"
131 addr += CONFIG_SYS_CACHELINE_SIZE;
135 void sdram_init_ecc_bits(struct bd_info *bd)
137 phys_size_t size, size_init;
138 phys_addr_t start_addr;
140 unsigned int start = get_timer(0);
144 start_addr = bd->bi_dram[0].start;
145 size = bd->bi_dram[0].size;
147 /* Initialize small block for page table */
148 memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
149 gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
150 gd->arch.tlb_size = PGTABLE_SIZE;
151 start_addr += PGTABLE_SIZE + PGTABLE_OFF;
152 size -= (PGTABLE_OFF + PGTABLE_SIZE);
157 size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
158 sdram_clear_mem(start_addr, size_init);
160 start_addr += size_init;
165 if (bank >= CONFIG_NR_DRAM_BANKS)
168 start_addr = bd->bi_dram[bank].start;
169 size = bd->bi_dram[bank].size;
175 printf("SDRAM-ECC: Initialized success with %d ms\n",
176 (unsigned int)get_timer(start));
179 void sdram_size_check(struct bd_info *bd)
181 phys_size_t total_ram_check = 0;
182 phys_size_t ram_check = 0;
183 phys_addr_t start = 0;
186 /* Sanity check ensure correct SDRAM size specified */
187 debug("DDR: Running SDRAM size sanity check\n");
189 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
190 start = bd->bi_dram[bank].start;
191 while (ram_check < bd->bi_dram[bank].size) {
192 ram_check += get_ram_size((void *)(start + ram_check),
195 total_ram_check += ram_check;
199 /* If the ram_size is 2GB smaller, we can assume the IO space is
200 * not mapped in. gd->ram_size is the actual size of the dram
201 * not the accessible size.
203 if (total_ram_check != gd->ram_size) {
204 puts("DDR: SDRAM size check failed!\n");
208 debug("DDR: SDRAM size check passed!\n");
212 * sdram_calculate_size() - Calculate SDRAM size
214 * Calculate SDRAM device size based on SDRAM controller parameters.
215 * Size is specified in bytes.
217 phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
219 u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
221 phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
222 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
223 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
224 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
225 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
227 size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
228 DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
233 static int altera_sdram_of_to_plat(struct udevice *dev)
235 struct altera_sdram_platdata *plat = dev->plat;
238 addr = dev_read_addr_index(dev, 0);
239 if (addr == FDT_ADDR_T_NONE)
241 plat->ddr_sch = (void __iomem *)addr;
243 addr = dev_read_addr_index(dev, 1);
244 if (addr == FDT_ADDR_T_NONE)
246 plat->iomhc = (void __iomem *)addr;
248 addr = dev_read_addr_index(dev, 2);
249 if (addr == FDT_ADDR_T_NONE)
251 plat->hmc = (void __iomem *)addr;
256 static int altera_sdram_probe(struct udevice *dev)
259 struct altera_sdram_priv *priv = dev_get_priv(dev);
261 ret = reset_get_bulk(dev, &priv->resets);
263 dev_err(dev, "Can't get reset: %d\n", ret);
266 reset_deassert_bulk(&priv->resets);
268 if (sdram_mmr_init_full(dev) != 0) {
269 puts("SDRAM init failed.\n");
276 reset_release_bulk(&priv->resets);
280 static int altera_sdram_get_info(struct udevice *dev,
281 struct ram_info *info)
283 struct altera_sdram_priv *priv = dev_get_priv(dev);
285 info->base = priv->info.base;
286 info->size = priv->info.size;
291 static struct ram_ops altera_sdram_ops = {
292 .get_info = altera_sdram_get_info,
295 static const struct udevice_id altera_sdram_ids[] = {
296 { .compatible = "altr,sdr-ctl-s10" },
297 { .compatible = "intel,sdr-ctl-agilex" },
301 U_BOOT_DRIVER(altera_sdram) = {
302 .name = "altr_sdr_ctl",
304 .of_match = altera_sdram_ids,
305 .ops = &altera_sdram_ops,
306 .of_to_plat = altera_sdram_of_to_plat,
307 .plat_auto = sizeof(struct altera_sdram_platdata),
308 .probe = altera_sdram_probe,
309 .priv_auto = sizeof(struct altera_sdram_priv),