drivers/ddr/altera/sdram_soc64.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <hang.h>
  14 #include <ram.h>
  15 #include <reset.h>
  16 #include "sdram_soc64.h"
  17 #include <wait_bit.h>
  18 #include <asm/arch/firewall.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/arch/reset_manager.h>
  21 #include <asm/cache.h>
  22 #include <asm/io.h>
  23 #include <dm/device_compat.h>
  24 #include <linux/sizes.h>
  25
  26 #define PGTABLE_OFF     0x4000
  27
  28 u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  29 {
  30         return readl(plat->iomhc + reg);
  31 }
  32
  33 u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  34 {
  35         return readl(plat->hmc + reg);
  36 }
  37
  38 u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  39                    u32 data, u32 reg)
  40 {
  41         return writel(data, plat->hmc + reg);
  42 }
  43
  44 u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  45                    u32 reg)
  46 {
  47         return writel(data, plat->ddr_sch + reg);
  48 }
  49
  50 int emif_clear(struct altera_sdram_platdata *plat)
  51 {
  52         hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
  53
  54         return wait_for_bit_le32((const void *)(plat->hmc +
  55                                  RSTHANDSHAKESTAT),
  56                                  DDR_HMC_RSTHANDSHAKE_MASK,
  57                                  false, 1000, false);
  58 }
  59
  60 int emif_reset(struct altera_sdram_platdata *plat)
  61 {
  62         u32 c2s, s2c, ret;
  63
  64         c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
  65         s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
  66
  67         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  68               c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
  69               hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
  70               hmc_readl(plat, DRAMSTS));
  71
  72         if (s2c && emif_clear(plat)) {
  73                 printf("DDR: emif_clear() failed\n");
  74                 return -1;
  75         }
  76
  77         debug("DDR: Triggerring emif reset\n");
  78         hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
  79
  80         /* if seq2core[3] = 0, we are good */
  81         ret = wait_for_bit_le32((const void *)(plat->hmc +
  82                                  RSTHANDSHAKESTAT),
  83                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
  84                                  false, 1000, false);
  85         if (ret) {
  86                 printf("DDR: failed to get ack from EMIF\n");
  87                 return ret;
  88         }
  89
  90         ret = emif_clear(plat);
  91         if (ret) {
  92                 printf("DDR: emif_clear() failed\n");
  93                 return ret;
  94         }
  95
  96         debug("DDR: %s triggered successly\n", __func__);
  97         return 0;
  98 }
  99
 100 int poll_hmc_clock_status(void)
 101 {
 102         return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
 103                                  SYSMGR_SOC64_HMC_CLK),
 104                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 105 }
 106
 107 void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
 108 {
 109         phys_size_t i;
 110
 111         if (addr % CONFIG_SYS_CACHELINE_SIZE) {
 112                 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
 113                        addr);
 114                 hang();
 115         }
 116
 117         if (size % CONFIG_SYS_CACHELINE_SIZE) {
 118                 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
 119                        size);
 120                 hang();
 121         }
 122
 123         /* Use DC ZVA instruction to clear memory to zeros by a cache line */
 124         for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
 125                 asm volatile("dc zva, %0"
 126                      :
 127                      : "r"(addr)
 128                      : "memory");
 129                 addr += CONFIG_SYS_CACHELINE_SIZE;
 130         }
 131 }
 132
 133 void sdram_init_ecc_bits(bd_t *bd)
 134 {
 135         phys_size_t size, size_init;
 136         phys_addr_t start_addr;
 137         int bank = 0;
 138         unsigned int start = get_timer(0);
 139
 140         icache_enable();
 141
 142         start_addr = bd->bi_dram[0].start;
 143         size = bd->bi_dram[0].size;
 144
 145         /* Initialize small block for page table */
 146         memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
 147         gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
 148         gd->arch.tlb_size = PGTABLE_SIZE;
 149         start_addr += PGTABLE_SIZE + PGTABLE_OFF;
 150         size -= (PGTABLE_OFF + PGTABLE_SIZE);
 151         dcache_enable();
 152
 153         while (1) {
 154                 while (size) {
 155                         size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
 156                         sdram_clear_mem(start_addr, size_init);
 157                         size -= size_init;
 158                         start_addr += size_init;
 159                         WATCHDOG_RESET();
 160                 }
 161
 162                 bank++;
 163                 if (bank >= CONFIG_NR_DRAM_BANKS)
 164                         break;
 165
 166                 start_addr = bd->bi_dram[bank].start;
 167                 size = bd->bi_dram[bank].size;
 168         }
 169
 170         dcache_disable();
 171         icache_disable();
 172
 173         printf("SDRAM-ECC: Initialized success with %d ms\n",
 174                (unsigned int)get_timer(start));
 175 }
 176
 177 void sdram_size_check(bd_t *bd)
 178 {
 179         phys_size_t total_ram_check = 0;
 180         phys_size_t ram_check = 0;
 181         phys_addr_t start = 0;
 182         int bank;
 183
 184         /* Sanity check ensure correct SDRAM size specified */
 185         debug("DDR: Running SDRAM size sanity check\n");
 186
 187         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 188                 start = bd->bi_dram[bank].start;
 189                 while (ram_check < bd->bi_dram[bank].size) {
 190                         ram_check += get_ram_size((void *)(start + ram_check),
 191                                                  (phys_size_t)SZ_1G);
 192                 }
 193                 total_ram_check += ram_check;
 194                 ram_check = 0;
 195         }
 196
 197         /* If the ram_size is 2GB smaller, we can assume the IO space is
 198          * not mapped in.  gd->ram_size is the actual size of the dram
 199          * not the accessible size.
 200          */
 201         if (total_ram_check != gd->ram_size) {
 202                 puts("DDR: SDRAM size check failed!\n");
 203                 hang();
 204         }
 205
 206         debug("DDR: SDRAM size check passed!\n");
 207 }
 208
 209 /**
 210  * sdram_calculate_size() - Calculate SDRAM size
 211  *
 212  * Calculate SDRAM device size based on SDRAM controller parameters.
 213  * Size is specified in bytes.
 214  */
 215 phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
 216 {
 217         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 218
 219         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 220                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 221                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 222                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 223                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 224
 225         size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
 226                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 227
 228         return size;
 229 }
 230
 231 static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
 232 {
 233         struct altera_sdram_platdata *plat = dev->platdata;
 234         fdt_addr_t addr;
 235
 236         addr = dev_read_addr_index(dev, 0);
 237         if (addr == FDT_ADDR_T_NONE)
 238                 return -EINVAL;
 239         plat->ddr_sch = (void __iomem *)addr;
 240
 241         addr = dev_read_addr_index(dev, 1);
 242         if (addr == FDT_ADDR_T_NONE)
 243                 return -EINVAL;
 244         plat->iomhc = (void __iomem *)addr;
 245
 246         addr = dev_read_addr_index(dev, 2);
 247         if (addr == FDT_ADDR_T_NONE)
 248                 return -EINVAL;
 249         plat->hmc = (void __iomem *)addr;
 250
 251         return 0;
 252 }
 253
 254 static int altera_sdram_probe(struct udevice *dev)
 255 {
 256         int ret;
 257         struct altera_sdram_priv *priv = dev_get_priv(dev);
 258
 259         ret = reset_get_bulk(dev, &priv->resets);
 260         if (ret) {
 261                 dev_err(dev, "Can't get reset: %d\n", ret);
 262                 return -ENODEV;
 263         }
 264         reset_deassert_bulk(&priv->resets);
 265
 266         if (sdram_mmr_init_full(dev) != 0) {
 267                 puts("SDRAM init failed.\n");
 268                 goto failed;
 269         }
 270
 271         return 0;
 272
 273 failed:
 274         reset_release_bulk(&priv->resets);
 275         return -ENODEV;
 276 }
 277
 278 static int altera_sdram_get_info(struct udevice *dev,
 279                                  struct ram_info *info)
 280 {
 281         struct altera_sdram_priv *priv = dev_get_priv(dev);
 282
 283         info->base = priv->info.base;
 284         info->size = priv->info.size;
 285
 286         return 0;
 287 }
 288
 289 static struct ram_ops altera_sdram_ops = {
 290         .get_info = altera_sdram_get_info,
 291 };
 292
 293 static const struct udevice_id altera_sdram_ids[] = {
 294         { .compatible = "altr,sdr-ctl-s10" },
 295         { .compatible = "intel,sdr-ctl-agilex" },
 296         { /* sentinel */ }
 297 };
 298
 299 U_BOOT_DRIVER(altera_sdram) = {
 300         .name = "altr_sdr_ctl",
 301         .id = UCLASS_RAM,
 302         .of_match = altera_sdram_ids,
 303         .ops = &altera_sdram_ops,
 304         .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
 305         .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
 306         .probe = altera_sdram_probe,
 307         .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
 308 };