drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <ram.h>
  14 #include <reset.h>
  15 #include "sdram_s10.h"
  16 #include <wait_bit.h>
  17 #include <asm/arch/firewall.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/io.h>
  20 #include <linux/sizes.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  25
  26 /* The followring are the supported configurations */
  27 u32 ddr_config[] = {
  28         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  29         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  30         DDR_CONFIG(0, 3, 10, 12),
  31         DDR_CONFIG(0, 3,  9, 13),
  32         DDR_CONFIG(0, 3, 10, 13),
  33         DDR_CONFIG(0, 3,  9, 14),
  34         DDR_CONFIG(0, 3, 10, 14),
  35         DDR_CONFIG(0, 3, 10, 15),
  36         DDR_CONFIG(0, 3, 11, 14),
  37         DDR_CONFIG(0, 3, 11, 15),
  38         DDR_CONFIG(0, 3, 10, 16),
  39         DDR_CONFIG(0, 3, 11, 16),
  40         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  41         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  42         DDR_CONFIG(1, 3, 10, 14),
  43         DDR_CONFIG(1, 4, 10, 14),
  44         DDR_CONFIG(1, 3, 10, 15),
  45         DDR_CONFIG(1, 4, 10, 15),
  46         DDR_CONFIG(1, 3, 10, 16),
  47         DDR_CONFIG(1, 4, 10, 16),
  48         DDR_CONFIG(1, 3, 10, 17),
  49         DDR_CONFIG(1, 4, 10, 17),
  50 };
  51
  52 int match_ddr_conf(u32 ddr_conf)
  53 {
  54         int i;
  55
  56         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  57                 if (ddr_conf == ddr_config[i])
  58                         return i;
  59         }
  60         return 0;
  61 }
  62
  63 /**
  64  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  65  *
  66  * Initialize the SDRAM MMR.
  67  */
  68 int sdram_mmr_init_full(struct udevice *dev)
  69 {
  70         struct altera_sdram_platdata *plat = dev->platdata;
  71         struct altera_sdram_priv *priv = dev_get_priv(dev);
  72         u32 update_value, io48_value, ddrioctl;
  73         u32 i;
  74         int ret;
  75         phys_size_t hw_size;
  76         bd_t bd = {0};
  77
  78         /* Enable access to DDR from CPU master */
  79         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
  80                      CCU_ADBASE_DI_MASK);
  81         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
  82                      CCU_ADBASE_DI_MASK);
  83         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
  84                      CCU_ADBASE_DI_MASK);
  85         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
  86                      CCU_ADBASE_DI_MASK);
  87         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
  88                      CCU_ADBASE_DI_MASK);
  89         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
  90                      CCU_ADBASE_DI_MASK);
  91         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
  92                      CCU_ADBASE_DI_MASK);
  93
  94         /* Enable access to DDR from IO master */
  95         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
  96                      CCU_ADBASE_DI_MASK);
  97         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
  98                      CCU_ADBASE_DI_MASK);
  99         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 100                      CCU_ADBASE_DI_MASK);
 101         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 102                      CCU_ADBASE_DI_MASK);
 103         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 104                      CCU_ADBASE_DI_MASK);
 105         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 106                      CCU_ADBASE_DI_MASK);
 107
 108         /* Enable access to DDR from TCU */
 109         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
 110                      CCU_ADBASE_DI_MASK);
 111         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
 112                      CCU_ADBASE_DI_MASK);
 113         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
 114                      CCU_ADBASE_DI_MASK);
 115         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
 116                      CCU_ADBASE_DI_MASK);
 117         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
 118                      CCU_ADBASE_DI_MASK);
 119         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
 120                      CCU_ADBASE_DI_MASK);
 121
 122         /* this enables nonsecure access to DDR */
 123         /* mpuregion0addr_limit */
 124         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 125         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 126
 127         /* nonmpuregion0addr_limit */
 128         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 129                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 130         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 131
 132         /* Enable mpuregion0enable and nonmpuregion0enable */
 133         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 134                               FW_MPU_DDR_SCR_EN_SET);
 135
 136         /* Ensure HMC clock is running */
 137         if (poll_hmc_clock_status()) {
 138                 puts("DDR: Error as HMC clock not running\n");
 139                 return -1;
 140         }
 141
 142         /* Try 3 times to do a calibration */
 143         for (i = 0; i < 3; i++) {
 144                 ret = wait_for_bit_le32((const void *)(plat->hmc +
 145                                         DDRCALSTAT),
 146                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 147                                         false);
 148                 if (!ret)
 149                         break;
 150
 151                 emif_reset(plat);
 152         }
 153
 154         if (ret) {
 155                 puts("DDR: Error as SDRAM calibration failed\n");
 156                 return -1;
 157         }
 158         debug("DDR: Calibration success\n");
 159
 160         u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
 161         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 162         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 163         u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
 164         u32 caltim0 = hmc_readl(plat, CALTIMING0);
 165         u32 caltim1 = hmc_readl(plat, CALTIMING1);
 166         u32 caltim2 = hmc_readl(plat, CALTIMING2);
 167         u32 caltim3 = hmc_readl(plat, CALTIMING3);
 168         u32 caltim4 = hmc_readl(plat, CALTIMING4);
 169         u32 caltim9 = hmc_readl(plat, CALTIMING9);
 170
 171         /*
 172          * Configure the DDR IO size [0xFFCFB008]
 173          * niosreserve0: Used to indicate DDR width &
 174          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 175          *      bit[8]   = 1 if user-mode OCT is present
 176          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 177          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 178          * niosreserve1: IP ADCDS version encoded as 16 bit value
 179          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 180          *                          3=EAP, 4-6 are reserved)
 181          *      bit[5:3] = Service Pack # (e.g. 1)
 182          *      bit[9:6] = Minor Release #
 183          *      bit[14:10] = Major Release #
 184          */
 185         update_value = hmc_readl(plat, NIOSRESERVED0);
 186         hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
 187         ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
 188
 189         /* enable HPS interface to HMC */
 190         hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 191
 192         /* Set the DDR Configuration */
 193         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 194                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 195                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 196                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 197                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 198
 199         update_value = match_ddr_conf(io48_value);
 200         if (update_value)
 201                 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
 202
 203         /* Configure HMC dramaddrw */
 204         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
 205
 206         /*
 207          * Configure DDR timing
 208          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 209          *  WRTOMISS = WL + tWR + tRP + tRCD and
 210          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 211          *  First part of equation is in memory clock units so divide by 2
 212          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 213          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 214          */
 215         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 216
 217         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 218                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 219                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 220                        (burst_len >> 2);
 221         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 222                        (burst_len >> 1)) >> 1) -
 223                       /* Up to here was in memory cycles so divide by 2 */
 224                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 225                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 226                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 227
 228         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 229                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 230                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 231                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 232                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 233                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 234                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 235                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 236                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 237                         (((ddrioctl == 1) ? 1 : 0) <<
 238                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 239                         DDR_SCH_DDRTIMING);
 240
 241         /* Configure DDR mode [precharge = 0] */
 242         ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
 243                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 244                         DDR_SCH_DDRMODE);
 245
 246         /* Configure the read latency */
 247         ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 248                         DDR_READ_LATENCY_DELAY,
 249                         DDR_SCH_READ_LATENCY);
 250
 251         /*
 252          * Configuring timing values concerning activate commands
 253          * [FAWBANK alway 1 because always 4 bank DDR]
 254          */
 255         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 256                          DDR_SCH_ACTIVATE_RRD_OFF) |
 257                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 258                          DDR_SCH_ACTIVATE_FAW_OFF) |
 259                         (DDR_ACTIVATE_FAWBANK <<
 260                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 261                         DDR_SCH_ACTIVATE);
 262
 263         /*
 264          * Configuring timing values concerning device to device data bus
 265          * ownership change
 266          */
 267         ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 268                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 269                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 270                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 271                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 272                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 273                         DDR_SCH_DEVTODEV);
 274
 275         /* assigning the SDRAM size */
 276         unsigned long long size = sdram_calculate_size(plat);
 277         /* If the size is invalid, use default Config size */
 278         if (size <= 0)
 279                 hw_size = PHYS_SDRAM_1_SIZE;
 280         else
 281                 hw_size = size;
 282
 283         /* Get bank configuration from devicetree */
 284         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 285                                      (phys_size_t *)&gd->ram_size, &bd);
 286         if (ret) {
 287                 puts("DDR: Failed to decode memory node\n");
 288                 return -1;
 289         }
 290
 291         if (gd->ram_size != hw_size)
 292                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 293
 294         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 295
 296         /* Enable or disable the SDRAM ECC */
 297         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 298                 setbits_le32(plat->hmc + ECCCTRL1,
 299                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 300                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 301                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 302                 clrbits_le32(plat->hmc + ECCCTRL1,
 303                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 304                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 305                 setbits_le32(plat->hmc + ECCCTRL2,
 306                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 307                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 308                 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 309
 310                 /* Initialize memory content if not from warm reset */
 311                 if (!cpu_has_been_warmreset())
 312                         sdram_init_ecc_bits(&bd);
 313         } else {
 314                 clrbits_le32(plat->hmc + ECCCTRL1,
 315                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 316                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 317                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 318                 clrbits_le32(plat->hmc + ECCCTRL2,
 319                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 320                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 321         }
 322
 323         /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
 324         writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 325
 326         sdram_size_check(&bd);
 327
 328         priv->info.base = bd.bi_dram[0].start;
 329         priv->info.size = gd->ram_size;
 330
 331         debug("DDR: HMC init success\n");
 332         return 0;
 333 }
 334