drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <div64.h>
  10 #include <fdtdec.h>
  11 #include <asm/io.h>
  12 #include <wait_bit.h>
  13 #include <asm/arch/firewall_s10.h>
  14 #include <asm/arch/sdram_s10.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <linux/sizes.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static const struct socfpga_system_manager *sysmgr_regs =
  22                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  23
  24 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  25
  26 /* The followring are the supported configurations */
  27 u32 ddr_config[] = {
  28         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  29         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  30         DDR_CONFIG(0, 3, 10, 12),
  31         DDR_CONFIG(0, 3,  9, 13),
  32         DDR_CONFIG(0, 3, 10, 13),
  33         DDR_CONFIG(0, 3,  9, 14),
  34         DDR_CONFIG(0, 3, 10, 14),
  35         DDR_CONFIG(0, 3, 10, 15),
  36         DDR_CONFIG(0, 3, 11, 14),
  37         DDR_CONFIG(0, 3, 11, 15),
  38         DDR_CONFIG(0, 3, 10, 16),
  39         DDR_CONFIG(0, 3, 11, 16),
  40         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  41         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  42         DDR_CONFIG(1, 3, 10, 14),
  43         DDR_CONFIG(1, 4, 10, 14),
  44         DDR_CONFIG(1, 3, 10, 15),
  45         DDR_CONFIG(1, 4, 10, 15),
  46         DDR_CONFIG(1, 3, 10, 16),
  47         DDR_CONFIG(1, 4, 10, 16),
  48         DDR_CONFIG(1, 3, 10, 17),
  49         DDR_CONFIG(1, 4, 10, 17),
  50 };
  51
  52 static u32 hmc_readl(u32 reg)
  53 {
  54         return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
  55 }
  56
  57 static u32 hmc_ecc_readl(u32 reg)
  58 {
  59         return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
  60 }
  61
  62 static u32 hmc_ecc_writel(u32 data, u32 reg)
  63 {
  64         return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
  65 }
  66
  67 static u32 ddr_sch_writel(u32 data, u32 reg)
  68 {
  69         return writel(data,
  70                       (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
  71 }
  72
  73 int match_ddr_conf(u32 ddr_conf)
  74 {
  75         int i;
  76
  77         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  78                 if (ddr_conf == ddr_config[i])
  79                         return i;
  80         }
  81         return 0;
  82 }
  83
  84 static int emif_clear(void)
  85 {
  86         hmc_ecc_writel(0, RSTHANDSHAKECTRL);
  87
  88         return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
  89                                  RSTHANDSHAKESTAT),
  90                                  DDR_HMC_RSTHANDSHAKE_MASK,
  91                                  false, 1000, false);
  92 }
  93
  94 static int emif_reset(void)
  95 {
  96         u32 c2s, s2c, ret;
  97
  98         c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
  99         s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
 100
 101         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 102               c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
 103               hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
 104
 105         if (s2c && emif_clear()) {
 106                 printf("DDR: emif_clear() failed\n");
 107                 return -1;
 108         }
 109
 110         debug("DDR: Triggerring emif reset\n");
 111         hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 112
 113         /* if seq2core[3] = 0, we are good */
 114         ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
 115                                  RSTHANDSHAKESTAT),
 116                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
 117                                  false, 1000, false);
 118         if (ret) {
 119                 printf("DDR: failed to get ack from EMIF\n");
 120                 return ret;
 121         }
 122
 123         ret = emif_clear();
 124         if (ret) {
 125                 printf("DDR: emif_clear() failed\n");
 126                 return ret;
 127         }
 128
 129         debug("DDR: %s triggered successly\n", __func__);
 130         return 0;
 131 }
 132
 133 static int poll_hmc_clock_status(void)
 134 {
 135         return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
 136                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 137 }
 138
 139 static void sdram_size_check(bd_t *bd)
 140 {
 141         phys_size_t total_ram_check = 0;
 142         phys_size_t ram_check = 0;
 143         phys_addr_t start = 0;
 144         int bank;
 145
 146         /* Sanity check ensure correct SDRAM size specified */
 147         debug("DDR: Running SDRAM size sanity check\n");
 148
 149         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 150                 start = bd->bi_dram[bank].start;
 151                 while (ram_check < bd->bi_dram[bank].size) {
 152                         ram_check += get_ram_size((void *)(start + ram_check),
 153                                                  (phys_size_t)SZ_1G);
 154                 }
 155                 total_ram_check += ram_check;
 156                 ram_check = 0;
 157         }
 158
 159         /* If the ram_size is 2GB smaller, we can assume the IO space is
 160          * not mapped in.  gd->ram_size is the actual size of the dram
 161          * not the accessible size.
 162          */
 163         if (total_ram_check != gd->ram_size) {
 164                 puts("DDR: SDRAM size check failed!\n");
 165                 hang();
 166         }
 167
 168         debug("DDR: SDRAM size check passed!\n");
 169 }
 170
 171 /**
 172  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 173  *
 174  * Initialize the SDRAM MMR.
 175  */
 176 int sdram_mmr_init_full(unsigned int unused)
 177 {
 178         u32 update_value, io48_value, ddrioctl;
 179         u32 i;
 180         int ret;
 181         phys_size_t hw_size;
 182         bd_t bd = {0};
 183
 184         /* Enable access to DDR from CPU master */
 185         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
 186                      CCU_ADBASE_DI_MASK);
 187         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
 188                      CCU_ADBASE_DI_MASK);
 189         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
 190                      CCU_ADBASE_DI_MASK);
 191         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
 192                      CCU_ADBASE_DI_MASK);
 193         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
 194                      CCU_ADBASE_DI_MASK);
 195         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
 196                      CCU_ADBASE_DI_MASK);
 197         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
 198                      CCU_ADBASE_DI_MASK);
 199
 200         /* Enable access to DDR from IO master */
 201         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
 202                      CCU_ADBASE_DI_MASK);
 203         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
 204                      CCU_ADBASE_DI_MASK);
 205         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 206                      CCU_ADBASE_DI_MASK);
 207         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 208                      CCU_ADBASE_DI_MASK);
 209         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 210                      CCU_ADBASE_DI_MASK);
 211         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 212                      CCU_ADBASE_DI_MASK);
 213
 214         /* this enables nonsecure access to DDR */
 215         /* mpuregion0addr_limit */
 216         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 217         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 218
 219         /* nonmpuregion0addr_limit */
 220         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 221                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 222         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 223
 224         /* Enable mpuregion0enable and nonmpuregion0enable */
 225         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 226                               FW_MPU_DDR_SCR_EN_SET);
 227
 228         /* Ensure HMC clock is running */
 229         if (poll_hmc_clock_status()) {
 230                 puts("DDR: Error as HMC clock not running\n");
 231                 return -1;
 232         }
 233
 234         /* release DDR scheduler from reset */
 235         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 236
 237         /* Try 3 times to do a calibration */
 238         for (i = 0; i < 3; i++) {
 239                 ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
 240                                         DDRCALSTAT),
 241                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 242                                         false);
 243                 if (!ret)
 244                         break;
 245
 246                 emif_reset();
 247         }
 248
 249         if (ret) {
 250                 puts("DDR: Error as SDRAM calibration failed\n");
 251                 return -1;
 252         }
 253         debug("DDR: Calibration success\n");
 254
 255         u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
 256         u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
 257         u32 dramaddrw = hmc_readl(DRAMADDRW);
 258         u32 dramtim0 = hmc_readl(DRAMTIMING0);
 259         u32 caltim0 = hmc_readl(CALTIMING0);
 260         u32 caltim1 = hmc_readl(CALTIMING1);
 261         u32 caltim2 = hmc_readl(CALTIMING2);
 262         u32 caltim3 = hmc_readl(CALTIMING3);
 263         u32 caltim4 = hmc_readl(CALTIMING4);
 264         u32 caltim9 = hmc_readl(CALTIMING9);
 265
 266         /*
 267          * Configure the DDR IO size [0xFFCFB008]
 268          * niosreserve0: Used to indicate DDR width &
 269          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 270          *      bit[8]   = 1 if user-mode OCT is present
 271          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 272          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 273          * niosreserve1: IP ADCDS version encoded as 16 bit value
 274          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 275          *                          3=EAP, 4-6 are reserved)
 276          *      bit[5:3] = Service Pack # (e.g. 1)
 277          *      bit[9:6] = Minor Release #
 278          *      bit[14:10] = Major Release #
 279          */
 280         update_value = hmc_readl(NIOSRESERVED0);
 281         hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
 282         ddrioctl = hmc_ecc_readl(DDRIOCTRL);
 283
 284         /* enable HPS interface to HMC */
 285         hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 286
 287         /* Set the DDR Configuration */
 288         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 289                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 290                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 291                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 292                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 293
 294         update_value = match_ddr_conf(io48_value);
 295         if (update_value)
 296                 ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
 297
 298         /* Configure HMC dramaddrw */
 299         hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
 300
 301         /*
 302          * Configure DDR timing
 303          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 304          *  WRTOMISS = WL + tWR + tRP + tRCD and
 305          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 306          *  First part of equation is in memory clock units so divide by 2
 307          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 308          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 309          */
 310         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 311
 312         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 313                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 314                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 315                        (burst_len >> 2);
 316         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 317                        (burst_len >> 1)) >> 1) -
 318                       /* Up to here was in memory cycles so divide by 2 */
 319                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 320                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 321                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 322
 323         ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 324                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 325                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 326                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 327                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 328                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 329                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 330                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 331                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 332                         (((ddrioctl == 1) ? 1 : 0) <<
 333                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 334                         DDR_SCH_DDRTIMING);
 335
 336         /* Configure DDR mode [precharge = 0] */
 337         ddr_sch_writel(((ddrioctl ? 0 : 1) <<
 338                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 339                         DDR_SCH_DDRMODE);
 340
 341         /* Configure the read latency */
 342         ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 343                         DDR_READ_LATENCY_DELAY,
 344                         DDR_SCH_READ_LATENCY);
 345
 346         /*
 347          * Configuring timing values concerning activate commands
 348          * [FAWBANK alway 1 because always 4 bank DDR]
 349          */
 350         ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 351                          DDR_SCH_ACTIVATE_RRD_OFF) |
 352                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 353                          DDR_SCH_ACTIVATE_FAW_OFF) |
 354                         (DDR_ACTIVATE_FAWBANK <<
 355                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 356                         DDR_SCH_ACTIVATE);
 357
 358         /*
 359          * Configuring timing values concerning device to device data bus
 360          * ownership change
 361          */
 362         ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 363                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 364                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 365                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 366                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 367                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 368                         DDR_SCH_DEVTODEV);
 369
 370         /* assigning the SDRAM size */
 371         unsigned long long size = sdram_calculate_size();
 372         /* If the size is invalid, use default Config size */
 373         if (size <= 0)
 374                 hw_size = PHYS_SDRAM_1_SIZE;
 375         else
 376                 hw_size = size;
 377
 378         /* Get bank configuration from devicetree */
 379         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 380                                      (phys_size_t *)&gd->ram_size, &bd);
 381         if (ret) {
 382                 puts("DDR: Failed to decode memory node\n");
 383                 return -1;
 384         }
 385
 386         if (gd->ram_size != hw_size)
 387                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 388
 389         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 390
 391         /* Enable or disable the SDRAM ECC */
 392         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 393                 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 394                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 395                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 396                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 397                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 398                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 399                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 400                 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 401                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 402                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 403         } else {
 404                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 405                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 406                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 407                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 408                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 409                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 410                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 411         }
 412
 413         sdram_size_check(&bd);
 414
 415         debug("DDR: HMC init success\n");
 416         return 0;
 417 }
 418
 419 /**
 420  * sdram_calculate_size() - Calculate SDRAM size
 421  *
 422  * Calculate SDRAM device size based on SDRAM controller parameters.
 423  * Size is specified in bytes.
 424  */
 425 phys_size_t sdram_calculate_size(void)
 426 {
 427         u32 dramaddrw = hmc_readl(DRAMADDRW);
 428
 429         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 430                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 431                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 432                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 433                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 434
 435         size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
 436                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 437
 438         return size;
 439 }