drivers/ddr/altera/sdram_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright Altera Corporation (C) 2014-2015
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <init.h>
  10 #include <ram.h>
  11 #include <reset.h>
  12 #include <watchdog.h>
  13 #include <asm/arch/fpga_manager.h>
  14 #include <asm/arch/reset_manager.h>
  15 #include <asm/arch/sdram.h>
  16 #include <asm/arch/system_manager.h>
  17 #include <asm/io.h>
  18
  19 #include "sequencer.h"
  20
  21 #ifdef CONFIG_SPL_BUILD
  22
  23 struct altera_gen5_sdram_priv {
  24         struct ram_info info;
  25 };
  26
  27 struct altera_gen5_sdram_platdata {
  28         struct socfpga_sdr *sdr;
  29 };
  30
  31 struct sdram_prot_rule {
  32         u32     sdram_start;    /* SDRAM start address */
  33         u32     sdram_end;      /* SDRAM end address */
  34         u32     rule;           /* SDRAM protection rule number: 0-19 */
  35         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  36
  37         u32     security;
  38         u32     portmask;
  39         u32     result;
  40         u32     lo_prot_id;
  41         u32     hi_prot_id;
  42 };
  43
  44 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
  45
  46 /**
  47  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  48  * @cfg:        SDRAM controller configuration data
  49  *
  50  * SDRAM Failure happens when accessing non-existent memory. Artificially
  51  * increase the number of rows so that the memory controller thinks it has
  52  * 4GB of RAM. This function returns such amount of rows.
  53  */
  54 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  55 {
  56         /* Define constant for 4G memory - used for SDRAM errata workaround */
  57 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  58         const unsigned long long memsize = MEMSIZE_4G;
  59         const unsigned int cs =
  60                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  61                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  62         const unsigned int rows =
  63                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  64                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  65         const unsigned int banks =
  66                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  67                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  68         const unsigned int cols =
  69                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  70                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  71         const unsigned int width = 8;
  72
  73         unsigned long long newrows;
  74         int bits, inewrowslog2;
  75
  76         debug("workaround rows - memsize %lld\n", memsize);
  77         debug("workaround rows - cs        %d\n", cs);
  78         debug("workaround rows - width     %d\n", width);
  79         debug("workaround rows - rows      %d\n", rows);
  80         debug("workaround rows - banks     %d\n", banks);
  81         debug("workaround rows - cols      %d\n", cols);
  82
  83         newrows = lldiv(memsize, cs * (width / 8));
  84         debug("rows workaround - term1 %lld\n", newrows);
  85
  86         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  87         debug("rows workaround - term2 %lld\n", newrows);
  88
  89         /*
  90          * Compute the hamming weight - same as number of bits set.
  91          * Need to see if result is ordinal power of 2 before
  92          * attempting log2 of result.
  93          */
  94         bits = generic_hweight32(newrows);
  95
  96         debug("rows workaround - bits %d\n", bits);
  97
  98         if (bits != 1) {
  99                 printf("SDRAM workaround failed, bits set %d\n", bits);
 100                 return rows;
 101         }
 102
 103         if (newrows > UINT_MAX) {
 104                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
 105                 return rows;
 106         }
 107
 108         inewrowslog2 = __ilog2(newrows);
 109
 110         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 111
 112         if (inewrowslog2 == -1) {
 113                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 114                 return rows;
 115         }
 116
 117         return inewrowslog2;
 118 }
 119
 120 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 121 static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
 122                            struct sdram_prot_rule *prule)
 123 {
 124         u32 lo_addr_bits;
 125         u32 hi_addr_bits;
 126         int ruleno = prule->rule;
 127
 128         /* Select the rule */
 129         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 130
 131         /* Obtain the address bits */
 132         lo_addr_bits = prule->sdram_start >> 20ULL;
 133         hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 134
 135         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 136               prule->sdram_start);
 137         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 138               prule->sdram_end);
 139
 140         /* Set rule addresses */
 141         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 142
 143         /* Set rule protection ids */
 144         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 145                &sdr_ctrl->prot_rule_id);
 146
 147         /* Set the rule data */
 148         writel(prule->security | (prule->valid << 2) |
 149                (prule->portmask << 3) | (prule->result << 13),
 150                &sdr_ctrl->prot_rule_data);
 151
 152         /* write the rule */
 153         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 154
 155         /* Set rule number to 0 by default */
 156         writel(0, &sdr_ctrl->prot_rule_rdwr);
 157 }
 158
 159 static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
 160                            struct sdram_prot_rule *prule)
 161 {
 162         u32 addr;
 163         u32 id;
 164         u32 data;
 165         int ruleno = prule->rule;
 166
 167         /* Read the rule */
 168         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 169         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 170
 171         /* Get the addresses */
 172         addr = readl(&sdr_ctrl->prot_rule_addr);
 173         prule->sdram_start = (addr & 0xFFF) << 20;
 174         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 175
 176         /* Get the configured protection IDs */
 177         id = readl(&sdr_ctrl->prot_rule_id);
 178         prule->lo_prot_id = id & 0xFFF;
 179         prule->hi_prot_id = (id >> 12) & 0xFFF;
 180
 181         /* Get protection data */
 182         data = readl(&sdr_ctrl->prot_rule_data);
 183
 184         prule->security = data & 0x3;
 185         prule->valid = (data >> 2) & 0x1;
 186         prule->portmask = (data >> 3) & 0x3FF;
 187         prule->result = (data >> 13) & 0x1;
 188 }
 189
 190 static void
 191 sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
 192                             const u32 sdram_start, const u32 sdram_end)
 193 {
 194         struct sdram_prot_rule rule;
 195         int rules;
 196
 197         /* Start with accepting all SDRAM transaction */
 198         writel(0x0, &sdr_ctrl->protport_default);
 199
 200         /* Clear all protection rules for warm boot case */
 201         memset(&rule, 0, sizeof(rule));
 202
 203         for (rules = 0; rules < 20; rules++) {
 204                 rule.rule = rules;
 205                 sdram_set_rule(sdr_ctrl, &rule);
 206         }
 207
 208         /* new rule: accept SDRAM */
 209         rule.sdram_start = sdram_start;
 210         rule.sdram_end = sdram_end;
 211         rule.lo_prot_id = 0x0;
 212         rule.hi_prot_id = 0xFFF;
 213         rule.portmask = 0x3FF;
 214         rule.security = 0x3;
 215         rule.result = 0;
 216         rule.valid = 1;
 217         rule.rule = 0;
 218
 219         /* set new rule */
 220         sdram_set_rule(sdr_ctrl, &rule);
 221
 222         /* default rule: reject everything */
 223         writel(0x3ff, &sdr_ctrl->protport_default);
 224 }
 225
 226 static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
 227 {
 228         struct sdram_prot_rule rule;
 229         int rules;
 230
 231         debug("SDRAM Prot rule, default %x\n",
 232               readl(&sdr_ctrl->protport_default));
 233
 234         for (rules = 0; rules < 20; rules++) {
 235                 rule.rule = rules;
 236                 sdram_get_rule(sdr_ctrl, &rule);
 237                 debug("Rule %d, rules ...\n", rules);
 238                 debug("    sdram start %x\n", rule.sdram_start);
 239                 debug("    sdram end   %x\n", rule.sdram_end);
 240                 debug("    low prot id %d, hi prot id %d\n",
 241                       rule.lo_prot_id,
 242                       rule.hi_prot_id);
 243                 debug("    portmask %x\n", rule.portmask);
 244                 debug("    security %d\n", rule.security);
 245                 debug("    result %d\n", rule.result);
 246                 debug("    valid %d\n", rule.valid);
 247         }
 248 }
 249
 250 /**
 251  * sdram_write_verify() - write to register and verify the write.
 252  * @addr:       Register address
 253  * @val:        Value to be written and verified
 254  *
 255  * This function writes to a register, reads back the value and compares
 256  * the result with the written value to check if the data match.
 257  */
 258 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 259 {
 260         u32 rval;
 261
 262         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 263         writel(val, addr);
 264
 265         debug("   Read and verify...");
 266         rval = readl(addr);
 267         if (rval != val) {
 268                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 269                       addr, val, rval);
 270                 return -EINVAL;
 271         }
 272
 273         debug("correct!\n");
 274         return 0;
 275 }
 276
 277 /**
 278  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 279  * @cfg:        SDRAM controller configuration data
 280  *
 281  * Return the value of DRAM CTRLCFG register.
 282  */
 283 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 284 {
 285         const u32 csbits =
 286                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 287                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 288         u32 addrorder =
 289                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 290                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 291
 292         u32 ctrl_cfg = cfg->ctrl_cfg;
 293
 294         /*
 295          * SDRAM Failure When Accessing Non-Existent Memory
 296          * Set the addrorder field of the SDRAM control register
 297          * based on the CSBITs setting.
 298          */
 299         if (csbits == 1) {
 300                 if (addrorder != 0)
 301                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 302                 addrorder = 0;
 303         } else if (csbits == 2) {
 304                 if (addrorder != 2)
 305                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 306                 addrorder = 2;
 307         }
 308
 309         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 310         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 311
 312         return ctrl_cfg;
 313 }
 314
 315 /**
 316  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 317  * @cfg:        SDRAM controller configuration data
 318  *
 319  * Return the value of DRAM ADDRW register.
 320  */
 321 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 322 {
 323         /*
 324          * SDRAM Failure When Accessing Non-Existent Memory
 325          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 326          * log2(number of chip select bits). Since there's only
 327          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 328          * which is the same as "chip selects" - 1.
 329          */
 330         const int rows = get_errata_rows(cfg);
 331         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 332
 333         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 334 }
 335
 336 /**
 337  * sdr_load_regs() - Load SDRAM controller registers
 338  * @cfg:        SDRAM controller configuration data
 339  *
 340  * This function loads the register values into the SDRAM controller block.
 341  */
 342 static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
 343                           const struct socfpga_sdram_config *cfg)
 344 {
 345         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 346         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 347
 348         debug("\nConfiguring CTRLCFG\n");
 349         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 350
 351         debug("Configuring DRAMTIMING1\n");
 352         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 353
 354         debug("Configuring DRAMTIMING2\n");
 355         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 356
 357         debug("Configuring DRAMTIMING3\n");
 358         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 359
 360         debug("Configuring DRAMTIMING4\n");
 361         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 362
 363         debug("Configuring LOWPWRTIMING\n");
 364         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 365
 366         debug("Configuring DRAMADDRW\n");
 367         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 368
 369         debug("Configuring DRAMIFWIDTH\n");
 370         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 371
 372         debug("Configuring DRAMDEVWIDTH\n");
 373         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 374
 375         debug("Configuring LOWPWREQ\n");
 376         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 377
 378         debug("Configuring DRAMINTR\n");
 379         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 380
 381         debug("Configuring STATICCFG\n");
 382         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 383
 384         debug("Configuring CTRLWIDTH\n");
 385         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 386
 387         debug("Configuring PORTCFG\n");
 388         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 389
 390         debug("Configuring FIFOCFG\n");
 391         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 392
 393         debug("Configuring MPPRIORITY\n");
 394         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 395
 396         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 397         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 398         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 399         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 400         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 401
 402         debug("Configuring MPPACING_MPPACING_0\n");
 403         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 404         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 405         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 406         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 407
 408         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 409         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 410         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 411         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 412
 413         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 414         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 415
 416         debug("Configuring CPORTWIDTH\n");
 417         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 418
 419         debug("Configuring CPORTWMAP\n");
 420         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 421
 422         debug("Configuring CPORTRMAP\n");
 423         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 424
 425         debug("Configuring RFIFOCMAP\n");
 426         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 427
 428         debug("Configuring WFIFOCMAP\n");
 429         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 430
 431         debug("Configuring CPORTRDWR\n");
 432         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 433
 434         debug("Configuring DRAMODT\n");
 435         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 436
 437         debug("Configuring EXTRATIME1\n");
 438         writel(cfg->extratime1, &sdr_ctrl->extratime1);
 439 }
 440
 441 /**
 442  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 443  * @sdr_phy_reg:        Value of the PHY control register 0
 444  *
 445  * Initialize the SDRAM MMR.
 446  */
 447 int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
 448                         unsigned int sdr_phy_reg)
 449 {
 450         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 451         const unsigned int rows =
 452                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 453                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 454         int ret;
 455
 456         writel(rows,
 457                socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 458
 459         sdr_load_regs(sdr_ctrl, cfg);
 460
 461         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 462         writel(cfg->fpgaport_rst,
 463                socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
 464
 465         /* only enable if the FPGA is programmed */
 466         if (fpgamgr_test_fpga_ready()) {
 467                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 468                                          cfg->fpgaport_rst);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         /* Restore the SDR PHY Register if valid */
 474         if (sdr_phy_reg != 0xffffffff)
 475                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 476
 477         /* Final step - apply configuration changes */
 478         debug("Configuring STATICCFG\n");
 479         clrsetbits_le32(&sdr_ctrl->static_cfg,
 480                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 481                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 482
 483         sdram_set_protection_config(sdr_ctrl, 0,
 484                                     sdram_calculate_size(sdr_ctrl) - 1);
 485
 486         sdram_dump_protection_config(sdr_ctrl);
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * sdram_calculate_size() - Calculate SDRAM size
 493  *
 494  * Calculate SDRAM device size based on SDRAM controller parameters.
 495  * Size is specified in bytes.
 496  */
 497 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
 498 {
 499         unsigned long temp;
 500         unsigned long row, bank, col, cs, width;
 501         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 502         const unsigned int csbits =
 503                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 504                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 505         const unsigned int rowbits =
 506                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 507                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 508
 509         temp = readl(&sdr_ctrl->dram_addrw);
 510         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 511                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 512
 513         /*
 514          * SDRAM Failure When Accessing Non-Existent Memory
 515          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 516          * since the FB specifies we modify ROWBITs to work around SDRAM
 517          * controller issue.
 518          */
 519         row = readl(socfpga_get_sysmgr_addr() +
 520                     SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
 521         if (row == 0)
 522                 row = rowbits;
 523         /*
 524          * If the stored handoff value for rows is greater than
 525          * the field width in the sdr.dramaddrw register then
 526          * something is very wrong. Revert to using the the #define
 527          * value handed off by the SOCEDS tool chain instead of
 528          * using a broken value.
 529          */
 530         if (row > 31)
 531                 row = rowbits;
 532
 533         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 534                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 535
 536         /*
 537          * SDRAM Failure When Accessing Non-Existent Memory
 538          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 539          * since the FB specifies we modify CSBITs to work around SDRAM
 540          * controller issue.
 541          */
 542         cs = csbits;
 543
 544         width = readl(&sdr_ctrl->dram_if_width);
 545
 546         /* ECC would not be calculated as its not addressible */
 547         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 548                 width = 32;
 549         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 550                 width = 16;
 551
 552         /* calculate the SDRAM size base on this info */
 553         temp = 1 << (row + bank + col);
 554         temp = temp * cs * (width  / 8);
 555
 556         debug("%s returns %ld\n", __func__, temp);
 557
 558         return temp;
 559 }
 560
 561 static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
 562 {
 563         struct altera_gen5_sdram_platdata *plat = dev->platdata;
 564
 565         plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
 566         if (!plat->sdr)
 567                 return -ENODEV;
 568
 569         return 0;
 570 }
 571
 572 static int altera_gen5_sdram_probe(struct udevice *dev)
 573 {
 574         int ret;
 575         unsigned long sdram_size;
 576         struct altera_gen5_sdram_platdata *plat = dev->platdata;
 577         struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
 578         struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
 579         struct reset_ctl_bulk resets;
 580
 581         ret = reset_get_bulk(dev, &resets);
 582         if (ret) {
 583                 dev_err(dev, "Can't get reset: %d\n", ret);
 584                 return -ENODEV;
 585         }
 586         reset_deassert_bulk(&resets);
 587
 588         if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
 589                 puts("SDRAM init failed.\n");
 590                 goto failed;
 591         }
 592
 593         debug("SDRAM: Calibrating PHY\n");
 594         /* SDRAM calibration */
 595         if (sdram_calibration_full(plat->sdr) == 0) {
 596                 puts("SDRAM calibration failed.\n");
 597                 goto failed;
 598         }
 599
 600         sdram_size = sdram_calculate_size(sdr_ctrl);
 601         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 602
 603         /* Sanity check ensure correct SDRAM size specified */
 604         if (get_ram_size(0, sdram_size) != sdram_size) {
 605                 puts("SDRAM size check failed!\n");
 606                 goto failed;
 607         }
 608
 609         priv->info.base = 0;
 610         priv->info.size = sdram_size;
 611
 612         return 0;
 613
 614 failed:
 615         reset_release_bulk(&resets);
 616         return -ENODEV;
 617 }
 618
 619 static int altera_gen5_sdram_get_info(struct udevice *dev,
 620                                       struct ram_info *info)
 621 {
 622         struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
 623
 624         info->base = priv->info.base;
 625         info->size = priv->info.size;
 626
 627         return 0;
 628 }
 629
 630 static const struct ram_ops altera_gen5_sdram_ops = {
 631         .get_info = altera_gen5_sdram_get_info,
 632 };
 633
 634 static const struct udevice_id altera_gen5_sdram_ids[] = {
 635         { .compatible = "altr,sdr-ctl" },
 636         { /* sentinel */ }
 637 };
 638
 639 U_BOOT_DRIVER(altera_gen5_sdram) = {
 640         .name = "altr_sdr_ctl",
 641         .id = UCLASS_RAM,
 642         .of_match = altera_gen5_sdram_ids,
 643         .ops = &altera_gen5_sdram_ops,
 644         .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
 645         .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
 646         .probe = altera_gen5_sdram_probe,
 647         .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
 648 };
 649
 650 #endif /* CONFIG_SPL_BUILD */