1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
13 #include <asm/arch/fpga_manager.h>
14 #include <asm/arch/misc.h>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/sdram.h>
17 #include <linux/kernel.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static void sdram_mmr_init(void);
22 static u64 sdram_size_calc(void);
24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
25 #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
27 #define ARRIA_DDR_CONFIG(A, B, C, R) \
28 (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
29 #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
30 #define DDR_REG_SEQ2CORE 0xFFD0507C
31 #define DDR_REG_CORE2SEQ 0xFFD05078
32 #define DDR_READ_LATENCY_DELAY 40
33 #define DDR_SIZE_2GB_HEX 0x80000000
34 #define DDR_MAX_TRIES 0x00100000
36 #define IO48_MMR_DRAMSTS 0xFFCFA0EC
37 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
38 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
39 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
41 #define SEQ2CORE_MASK 0xF
42 #define CORE2SEQ_INT_REQ 0xF
43 #define SEQ2CORE_INT_RESP_BIT 3
45 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
46 (void *)SOCFPGA_SDR_ADDRESS;
47 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
48 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
49 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
50 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
51 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
52 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
53 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
54 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
55 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
57 /* The following are the supported configurations */
58 static u32 ddr_config[] = {
59 /* Chip - Row - Bank - Column Style */
61 ARRIA_DDR_CONFIG(0, 3, 10, 12),
62 ARRIA_DDR_CONFIG(0, 3, 10, 13),
63 ARRIA_DDR_CONFIG(0, 3, 10, 14),
64 ARRIA_DDR_CONFIG(0, 3, 10, 15),
65 ARRIA_DDR_CONFIG(0, 3, 10, 16),
66 ARRIA_DDR_CONFIG(0, 3, 10, 17),
68 ARRIA_DDR_CONFIG(0, 3, 11, 14),
69 ARRIA_DDR_CONFIG(0, 3, 11, 15),
70 ARRIA_DDR_CONFIG(0, 3, 11, 16),
71 ARRIA_DDR_CONFIG(0, 3, 12, 15),
73 ARRIA_DDR_CONFIG(0, 4, 10, 14),
74 ARRIA_DDR_CONFIG(0, 4, 10, 15),
75 ARRIA_DDR_CONFIG(0, 4, 10, 16),
76 ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
77 /* Chip - Bank - Row - Column Style */
78 ARRIA_DDR_CONFIG(1, 3, 10, 12),
79 ARRIA_DDR_CONFIG(1, 3, 10, 13),
80 ARRIA_DDR_CONFIG(1, 3, 10, 14),
81 ARRIA_DDR_CONFIG(1, 3, 10, 15),
82 ARRIA_DDR_CONFIG(1, 3, 10, 16),
83 ARRIA_DDR_CONFIG(1, 3, 10, 17),
84 ARRIA_DDR_CONFIG(1, 3, 11, 14),
85 ARRIA_DDR_CONFIG(1, 3, 11, 15),
86 ARRIA_DDR_CONFIG(1, 3, 11, 16),
87 ARRIA_DDR_CONFIG(1, 3, 12, 15),
89 ARRIA_DDR_CONFIG(1, 4, 10, 14),
90 ARRIA_DDR_CONFIG(1, 4, 10, 15),
91 ARRIA_DDR_CONFIG(1, 4, 10, 16),
92 ARRIA_DDR_CONFIG(1, 4, 10, 17),
95 static int match_ddr_conf(u32 ddr_conf)
99 for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
100 if (ddr_conf == ddr_config[i])
106 /* Check whether SDRAM is successfully Calibrated */
107 static int is_sdram_cal_success(void)
109 return readl(&socfpga_ecc_hmc_base->ddrcalstat);
112 static unsigned char ddr_get_bit(u32 ereg, unsigned char bit)
114 u32 reg = readl(ereg);
116 return (reg & BIT(bit)) ? 1 : 0;
119 static unsigned char ddr_wait_bit(u32 ereg, u32 bit,
120 u32 expected, u32 timeout_usec)
124 for (tmr = 0; tmr < timeout_usec; tmr += 100) {
127 if (ddr_get_bit(ereg, bit) == expected)
134 static int emif_clear(void)
136 u32 i = DDR_MAX_TRIES;
139 writel(0, DDR_REG_CORE2SEQ);
142 ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
143 SEQ2CORE_MASK, 1, 50, 0);
144 } while (ret && (--i > 0));
149 static int emif_reset(void)
153 c2s = readl(DDR_REG_CORE2SEQ);
154 s2c = readl(DDR_REG_SEQ2CORE);
156 debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
157 c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
158 readl(IO48_MMR_NIOS2_RESERVE1),
159 readl(IO48_MMR_NIOS2_RESERVE2),
160 readl(IO48_MMR_DRAMSTS));
162 if ((s2c & SEQ2CORE_MASK) && emif_clear()) {
163 debug("failed emif_clear()\n");
167 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
169 if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) {
170 debug("emif_reset failed to see interrupt acknowledge\n");
173 debug("emif_reset interrupt acknowledged\n");
177 debug("emif_clear() failed\n");
180 debug("emif_reset interrupt cleared\n");
182 debug("nr0=%08x nr1=%08x nr2=%08x\n",
183 readl(IO48_MMR_NIOS2_RESERVE0),
184 readl(IO48_MMR_NIOS2_RESERVE1),
185 readl(IO48_MMR_NIOS2_RESERVE2));
190 static int ddr_setup(void)
192 int i, j, ddr_setup_complete = 0;
194 /* Try 3 times to do a calibration */
195 for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
198 /* A delay to wait for calibration bit to set */
199 for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
201 ddr_setup_complete = is_sdram_cal_success();
204 if (!ddr_setup_complete)
206 puts("Error: Failed to reset EMIF\n");
209 /* After 3 times trying calibration */
210 if (!ddr_setup_complete) {
211 puts("Error: Could Not Calibrate SDRAM\n");
218 /* Function to startup the SDRAM*/
219 static int sdram_startup(void)
221 /* Release NOC ddr scheduler from reset */
222 socfpga_reset_deassert_noc_ddr_scheduler();
224 /* Bringup the DDR (calibration and configuration) */
228 static u64 sdram_size_calc(void)
230 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
232 u64 size = BIT(((dramaddrw &
233 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
234 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
236 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
237 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
239 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
240 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
242 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
243 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
244 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
246 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
247 ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
249 debug("SDRAM size=%llu", size);
254 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
255 static void sdram_mmr_init(void)
257 u32 update_value, io48_value;
258 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
259 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
260 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
261 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
262 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
263 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
264 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
265 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
266 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
270 * Configure the DDR IO size [0xFFCFB008]
271 * niosreserve0: Used to indicate DDR width &
272 * bit[7:0] = Number of data bits (0x20 for 32bit)
273 * bit[8] = 1 if user-mode OCT is present
274 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
275 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
276 * niosreserve1: IP ADCDS version encoded as 16 bit value
277 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
278 * 3=EAP, 4-6 are reserved)
279 * bit[5:3] = Service Pack # (e.g. 1)
280 * bit[9:6] = Minor Release #
281 * bit[14:10] = Major Release #
283 if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) {
284 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
285 writel(((update_value & 0xFF) >> 5),
286 &socfpga_ecc_hmc_base->ddrioctrl);
289 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
291 /* Set the DDR Configuration [0xFFD12400] */
292 io48_value = ARRIA_DDR_CONFIG(
294 IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
295 IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
297 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
298 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
300 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
301 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
303 IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
305 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
306 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
308 update_value = match_ddr_conf(io48_value);
311 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
314 * Configure DDR timing [0xFFD1240C]
315 * RDTOMISS = tRTP + tRP + tRCD - BL/2
316 * WRTOMISS = WL + tWR + tRP + tRCD and
317 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
318 * First part of equation is in memory clock units so divide by 2
319 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
320 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
322 u32 ctrlcfg0_cfg_ctrl_burst_len =
323 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
324 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
326 u32 caltim0_cfg_act_to_rdwr = caltim0 &
327 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
329 u32 caltim0_cfg_act_to_act =
330 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
331 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
333 u32 caltim0_cfg_act_to_act_db =
335 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
336 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
338 u32 caltim1_cfg_rd_to_wr =
339 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
340 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
342 u32 caltim1_cfg_rd_to_rd_dc =
343 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
344 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
346 u32 caltim1_cfg_rd_to_wr_dc =
347 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
348 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
350 u32 caltim2_cfg_rd_to_pch =
351 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
352 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
354 u32 caltim3_cfg_wr_to_rd =
355 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
356 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
358 u32 caltim3_cfg_wr_to_rd_dc =
359 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
360 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
362 u32 caltim4_cfg_pch_to_valid =
363 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
364 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
366 u32 caltim9_cfg_4_act_to_act = caltim9 &
367 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
369 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
370 caltim0_cfg_act_to_rdwr -
371 (ctrlcfg0_cfg_ctrl_burst_len >> 2));
373 io48_value = ((((socfpga_io48_mmr_base->dramtiming0 &
374 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
375 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
376 /* Up to here was in memory cycles so divide by 2 */
377 caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
378 caltim4_cfg_pch_to_valid);
380 writel(((caltim0_cfg_act_to_act <<
381 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
383 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
385 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
386 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
387 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
388 (caltim1_cfg_rd_to_wr <<
389 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
390 (caltim3_cfg_wr_to_rd <<
391 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
392 (((ddrioctl == 1) ? 1 : 0) <<
393 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
394 &socfpga_noc_ddr_scheduler_base->
395 ddr_t_main_scheduler_ddrtiming);
397 /* Configure DDR mode [0xFFD12410] [precharge = 0] */
398 writel(((ddrioctl ? 0 : 1) <<
399 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
400 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
402 /* Configure the read latency [0xFFD12414] */
403 writel(((socfpga_io48_mmr_base->dramtiming0 &
404 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
405 DDR_READ_LATENCY_DELAY,
406 &socfpga_noc_ddr_scheduler_base->
407 ddr_t_main_scheduler_readlatency);
410 * Configuring timing values concerning activate commands
411 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
413 writel(((caltim0_cfg_act_to_act_db <<
414 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
415 (caltim9_cfg_4_act_to_act <<
416 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
417 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
418 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
419 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
422 * Configuring timing values concerning device to device data bus
423 * ownership change [0xFFD1243C]
425 writel(((caltim1_cfg_rd_to_rd_dc <<
426 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
427 (caltim1_cfg_rd_to_wr_dc <<
428 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
429 (caltim3_cfg_wr_to_rd_dc <<
430 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
431 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
433 /* Enable or disable the SDRAM ECC */
434 if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
435 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
436 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
437 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
438 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
439 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
440 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
441 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
442 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
443 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
444 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
446 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
447 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
448 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
449 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
450 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
451 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
452 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
456 struct firewall_entry {
457 const char *prop_name;
462 #define FW_MPU_FPGA_ADDRESS \
463 ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
464 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
466 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
467 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
468 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
470 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
471 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
472 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
474 const struct firewall_entry firewall_table[] = {
477 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
478 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
479 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
483 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
484 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
485 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
486 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
490 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
491 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
492 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
496 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
497 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
498 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
502 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
503 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
504 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
508 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
509 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
510 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
514 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
515 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
516 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
520 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
521 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
522 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
526 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
527 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
528 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
532 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
533 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
534 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
538 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
539 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
540 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
544 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
545 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
546 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
550 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
551 (fpga2sdram0region0addr),
552 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
553 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
557 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
558 (fpga2sdram0region1addr),
559 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
560 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
564 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
565 (fpga2sdram0region2addr),
566 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
567 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
571 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
572 (fpga2sdram0region3addr),
573 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
574 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
578 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
579 (fpga2sdram1region0addr),
580 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
581 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
585 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
586 (fpga2sdram1region1addr),
587 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
588 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
592 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
593 (fpga2sdram1region2addr),
594 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
595 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
599 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
600 (fpga2sdram1region3addr),
601 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
602 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
606 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
607 (fpga2sdram2region0addr),
608 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
609 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
613 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
614 (fpga2sdram2region1addr),
615 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
616 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
620 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
621 (fpga2sdram2region2addr),
622 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
623 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
627 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
628 (fpga2sdram2region3addr),
629 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
630 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
635 static int of_sdram_firewall_setup(const void *blob)
637 int child, i, node, ret;
641 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
645 child = fdt_first_subnode(blob, node);
649 /* set to default state */
650 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
651 writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
654 for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
655 sprintf(name, "%s", firewall_table[i].prop_name);
656 ret = fdtdec_get_int_array(blob, child, name,
659 sprintf(name, "altr,%s", firewall_table[i].prop_name);
660 ret = fdtdec_get_int_array(blob, child, name,
666 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
667 (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
668 firewall_table[i].cfg_addr);
669 setbits_le32(firewall_table[i].en_addr,
670 firewall_table[i].en_bit);
676 int ddr_calibration_sequence(void)
680 /* Check to see if SDRAM cal was success */
681 if (sdram_startup()) {
682 puts("DDRCAL: Failed\n");
686 puts("DDRCAL: Success\n");
690 /* initialize the MMR register */
693 /* assigning the SDRAM size */
694 u64 size = sdram_size_calc();
697 * If size is less than zero, this is invalid/weird value from
698 * calculation, use default Config size.
699 * Up to 2GB is supported, 2GB would be used if more than that.
702 gd->ram_size = PHYS_SDRAM_1_SIZE;
703 else if (DDR_SIZE_2GB_HEX <= size)
704 gd->ram_size = DDR_SIZE_2GB_HEX;
706 gd->ram_size = (u32)size;
708 /* setup the dram info within bd */
709 dram_init_banksize();
711 if (of_sdram_firewall_setup(gd->fdt_blob))
712 puts("FW: Error Configuring Firewall\n");
717 void dram_bank_mmu_setup(int bank)
722 debug("%s: bank: %d\n", __func__, bank);
723 for (i = bd->bi_dram[bank].start >> 20;
724 i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
726 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
727 set_section_dcache(i, DCACHE_WRITETHROUGH);
729 set_section_dcache(i, DCACHE_WRITEBACK);
733 /* same as above but just that we would want cacheable for ocram too */
734 i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
735 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
736 set_section_dcache(i, DCACHE_WRITETHROUGH);
738 set_section_dcache(i, DCACHE_WRITEBACK);