drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <malloc.h>
  11 #include <wait_bit.h>
  12 #include <watchdog.h>
  13 #include <asm/cache.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fpga_manager.h>
  16 #include <asm/arch/misc.h>
  17 #include <asm/arch/reset_manager.h>
  18 #include <asm/arch/sdram.h>
  19 #include <linux/kernel.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static void sdram_mmr_init(void);
  24 static u64 sdram_size_calc(void);
  25
  26 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  27 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  28
  29 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  30         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  31 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  32 #define DDR_REG_SEQ2CORE        0xFFD0507C
  33 #define DDR_REG_CORE2SEQ        0xFFD05078
  34 #define DDR_READ_LATENCY_DELAY  40
  35 #define DDR_SIZE_2GB_HEX        0x80000000
  36
  37 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  38 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  39 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  40 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  41
  42 #define SEQ2CORE_MASK           0xF
  43 #define CORE2SEQ_INT_REQ        0xF
  44 #define SEQ2CORE_INT_RESP_BIT   3
  45
  46 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  47                 (void *)SOCFPGA_SDR_ADDRESS;
  48 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  49                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  50 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  51                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  52                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  53 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  54                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  55 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  56                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  57
  58 /* The following are the supported configurations */
  59 static u32 ddr_config[] = {
  60         /* Chip - Row - Bank - Column Style */
  61         /* All Types */
  62         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  63         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  64         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  65         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  66         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  67         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  68         /* LPDDR x16 */
  69         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  70         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  71         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  72         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  73         /* DDR4 Only */
  74         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  75         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  76         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  77         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  78         /* Chip - Bank - Row - Column Style */
  79         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  80         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  81         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  82         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  83         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  84         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  85         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  86         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  87         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  88         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  89         /* DDR4 Only */
  90         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  91         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  92         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  93         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  94 };
  95
  96 static int match_ddr_conf(u32 ddr_conf)
  97 {
  98         int i;
  99
 100         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 101                 if (ddr_conf == ddr_config[i])
 102                         return i;
 103         }
 104         return 0;
 105 }
 106
 107 static int emif_clear(void)
 108 {
 109         writel(0, DDR_REG_CORE2SEQ);
 110
 111         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 112                                 SEQ2CORE_MASK, 0, 1000, 0);
 113 }
 114
 115 static int emif_reset(void)
 116 {
 117         u32 c2s, s2c;
 118         int ret;
 119
 120         c2s = readl(DDR_REG_CORE2SEQ);
 121         s2c = readl(DDR_REG_SEQ2CORE);
 122
 123         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 124              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 125              readl(IO48_MMR_NIOS2_RESERVE1),
 126              readl(IO48_MMR_NIOS2_RESERVE2),
 127              readl(IO48_MMR_DRAMSTS));
 128
 129         if (s2c & SEQ2CORE_MASK) {
 130                 ret = emif_clear();
 131                 if (ret) {
 132                         debug("failed emif_clear()\n");
 133                         return -EPERM;
 134                 }
 135         }
 136
 137         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 138
 139         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 140                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 141         if (ret) {
 142                 debug("emif_reset failed to see interrupt acknowledge\n");
 143                 emif_clear();
 144                 return ret;
 145         }
 146
 147         mdelay(1);
 148
 149         ret = emif_clear();
 150         if (ret) {
 151                 debug("emif_clear() failed\n");
 152                 return -EPERM;
 153         }
 154         debug("emif_reset interrupt cleared\n");
 155
 156         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 157              readl(IO48_MMR_NIOS2_RESERVE0),
 158              readl(IO48_MMR_NIOS2_RESERVE1),
 159              readl(IO48_MMR_NIOS2_RESERVE2));
 160
 161         return 0;
 162 }
 163
 164 static int ddr_setup(void)
 165 {
 166         int i, ret;
 167
 168         /* Try 32 times to do a calibration */
 169         for (i = 0; i < 32; i++) {
 170                 mdelay(500);
 171                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 172                                         BIT(0), true, 500, false);
 173                 if (!ret)
 174                         return 0;
 175
 176                 ret = emif_reset();
 177                 if (ret)
 178                         puts("Error: Failed to reset EMIF\n");
 179         }
 180
 181         puts("Error: Could Not Calibrate SDRAM\n");
 182         return -EPERM;
 183 }
 184
 185 static int sdram_is_ecc_enabled(void)
 186 {
 187         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 188                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 189 }
 190
 191 /* Initialize SDRAM ECC bits to avoid false DBE */
 192 static void sdram_init_ecc_bits(u32 size)
 193 {
 194         icache_enable();
 195
 196         memset(0, 0, 0x8000);
 197         gd->arch.tlb_addr = 0x4000;
 198         gd->arch.tlb_size = PGTABLE_SIZE;
 199
 200         dcache_enable();
 201
 202         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 203         memset((void *)0x8000, 0, size - 0x8000);
 204         flush_dcache_all();
 205         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 206         dcache_disable();
 207 }
 208
 209 /* Function to startup the SDRAM*/
 210 static int sdram_startup(void)
 211 {
 212         /* Release NOC ddr scheduler from reset */
 213         socfpga_reset_deassert_noc_ddr_scheduler();
 214
 215         /* Bringup the DDR (calibration and configuration) */
 216         return ddr_setup();
 217 }
 218
 219 static u64 sdram_size_calc(void)
 220 {
 221         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 222
 223         u64 size = BIT(((dramaddrw &
 224                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 225                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 226                 ((dramaddrw &
 227                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 228                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 229                 ((dramaddrw &
 230                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 231                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 232                 ((dramaddrw &
 233                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 234                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 235                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 236
 237         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 238                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 239
 240         debug("SDRAM size=%llu\n", size);
 241
 242         return size;
 243 }
 244
 245 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 246 static void sdram_mmr_init(void)
 247 {
 248         u32 update_value, io48_value;
 249         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 250         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 251         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 252         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 253         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 254         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 255         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 256         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 257         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 258         u32 ddrioctl;
 259
 260         /*
 261          * Configure the DDR IO size [0xFFCFB008]
 262          * niosreserve0: Used to indicate DDR width &
 263          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 264          *      bit[8]   = 1 if user-mode OCT is present
 265          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 266          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 267          * niosreserve1: IP ADCDS version encoded as 16 bit value
 268          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 269          *                          3=EAP, 4-6 are reserved)
 270          *      bit[5:3] = Service Pack # (e.g. 1)
 271          *      bit[9:6] = Minor Release #
 272          *      bit[14:10] = Major Release #
 273          */
 274         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 275                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 276                 writel(((update_value & 0xFF) >> 5),
 277                        &socfpga_ecc_hmc_base->ddrioctrl);
 278         }
 279
 280         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 281
 282         /* Set the DDR Configuration [0xFFD12400] */
 283         io48_value = ARRIA_DDR_CONFIG(
 284                         ((ctrlcfg1 &
 285                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 286                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 287                         ((dramaddrw &
 288                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 289                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 290                         ((dramaddrw &
 291                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 292                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 293                         (dramaddrw &
 294                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 295                         ((dramaddrw &
 296                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 297                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 298
 299         update_value = match_ddr_conf(io48_value);
 300         if (update_value)
 301                 writel(update_value,
 302                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 303
 304         /*
 305          * Configure DDR timing [0xFFD1240C]
 306          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 307          *  WRTOMISS = WL + tWR + tRP + tRCD and
 308          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 309          *  First part of equation is in memory clock units so divide by 2
 310          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 311          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 312          */
 313         u32 ctrlcfg0_cfg_ctrl_burst_len =
 314                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 315                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 316
 317         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 318                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 319
 320         u32 caltim0_cfg_act_to_act =
 321                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 322                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 323
 324         u32 caltim0_cfg_act_to_act_db =
 325                 (caltim0 &
 326                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 327                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 328
 329         u32 caltim1_cfg_rd_to_wr =
 330                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 331                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 332
 333         u32 caltim1_cfg_rd_to_rd_dc =
 334                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 335                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 336
 337         u32 caltim1_cfg_rd_to_wr_dc =
 338                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 339                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 340
 341         u32 caltim2_cfg_rd_to_pch =
 342                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 343                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 344
 345         u32 caltim3_cfg_wr_to_rd =
 346                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 347                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 348
 349         u32 caltim3_cfg_wr_to_rd_dc =
 350                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 351                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 352
 353         u32 caltim4_cfg_pch_to_valid =
 354                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 355                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 356
 357         u32 caltim9_cfg_4_act_to_act = caltim9 &
 358                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 359
 360         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 361                         caltim0_cfg_act_to_rdwr -
 362                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 363
 364         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 365                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 366                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 367                       /* Up to here was in memory cycles so divide by 2 */
 368                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 369                       caltim4_cfg_pch_to_valid);
 370
 371         writel(((caltim0_cfg_act_to_act <<
 372                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 373                 (update_value <<
 374                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 375                 (io48_value <<
 376                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 377                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 378                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 379                 (caltim1_cfg_rd_to_wr <<
 380                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 381                 (caltim3_cfg_wr_to_rd <<
 382                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 383                 (((ddrioctl == 1) ? 1 : 0) <<
 384                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 385                 &socfpga_noc_ddr_scheduler_base->
 386                         ddr_t_main_scheduler_ddrtiming);
 387
 388         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 389         writel(((ddrioctl ? 0 : 1) <<
 390                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 391                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 392
 393         /* Configure the read latency [0xFFD12414] */
 394         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 395                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 396                 DDR_READ_LATENCY_DELAY,
 397                 &socfpga_noc_ddr_scheduler_base->
 398                         ddr_t_main_scheduler_readlatency);
 399
 400         /*
 401          * Configuring timing values concerning activate commands
 402          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 403          */
 404         writel(((caltim0_cfg_act_to_act_db <<
 405                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 406                 (caltim9_cfg_4_act_to_act <<
 407                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 408                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 409                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 410                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 411
 412         /*
 413          * Configuring timing values concerning device to device data bus
 414          * ownership change [0xFFD1243C]
 415          */
 416         writel(((caltim1_cfg_rd_to_rd_dc <<
 417                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 418                 (caltim1_cfg_rd_to_wr_dc <<
 419                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 420                 (caltim3_cfg_wr_to_rd_dc <<
 421                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 422                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 423
 424         /* Enable or disable the SDRAM ECC */
 425         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 426                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 427                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 428                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 429                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 430                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 431                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 432                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 433                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 434                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 435                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 436         } else {
 437                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 438                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 439                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 440                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 441                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 442                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 443                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 444         }
 445 }
 446
 447 struct firewall_entry {
 448         const char *prop_name;
 449         const u32 cfg_addr;
 450         const u32 en_addr;
 451         const u32 en_bit;
 452 };
 453 #define FW_MPU_FPGA_ADDRESS \
 454         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 455         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 456
 457 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 458                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 459                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 460
 461 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 462                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 463                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 464
 465 const struct firewall_entry firewall_table[] = {
 466         {
 467                 "mpu0",
 468                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 469                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 470                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 471         },
 472         {
 473                 "mpu1",
 474                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 475                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 476                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 477                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 478         },
 479         {
 480                 "mpu2",
 481                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 482                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 483                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 484         },
 485         {
 486                 "mpu3",
 487                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 488                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 489                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 490         },
 491         {
 492                 "l3-0",
 493                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 494                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 495                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 496         },
 497         {
 498                 "l3-1",
 499                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 500                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 501                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 502         },
 503         {
 504                 "l3-2",
 505                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 506                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 507                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 508         },
 509         {
 510                 "l3-3",
 511                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 512                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 513                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 514         },
 515         {
 516                 "l3-4",
 517                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 518                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 519                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 520         },
 521         {
 522                 "l3-5",
 523                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 524                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 525                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 526         },
 527         {
 528                 "l3-6",
 529                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 530                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 531                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 532         },
 533         {
 534                 "l3-7",
 535                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 536                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 537                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 538         },
 539         {
 540                 "fpga2sdram0-0",
 541                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 542                 (fpga2sdram0region0addr),
 543                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 544                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 545         },
 546         {
 547                 "fpga2sdram0-1",
 548                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 549                 (fpga2sdram0region1addr),
 550                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 551                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 552         },
 553         {
 554                 "fpga2sdram0-2",
 555                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 556                 (fpga2sdram0region2addr),
 557                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 558                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 559         },
 560         {
 561                 "fpga2sdram0-3",
 562                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 563                 (fpga2sdram0region3addr),
 564                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 565                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 566         },
 567         {
 568                 "fpga2sdram1-0",
 569                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 570                 (fpga2sdram1region0addr),
 571                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 572                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 573         },
 574         {
 575                 "fpga2sdram1-1",
 576                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 577                 (fpga2sdram1region1addr),
 578                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 579                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 580         },
 581         {
 582                 "fpga2sdram1-2",
 583                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 584                 (fpga2sdram1region2addr),
 585                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 586                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 587         },
 588         {
 589                 "fpga2sdram1-3",
 590                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 591                 (fpga2sdram1region3addr),
 592                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 593                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 594         },
 595         {
 596                 "fpga2sdram2-0",
 597                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 598                 (fpga2sdram2region0addr),
 599                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 600                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 601         },
 602         {
 603                 "fpga2sdram2-1",
 604                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 605                 (fpga2sdram2region1addr),
 606                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 607                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 608         },
 609         {
 610                 "fpga2sdram2-2",
 611                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 612                 (fpga2sdram2region2addr),
 613                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 614                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 615         },
 616         {
 617                 "fpga2sdram2-3",
 618                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 619                 (fpga2sdram2region3addr),
 620                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 621                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 622         },
 623
 624 };
 625
 626 static int of_sdram_firewall_setup(const void *blob)
 627 {
 628         int child, i, node, ret;
 629         u32 start_end[2];
 630         char name[32];
 631
 632         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 633         if (node < 0)
 634                 return -ENXIO;
 635
 636         child = fdt_first_subnode(blob, node);
 637         if (child < 0)
 638                 return -ENXIO;
 639
 640         /* set to default state */
 641         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 642         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 643
 644
 645         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 646                 sprintf(name, "%s", firewall_table[i].prop_name);
 647                 ret = fdtdec_get_int_array(blob, child, name,
 648                                            start_end, 2);
 649                 if (ret) {
 650                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 651                         ret = fdtdec_get_int_array(blob, child, name,
 652                                                    start_end, 2);
 653                         if (ret)
 654                                 continue;
 655                 }
 656
 657                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 658                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 659                        firewall_table[i].cfg_addr);
 660                 setbits_le32(firewall_table[i].en_addr,
 661                              firewall_table[i].en_bit);
 662         }
 663
 664         return 0;
 665 }
 666
 667 int ddr_calibration_sequence(void)
 668 {
 669         WATCHDOG_RESET();
 670
 671         /* Check to see if SDRAM cal was success */
 672         if (sdram_startup()) {
 673                 puts("DDRCAL: Failed\n");
 674                 return -EPERM;
 675         }
 676
 677         puts("DDRCAL: Success\n");
 678
 679         WATCHDOG_RESET();
 680
 681         /* initialize the MMR register */
 682         sdram_mmr_init();
 683
 684         /* assigning the SDRAM size */
 685         u64 size = sdram_size_calc();
 686
 687         /*
 688          * If size is less than zero, this is invalid/weird value from
 689          * calculation, use default Config size.
 690          * Up to 2GB is supported, 2GB would be used if more than that.
 691          */
 692         if (size <= 0)
 693                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 694         else if (DDR_SIZE_2GB_HEX <= size)
 695                 gd->ram_size = DDR_SIZE_2GB_HEX;
 696         else
 697                 gd->ram_size = (u32)size;
 698
 699         /* setup the dram info within bd */
 700         dram_init_banksize();
 701
 702         if (of_sdram_firewall_setup(gd->fdt_blob))
 703                 puts("FW: Error Configuring Firewall\n");
 704
 705         if (sdram_is_ecc_enabled())
 706                 sdram_init_ecc_bits(gd->ram_size);
 707
 708         return 0;
 709 }