drivers/ddr/altera/sdram_agilex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <div64.h>
  11 #include <fdtdec.h>
  12 #include <hang.h>
  13 #include <ram.h>
  14 #include <reset.h>
  15 #include "sdram_soc64.h"
  16 #include <wait_bit.h>
  17 #include <asm/arch/firewall.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int sdram_mmr_init_full(struct udevice *dev)
  26 {
  27         struct altera_sdram_platdata *plat = dev->platdata;
  28         struct altera_sdram_priv *priv = dev_get_priv(dev);
  29         u32 i;
  30         int ret;
  31         phys_size_t hw_size;
  32         bd_t bd = {0};
  33
  34         /* Ensure HMC clock is running */
  35         if (poll_hmc_clock_status()) {
  36                 debug("DDR: Error as HMC clock was not running\n");
  37                 return -EPERM;
  38         }
  39
  40         /* Trying 3 times to do a calibration */
  41         for (i = 0; i < 3; i++) {
  42                 ret = wait_for_bit_le32((const void *)(plat->hmc +
  43                                         DDRCALSTAT),
  44                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  45                                         false);
  46                 if (!ret)
  47                         break;
  48
  49                 emif_reset(plat);
  50         }
  51
  52         if (ret) {
  53                 puts("DDR: Error as SDRAM calibration failed\n");
  54                 return -EPERM;
  55         }
  56         debug("DDR: Calibration success\n");
  57
  58         /*
  59          * Configure the DDR IO size
  60          * niosreserve0: Used to indicate DDR width &
  61          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  62          *      bit[8]   = 1 if user-mode OCT is present
  63          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
  64          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
  65          * niosreserve1: IP ADCDS version encoded as 16 bit value
  66          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  67          *                          3=EAP, 4-6 are reserved)
  68          *      bit[5:3] = Service Pack # (e.g. 1)
  69          *      bit[9:6] = Minor Release #
  70          *      bit[14:10] = Major Release #
  71          */
  72         /* Configure DDR IO size x16, x32 and x64 mode */
  73         u32 update_value;
  74
  75         update_value = hmc_readl(plat, NIOSRESERVED0);
  76         update_value = (update_value & 0xFF) >> 5;
  77
  78         /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */
  79         update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);
  80         hmc_ecc_writel(plat, update_value, DDRIOCTRL);
  81
  82         /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */
  83         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  84
  85         /* assigning the SDRAM size */
  86         phys_size_t size = sdram_calculate_size(plat);
  87
  88         if (size <= 0)
  89                 hw_size = PHYS_SDRAM_1_SIZE;
  90         else
  91                 hw_size = size;
  92
  93         /* Get bank configuration from devicetree */
  94         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  95                                      (phys_size_t *)&gd->ram_size, &bd);
  96         if (ret) {
  97                 puts("DDR: Failed to decode memory node\n");
  98                 return -ENXIO;
  99         }
 100
 101         if (gd->ram_size != hw_size) {
 102                 printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",
 103                        gd->ram_size >> 20);
 104                 printf(" mismatch with hardware (%lld MiB).\n",
 105                        hw_size >> 20);
 106         }
 107
 108         if (gd->ram_size > hw_size) {
 109                 printf("DDR: Error: DRAM size from device tree is greater\n");
 110                 printf(" than hardware size.\n");
 111                 hang();
 112         }
 113
 114         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 115
 116         /* This enables nonsecure access to DDR */
 117         /* mpuregion0addr_limit */
 118         FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
 119                               FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 120         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 121
 122         /* nonmpuregion0addr_limit */
 123         FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
 124                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 125
 126         /* Enable mpuregion0enable and nonmpuregion0enable */
 127         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 128                               FW_MPU_DDR_SCR_EN_SET);
 129
 130         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 131
 132         /* Enable or disable the DDR ECC */
 133         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 134                 setbits_le32(plat->hmc + ECCCTRL1,
 135                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 136                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 137                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 138                 clrbits_le32(plat->hmc + ECCCTRL1,
 139                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 140                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 141                 setbits_le32(plat->hmc + ECCCTRL2,
 142                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 143                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 144                 setbits_le32(plat->hmc + ERRINTEN,
 145                              DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);
 146
 147                 if (!cpu_has_been_warmreset())
 148                         sdram_init_ecc_bits(&bd);
 149         } else {
 150                 clrbits_le32(plat->hmc + ECCCTRL1,
 151                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 152                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 153                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 154                 clrbits_le32(plat->hmc + ECCCTRL2,
 155                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 156                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 157         }
 158
 159         /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
 160         writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 161
 162         sdram_size_check(&bd);
 163
 164         priv->info.base = bd.bi_dram[0].start;
 165         priv->info.size = gd->ram_size;
 166
 167         debug("DDR: HMC init success\n");
 168         return 0;
 169 }