2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
24 && defined(CONFIG_TULIP)
38 #define PCI_CFDA_PSM 0x43
40 #define CFRV_RN 0x000000f0 /* Revision Number */
42 #define WAKEUP 0x00 /* Power Saving Wakeup */
43 #define SLEEP 0x80 /* Power Saving Sleep Mode */
45 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
47 /* Ethernet chip registers.
49 #define DE4X5_BMR 0x000 /* Bus Mode Register */
50 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
51 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
52 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
53 #define DE4X5_STS 0x028 /* Status Register */
54 #define DE4X5_OMR 0x030 /* Operation Mode Register */
55 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
56 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
60 #define BMR_SWR 0x00000001 /* Software Reset */
61 #define STS_TS 0x00700000 /* Transmit Process State */
62 #define STS_RS 0x000e0000 /* Receive Process State */
63 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
64 #define OMR_SR 0x00000002 /* Start/Stop Receive */
65 #define OMR_PS 0x00040000 /* Port Select */
66 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
67 #define OMR_PM 0x00000080 /* Pass All Multicast */
71 #define R_OWN 0x80000000 /* Own Bit */
72 #define RD_RER 0x02000000 /* Receive End Of Ring */
73 #define RD_LS 0x00000100 /* Last Descriptor */
74 #define RD_ES 0x00008000 /* Error Summary */
75 #define TD_TER 0x02000000 /* Transmit End Of Ring */
76 #define T_OWN 0x80000000 /* Own Bit */
77 #define TD_LS 0x40000000 /* Last Segment */
78 #define TD_FS 0x20000000 /* First Segment */
79 #define TD_ES 0x00008000 /* Error Summary */
80 #define TD_SET 0x08000000 /* Setup Packet */
82 /* The EEPROM commands include the alway-set leading bit. */
83 #define SROM_WRITE_CMD 5
84 #define SROM_READ_CMD 6
85 #define SROM_ERASE_CMD 7
87 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
88 #define SROM_RD 0x00004000 /* Read from Boot ROM */
89 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
90 #define EE_WRITE_0 0x4801
91 #define EE_WRITE_1 0x4805
92 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
93 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
95 #define DT_IN 0x00000004 /* Serial Data In */
96 #define DT_CLK 0x00000002 /* Serial ROM Clock */
97 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
101 #define RESET_DE4X5(dev) {\
103 i=INL(dev, DE4X5_BMR);\
105 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
107 OUTL(dev, i, DE4X5_BMR);\
109 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
113 #define START_DE4X5(dev) {\
115 omr = INL(dev, DE4X5_OMR);\
116 omr |= OMR_ST | OMR_SR;\
117 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
120 #define STOP_DE4X5(dev) {\
122 omr = INL(dev, DE4X5_OMR);\
123 omr &= ~(OMR_ST|OMR_SR);\
124 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
127 #define NUM_RX_DESC PKTBUFSRX
128 #define NUM_TX_DESC 1 /* Number of TX descriptors */
129 #define RX_BUFF_SZ PKTSIZE_ALIGN
131 #define TOUT_LOOP 1000000
133 #define SETUP_FRAME_LEN 192
144 static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
145 static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
146 static int rx_new; /* RX descriptor ring pointer */
147 static int tx_new; /* TX descriptor ring pointer */
149 static char rxRingSize;
150 static char txRingSize;
152 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
153 static int getfrom_srom(struct eth_device* dev, u_long addr);
154 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len);
155 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len);
156 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
158 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
159 static void update_srom(struct eth_device *dev, bd_t *bis);
161 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
162 static void send_setup_frame(struct eth_device* dev, bd_t * bis);
164 static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
165 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
166 static int dc21x4x_recv(struct eth_device* dev);
167 static void dc21x4x_halt(struct eth_device* dev);
168 #ifdef CONFIG_TULIP_SELECT_MEDIA
169 extern void dc21x4x_select_media(struct eth_device* dev);
172 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
174 static int INL(struct eth_device* dev, u_long addr)
176 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
179 static void OUTL(struct eth_device* dev, int command, u_long addr)
181 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
184 static struct pci_device_id supported[] = {
185 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
186 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
190 int dc21x4x_initialize(bd_t *bis)
198 unsigned short status;
199 struct eth_device* dev;
202 devbusfn = pci_find_devices(supported, idx++);
203 if (devbusfn == -1) {
207 /* Get the chip configuration revision register. */
208 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
210 if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
211 printf("Error: The chip is not DC21143.\n");
215 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
217 #ifdef CONFIG_TULIP_USE_IO
223 pci_write_config_word(devbusfn, PCI_COMMAND, status);
225 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
226 if (!(status & PCI_COMMAND_IO)) {
227 printf("Error: Can not enable I/O access.\n");
231 if (!(status & PCI_COMMAND_IO)) {
232 printf("Error: Can not enable I/O access.\n");
236 if (!(status & PCI_COMMAND_MASTER)) {
237 printf("Error: Can not enable Bus Mastering.\n");
241 /* Check the latency timer for values >= 0x60. */
242 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
245 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
248 #ifdef CONFIG_TULIP_USE_IO
249 /* read BAR for memory space access */
250 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
251 iobase &= PCI_BASE_ADDRESS_IO_MASK;
253 /* read BAR for memory space access */
254 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
255 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
259 printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
262 dev = (struct eth_device*) malloc(sizeof *dev);
264 sprintf(dev->name, "dc21x4x#%d", card_number);
265 #ifdef CONFIG_TULIP_USE_IO
266 dev->iobase = pci_io_to_phys(devbusfn, iobase);
268 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
270 dev->priv = (void*) devbusfn;
271 dev->init = dc21x4x_init;
272 dev->halt = dc21x4x_halt;
273 dev->send = dc21x4x_send;
274 dev->recv = dc21x4x_recv;
276 /* Ensure we're not sleeping. */
277 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
281 read_hw_addr(dev, bis);
291 static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
294 int devbusfn = (int) dev->priv;
296 /* Ensure we're not sleeping. */
297 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
301 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
302 printf("Error: Cannot reset ethernet controller.\n");
306 #ifdef CONFIG_TULIP_SELECT_MEDIA
307 dc21x4x_select_media(dev);
309 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
312 for (i = 0; i < NUM_RX_DESC; i++) {
313 rx_ring[i].status = cpu_to_le32(R_OWN);
314 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
315 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
319 for (i=0; i < NUM_TX_DESC; i++) {
320 tx_ring[i].status = 0;
326 rxRingSize = NUM_RX_DESC;
327 txRingSize = NUM_TX_DESC;
329 /* Write the end of list marker to the descriptor lists. */
330 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
331 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
333 /* Tell the adapter where the TX/RX rings are located. */
334 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
335 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
342 send_setup_frame(dev, bis);
347 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
353 printf("%s: bad packet size: %d\n", dev->name, length);
357 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
358 if (i >= TOUT_LOOP) {
359 printf("%s: tx error buffer not ready\n", dev->name);
364 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
365 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
366 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
368 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
370 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
371 if (i >= TOUT_LOOP) {
372 printf(".%s: tx buffer not ready\n", dev->name);
377 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
378 #if 0 /* test-only */
379 printf("TX error status = 0x%08X\n",
380 le32_to_cpu(tx_ring[tx_new].status));
391 static int dc21x4x_recv(struct eth_device* dev)
397 status = (s32)le32_to_cpu(rx_ring[rx_new].status);
399 if (status & R_OWN) {
403 if (status & RD_LS) {
404 /* Valid frame status.
406 if (status & RD_ES) {
408 /* There was an error.
410 printf("RX error status = 0x%08X\n", status);
412 /* A valid frame received.
414 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
416 /* Pass the packet up to the protocol
419 NetReceive(NetRxPackets[rx_new], length - 4);
422 /* Change buffer ownership for this frame, back
425 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
428 /* Update entry information.
430 rx_new = (rx_new + 1) % rxRingSize;
436 static void dc21x4x_halt(struct eth_device* dev)
438 int devbusfn = (int) dev->priv;
441 OUTL(dev, 0, DE4X5_SICR);
443 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
446 static void send_setup_frame(struct eth_device* dev, bd_t *bis)
449 char setup_frame[SETUP_FRAME_LEN];
450 char *pa = &setup_frame[0];
452 memset(pa, 0xff, SETUP_FRAME_LEN);
454 for (i = 0; i < ETH_ALEN; i++) {
455 *(pa + (i & 1)) = dev->enetaddr[i];
461 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
462 if (i >= TOUT_LOOP) {
463 printf("%s: tx error buffer not ready\n", dev->name);
468 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
469 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
470 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
472 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
474 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
475 if (i >= TOUT_LOOP) {
476 printf("%s: tx buffer not ready\n", dev->name);
481 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
482 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
488 /* SROM Read and write routines.
492 sendto_srom(struct eth_device* dev, u_int command, u_long addr)
494 OUTL(dev, command, addr);
499 getfrom_srom(struct eth_device* dev, u_long addr)
503 tmp = INL(dev, addr);
509 /* Note: this routine returns extra data bits for size detection. */
510 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
514 int read_cmd = location | (SROM_READ_CMD << addr_len);
516 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
517 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
520 printf(" EEPROM read at %d ", location);
523 /* Shift the read command bits out. */
524 for (i = 4 + addr_len; i >= 0; i--) {
525 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
526 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
528 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
531 printf("%X", getfrom_srom(dev, ioaddr) & 15);
533 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
536 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
539 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
542 for (i = 16; i > 0; i--) {
543 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
546 printf("%X", getfrom_srom(dev, ioaddr) & 15);
548 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
549 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
553 /* Terminate the EEPROM access. */
554 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
557 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
563 /* This executes a generic EEPROM command, typically a write or write enable.
564 It returns the data output from the EEPROM, and thus may also be used for
566 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
571 printf(" EEPROM op 0x%x: ", cmd);
574 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
576 /* Shift the command bits out. */
578 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
579 sendto_srom(dev,dataval, ioaddr);
583 printf("%X", getfrom_srom(dev,ioaddr) & 15);
586 sendto_srom(dev,dataval | DT_CLK, ioaddr);
588 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
589 } while (--cmd_len >= 0);
590 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
592 /* Terminate the EEPROM access. */
593 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
596 printf(" EEPROM result is 0x%5.5x.\n", retval);
602 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
604 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
606 return do_eeprom_cmd(dev, ioaddr,
607 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
608 | 0xffff, 3 + ee_addr_size + 16);
612 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
614 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
616 unsigned short newval;
618 udelay(10*1000); /* test-only */
621 printf("ee_addr_size=%d.\n", ee_addr_size);
622 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
625 /* Enable programming modes. */
626 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
628 /* Do the actual write. */
629 do_eeprom_cmd(dev, ioaddr,
630 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
631 3 + ee_addr_size + 16);
633 /* Poll for write finished. */
634 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
635 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
636 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
640 printf(" Write finished after %d ticks.\n", i);
643 /* Disable programming. */
644 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
646 /* And read the result. */
647 newval = do_eeprom_cmd(dev, ioaddr,
648 (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
649 | 0xffff, 3 + ee_addr_size + 16);
651 printf(" New value at offset %d is %4.4x.\n", index, newval);
657 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
659 u_short tmp, *p = (short *)(&dev->enetaddr[0]);
662 for (i = 0; i < (ETH_ALEN >> 1); i++) {
663 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
664 *p = le16_to_cpu(tmp);
668 if ((j == 0) || (j == 0x2fffd)) {
669 memset (dev->enetaddr, 0, ETH_ALEN);
671 printf("Warning: can't read HW address from SROM.\n");
680 update_srom(dev, bis);
686 static void update_srom(struct eth_device *dev, bd_t *bis)
689 static unsigned short eeprom[0x40] = {
690 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
691 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
692 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
693 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
694 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
695 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
696 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
697 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
698 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
699 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
700 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
701 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
702 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
703 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
704 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
705 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
708 /* Ethernet Addr... */
709 eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff);
710 eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff);
711 eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff);
713 for (i=0; i<0x40; i++)
715 write_srom(dev, DE4X5_APROM, i, eeprom[i]);