1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
10 #define CXLMDEV_STATUS_OFFSET 0x0
11 #define CXLMDEV_DEV_FATAL BIT(0)
12 #define CXLMDEV_FW_HALT BIT(1)
13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
14 #define CXLMDEV_MS_NOT_READY 0
15 #define CXLMDEV_MS_READY 1
16 #define CXLMDEV_MS_ERROR 2
17 #define CXLMDEV_MS_DISABLED 3
18 #define CXLMDEV_READY(status) \
19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
21 #define CXLMDEV_MBOX_IF_READY BIT(4)
22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
23 #define CXLMDEV_RESET_NEEDED_NOT 0
24 #define CXLMDEV_RESET_NEEDED_COLD 1
25 #define CXLMDEV_RESET_NEEDED_WARM 2
26 #define CXLMDEV_RESET_NEEDED_HOT 3
27 #define CXLMDEV_RESET_NEEDED_CXL 4
28 #define CXLMDEV_RESET_NEEDED(status) \
29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
30 CXLMDEV_RESET_NEEDED_NOT)
33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
34 * @dev: driver core device object
35 * @cdev: char dev core object for ioctl operations
36 * @cxlds: The device state backing this device
37 * @detach_work: active memdev lost a port in its ancestry
38 * @id: id number of this memdev instance.
43 struct cxl_dev_state *cxlds;
44 struct work_struct detach_work;
48 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
50 return container_of(dev, struct cxl_memdev, dev);
53 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
55 return to_cxl_port(cxled->cxld.dev.parent);
58 static inline struct cxl_memdev *
59 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
61 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
63 return to_cxl_memdev(port->uport);
66 bool is_cxl_memdev(struct device *dev);
67 static inline bool is_cxl_endpoint(struct cxl_port *port)
69 return is_cxl_memdev(port->uport);
72 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
75 * struct cxl_mbox_cmd - A command to be submitted to hardware.
76 * @opcode: (input) The command set and command submitted to hardware.
77 * @payload_in: (input) Pointer to the input payload.
78 * @payload_out: (output) Pointer to the output payload. Must be allocated by
80 * @size_in: (input) Number of bytes to load from @payload_in.
81 * @size_out: (input) Max number of bytes loaded into @payload_out.
82 * (output) Number of bytes generated by the device. For fixed size
83 * outputs commands this is always expected to be deterministic. For
84 * variable sized output commands, it tells the exact number of bytes
86 * @return_code: (output) Error code returned from hardware.
88 * This is the primary mechanism used to send commands to the hardware.
89 * All the fields except @payload_* correspond exactly to the fields described in
90 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
91 * @payload_out are written to, and read from the Command Payload Registers
92 * defined in CXL 2.0 8.2.8.4.8.
104 * Per CXL 2.0 Section 8.2.8.4.5.1
106 #define CMD_CMD_RC_TABLE \
107 C(SUCCESS, 0, NULL), \
108 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
109 C(INPUT, -ENXIO, "cmd input was invalid"), \
110 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
111 C(INTERNAL, -ENXIO, "internal device error"), \
112 C(RETRY, -ENXIO, "temporary error, retry once"), \
113 C(BUSY, -ENXIO, "ongoing background operation"), \
114 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
115 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
116 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
117 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
118 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
119 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
120 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
121 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
122 C(PADDR, -ENXIO, "physical address specified is invalid"), \
123 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
124 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
125 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
126 C(SECURITY, -ENXIO, "not valid in the current security state"), \
127 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
128 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
129 C(PAYLOADLEN, -ENXIO, "invalid payload length")
132 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
133 enum { CMD_CMD_RC_TABLE };
135 #define C(a, b, c) { b, c }
136 struct cxl_mbox_cmd_rc {
142 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
145 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
147 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
150 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
152 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
156 * CXL 2.0 - Memory capacity multiplier
157 * See Section 8.2.9.5
159 * Volatile, Persistent, and Partition capacities are specified to be in
160 * multiples of 256MB - define a multiplier to convert to/from bytes.
162 #define CXL_CAPACITY_MULTIPLIER SZ_256M
165 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
166 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
167 * @ranges: Number of active HDM ranges this device uses.
168 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
170 struct cxl_endpoint_dvsec_info {
173 struct range dvsec_range[2];
177 * struct cxl_dev_state - The driver device state
179 * cxl_dev_state represents the CXL driver/device state. It provides an
180 * interface to mailbox commands as well as some cached data about the device.
181 * Currently only memory devices are represented.
183 * @dev: The device associated with this CXL state
184 * @regs: Parsed register blocks
185 * @cxl_dvsec: Offset to the PCIe device DVSEC
186 * @payload_size: Size of space for payload
187 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
188 * @lsa_size: Size of Label Storage Area
189 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
190 * @mbox_mutex: Mutex to synchronize mailbox access.
191 * @firmware_version: Firmware version for the memory device.
192 * @enabled_cmds: Hardware commands found enabled in CEL.
193 * @exclusive_cmds: Commands that are kernel-internal only
194 * @dpa_res: Overall DPA resource tree for the device
195 * @pmem_res: Active Persistent memory capacity configuration
196 * @ram_res: Active Volatile memory capacity configuration
197 * @total_bytes: sum of all possible capacities
198 * @volatile_only_bytes: hard volatile capacity
199 * @persistent_only_bytes: hard persistent capacity
200 * @partition_align_bytes: alignment size for partition-able capacity
201 * @active_volatile_bytes: sum of hard + soft volatile
202 * @active_persistent_bytes: sum of hard + soft persistent
203 * @next_volatile_bytes: volatile capacity change pending device reset
204 * @next_persistent_bytes: persistent capacity change pending device reset
205 * @component_reg_phys: register base of component registers
206 * @info: Cached DVSEC information about the device.
207 * @serial: PCIe Device Serial Number
208 * @doe_mbs: PCI DOE mailbox array
209 * @mbox_send: @dev specific transport for transmitting mailbox commands
211 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
212 * details on capacity parameters.
214 struct cxl_dev_state {
217 struct cxl_regs regs;
222 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
223 char firmware_version[0x10];
224 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
225 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
227 struct resource dpa_res;
228 struct resource pmem_res;
229 struct resource ram_res;
231 u64 volatile_only_bytes;
232 u64 persistent_only_bytes;
233 u64 partition_align_bytes;
235 u64 active_volatile_bytes;
236 u64 active_persistent_bytes;
237 u64 next_volatile_bytes;
238 u64 next_persistent_bytes;
240 resource_size_t component_reg_phys;
243 struct xarray doe_mbs;
245 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
249 CXL_MBOX_OP_INVALID = 0x0000,
250 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
251 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
252 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
253 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
254 CXL_MBOX_OP_GET_LOG = 0x0401,
255 CXL_MBOX_OP_IDENTIFY = 0x4000,
256 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
257 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
258 CXL_MBOX_OP_GET_LSA = 0x4102,
259 CXL_MBOX_OP_SET_LSA = 0x4103,
260 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
261 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
262 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
263 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
264 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
265 CXL_MBOX_OP_GET_POISON = 0x4300,
266 CXL_MBOX_OP_INJECT_POISON = 0x4301,
267 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
268 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
269 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
270 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
271 CXL_MBOX_OP_MAX = 0x10000
274 #define DEFINE_CXL_CEL_UUID \
275 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
278 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
279 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
282 struct cxl_mbox_get_supported_logs {
285 struct cxl_gsl_entry {
291 struct cxl_cel_entry {
296 struct cxl_mbox_get_log {
302 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
303 struct cxl_mbox_identify {
304 char fw_revision[0x10];
305 __le64 total_capacity;
306 __le64 volatile_capacity;
307 __le64 persistent_capacity;
308 __le64 partition_align;
309 __le16 info_event_log_size;
310 __le16 warning_event_log_size;
311 __le16 failure_event_log_size;
312 __le16 fatal_event_log_size;
314 u8 poison_list_max_mer[3];
315 __le16 inject_poison_limit;
317 u8 qos_telemetry_caps;
320 struct cxl_mbox_get_partition_info {
321 __le64 active_volatile_cap;
322 __le64 active_persistent_cap;
323 __le64 next_volatile_cap;
324 __le64 next_persistent_cap;
327 struct cxl_mbox_get_lsa {
332 struct cxl_mbox_set_lsa {
338 struct cxl_mbox_set_partition_info {
339 __le64 volatile_capacity;
343 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
346 * struct cxl_mem_command - Driver representation of a memory device command
347 * @info: Command information as it exists for the UAPI
348 * @opcode: The actual bits used for the mailbox protocol
349 * @flags: Set of flags effecting driver behavior.
351 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
352 * will be enabled by the driver regardless of what hardware may have
355 * The cxl_mem_command is the driver's internal representation of commands that
356 * are supported by the driver. Some of these commands may not be supported by
357 * the hardware. The driver will use @info to validate the fields passed in by
358 * the user then submit the @opcode to the hardware.
360 * See struct cxl_command_info.
362 struct cxl_mem_command {
363 struct cxl_command_info info;
364 enum cxl_opcode opcode;
366 #define CXL_CMD_FLAG_NONE 0
367 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
370 int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in,
371 size_t in_size, void *out, size_t out_size);
372 int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
373 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
374 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
375 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
376 struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
377 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
378 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
379 #ifdef CONFIG_CXL_SUSPEND
380 void cxl_mem_active_inc(void);
381 void cxl_mem_active_dec(void);
383 static inline void cxl_mem_active_inc(void)
386 static inline void cxl_mem_active_dec(void)
392 struct cxl_component_regs regs;
393 unsigned int decoder_count;
394 unsigned int target_count;
395 unsigned int interleave_mask;
396 struct cxl_port *port;
400 struct dentry *cxl_debugfs_create_dir(const char *dir);
401 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
402 #endif /* __CXL_MEM_H__ */