1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/log2.h>
16 * The CXL core objects like ports, decoders, and regions are shared
17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
18 * (port-driver, region-driver, nvdimm object-drivers... etc).
21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
25 #define CXL_CM_OFFSET 0x1000
26 #define CXL_CM_CAP_HDR_OFFSET 0x0
27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
28 #define CM_CAP_HDR_CAP_ID 1
29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
30 #define CM_CAP_HDR_CAP_VERSION 1
31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
36 #define CXL_CM_CAP_CAP_ID_RAS 0x2
37 #define CXL_CM_CAP_CAP_ID_HDM 0x5
38 #define CXL_CM_CAP_CAP_HDM_VERSION 1
40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4
47 #define CXL_HDM_DECODER_ENABLE BIT(1)
48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
59 #define CXL_HDM_DECODER0_CTRL_TYPE BIT(12)
60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
66 #define CXL_DECODER_MIN_GRANULARITY 256
67 #define CXL_DECODER_MAX_ENCODED_IG 6
69 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
73 return val ? val * 2 : 1;
76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
79 if (eig > CXL_DECODER_MAX_ENCODED_IG)
81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig;
85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
93 *ways = 3 << (eiw - 8);
102 static inline int granularity_to_eig(int granularity, u16 *eig)
104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY ||
105 !is_power_of_2(granularity))
107 *eig = ilog2(granularity) - 8;
111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
115 if (is_power_of_2(ways)) {
122 if (!is_power_of_2(ways))
124 *eiw = ilog2(ways) + 8;
128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8)
134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14
141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18
143 #define CXL_RAS_CAPABILITY_LENGTH 0x58
144 #define CXL_HEADERLOG_SIZE SZ_512
145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
149 #define CXLDEV_CAP_ARRAY_CAP_ID 0
150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
160 /* CXL 2.0 8.2.8.4 Mailbox Registers */
161 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
162 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
163 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
164 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
165 #define CXLDEV_MBOX_CMD_OFFSET 0x08
166 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
167 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
168 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
169 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
170 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
171 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
174 * Using struct_group() allows for per register-block-type helper routines,
175 * without requiring block-type agnostic code to include the prefix.
179 * Common set of CXL Component register block base pointers
180 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
181 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
183 struct_group_tagged(cxl_component_regs, component,
184 void __iomem *hdm_decoder;
188 * Common set of CXL Device register block base pointers
189 * @status: CXL 2.0 8.2.8.3 Device Status Registers
190 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
191 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
193 struct_group_tagged(cxl_device_regs, device_regs,
194 void __iomem *status, *mbox, *memdev;
201 unsigned long offset;
205 struct cxl_component_reg_map {
206 struct cxl_reg_map hdm_decoder;
207 struct cxl_reg_map ras;
210 struct cxl_device_reg_map {
211 struct cxl_reg_map status;
212 struct cxl_reg_map mbox;
213 struct cxl_reg_map memdev;
217 * struct cxl_register_map - DVSEC harvested register block mapping parameters
218 * @base: virtual base of the register-block-BAR + @block_offset
219 * @resource: physical resource base of the register block
220 * @max_size: maximum mapping size to perform register search
221 * @reg_type: see enum cxl_regloc_type
222 * @component_map: cxl_reg_map for component registers
223 * @device_map: cxl_reg_maps for device registers
225 struct cxl_register_map {
227 resource_size_t resource;
228 resource_size_t max_size;
231 struct cxl_component_reg_map component_map;
232 struct cxl_device_reg_map device_map;
236 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
237 struct cxl_component_reg_map *map);
238 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
239 struct cxl_device_reg_map *map);
240 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
241 struct cxl_register_map *map,
242 unsigned long map_mask);
243 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
244 struct cxl_register_map *map);
246 enum cxl_regloc_type;
247 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
248 struct cxl_register_map *map);
254 resource_size_t cxl_rcrb_to_component(struct device *dev,
255 resource_size_t rcrb,
256 enum cxl_rcrb which);
258 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
259 #define CXL_TARGET_STRLEN 20
262 * cxl_decoder flags that define the type of memory / devices this
263 * decoder supports as well as configuration lock status See "CXL 2.0
264 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
266 #define CXL_DECODER_F_RAM BIT(0)
267 #define CXL_DECODER_F_PMEM BIT(1)
268 #define CXL_DECODER_F_TYPE2 BIT(2)
269 #define CXL_DECODER_F_TYPE3 BIT(3)
270 #define CXL_DECODER_F_LOCK BIT(4)
271 #define CXL_DECODER_F_ENABLE BIT(5)
272 #define CXL_DECODER_F_MASK GENMASK(5, 0)
274 enum cxl_decoder_type {
275 CXL_DECODER_ACCELERATOR = 2,
276 CXL_DECODER_EXPANDER = 3,
280 * Current specification goes up to 8, double that seems a reasonable
281 * software max for the foreseeable future
283 #define CXL_DECODER_MAX_INTERLEAVE 16
287 * struct cxl_decoder - Common CXL HDM Decoder Attributes
288 * @dev: this decoder's device
289 * @id: kernel device name id
290 * @hpa_range: Host physical address range mapped by this decoder
291 * @interleave_ways: number of cxl_dports in this decode
292 * @interleave_granularity: data stride per dport
293 * @target_type: accelerator vs expander (type2 vs type3) selector
294 * @region: currently assigned region for this decoder
295 * @flags: memory type capabilities and locking
296 * @commit: device/decoder-type specific callback to commit settings to hw
297 * @reset: device/decoder-type specific callback to reset hw settings
302 struct range hpa_range;
304 int interleave_granularity;
305 enum cxl_decoder_type target_type;
306 struct cxl_region *region;
308 int (*commit)(struct cxl_decoder *cxld);
309 int (*reset)(struct cxl_decoder *cxld);
313 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions
314 * while cxld_unregister() is running
316 enum cxl_decoder_mode {
325 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
326 * @cxld: base cxl_decoder_object
327 * @dpa_res: actively claimed DPA span of this decoder
328 * @skip: offset into @dpa_res where @cxld.hpa_range maps
329 * @mode: which memory type / access-mode-partition this decoder targets
330 * @pos: interleave position in @cxld.region
332 struct cxl_endpoint_decoder {
333 struct cxl_decoder cxld;
334 struct resource *dpa_res;
335 resource_size_t skip;
336 enum cxl_decoder_mode mode;
341 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
342 * @cxld: base cxl_decoder object
343 * @target_lock: coordinate coherent reads of the target list
344 * @nr_targets: number of elements in @target
345 * @target: active ordered target list in current decoder configuration
347 * The 'switch' decoder type represents the decoder instances of cxl_port's that
348 * route from the root of a CXL memory decode topology to the endpoints. They
349 * come in two flavors, root-level decoders, statically defined by platform
350 * firmware, and mid-level decoders, where interleave-granularity,
351 * interleave-width, and the target list are mutable.
353 struct cxl_switch_decoder {
354 struct cxl_decoder cxld;
355 seqlock_t target_lock;
357 struct cxl_dport *target[];
360 struct cxl_root_decoder;
361 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd,
365 * struct cxl_root_decoder - Static platform CXL address decoder
366 * @res: host / parent resource for region allocations
367 * @region_id: region id for next region provisioning event
368 * @calc_hb: which host bridge covers the n'th position by granularity
369 * @platform_data: platform specific configuration data
370 * @cxlsd: base cxl switch decoder
372 struct cxl_root_decoder {
373 struct resource *res;
375 cxl_calc_hb_fn calc_hb;
377 struct cxl_switch_decoder cxlsd;
381 * enum cxl_config_state - State machine for region configuration
382 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
383 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
384 * changes to interleave_ways or interleave_granularity
385 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now
387 * @CXL_CONFIG_RESET_PENDING: see commit_store()
388 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
390 enum cxl_config_state {
392 CXL_CONFIG_INTERLEAVE_ACTIVE,
394 CXL_CONFIG_RESET_PENDING,
399 * struct cxl_region_params - region settings
400 * @state: allow the driver to lockdown further parameter changes
401 * @uuid: unique id for persistent regions
402 * @interleave_ways: number of endpoints in the region
403 * @interleave_granularity: capacity each endpoint contributes to a stripe
404 * @res: allocated iomem capacity for this region
405 * @targets: active ordered targets in current decoder configuration
406 * @nr_targets: number of targets
408 * State transitions are protected by the cxl_region_rwsem
410 struct cxl_region_params {
411 enum cxl_config_state state;
414 int interleave_granularity;
415 struct resource *res;
416 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
421 * Flag whether this region needs to have its HPA span synchronized with
422 * CPU cache state at region activation time.
424 #define CXL_REGION_F_INCOHERENT 0
427 * struct cxl_region - CXL region
428 * @dev: This region's device
429 * @id: This region's id. Id is globally unique across all regions
430 * @mode: Endpoint decoder allocation / access mode
431 * @type: Endpoint decoder target type
432 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
433 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge
434 * @flags: Region state flags
435 * @params: active + config params for the region
440 enum cxl_decoder_mode mode;
441 enum cxl_decoder_type type;
442 struct cxl_nvdimm_bridge *cxl_nvb;
443 struct cxl_pmem_region *cxlr_pmem;
445 struct cxl_region_params params;
448 struct cxl_nvdimm_bridge {
451 struct cxl_port *port;
452 struct nvdimm_bus *nvdimm_bus;
453 struct nvdimm_bus_descriptor nd_desc;
456 #define CXL_DEV_ID_LEN 19
460 struct cxl_memdev *cxlmd;
461 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
464 struct cxl_pmem_region_mapping {
465 struct cxl_memdev *cxlmd;
466 struct cxl_nvdimm *cxl_nvd;
472 struct cxl_pmem_region {
474 struct cxl_region *cxlr;
475 struct nd_region *nd_region;
476 struct range hpa_range;
478 struct cxl_pmem_region_mapping mapping[];
482 * struct cxl_port - logical collection of upstream port devices and
483 * downstream port devices to construct a CXL memory
485 * @dev: this port's device
486 * @uport: PCI or platform device implementing the upstream port capability
487 * @host_bridge: Shortcut to the platform attach point for this port
488 * @id: id for port device-name
489 * @dports: cxl_dport instances referenced by decoders
490 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
491 * @regions: cxl_region_ref instances, regions mapped by this port
492 * @parent_dport: dport that points to this port in the parent
493 * @decoder_ida: allocator for decoder ids
494 * @nr_dports: number of entries in @dports
495 * @hdm_end: track last allocated HDM decoder instance for allocation ordering
496 * @commit_end: cursor to track highest committed decoder for commit ordering
497 * @component_reg_phys: component register capability base address (optional)
498 * @dead: last ep has been removed, force port re-creation
499 * @depth: How deep this port is relative to the root. depth 0 is the root.
500 * @cdat: Cached CDAT data
501 * @cdat_available: Should a CDAT attribute be available in sysfs
505 struct device *uport;
506 struct device *host_bridge;
508 struct xarray dports;
509 struct xarray endpoints;
510 struct xarray regions;
511 struct cxl_dport *parent_dport;
512 struct ida decoder_ida;
516 resource_size_t component_reg_phys;
526 static inline struct cxl_dport *
527 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
529 return xa_load(&port->dports, (unsigned long)dport_dev);
533 * struct cxl_dport - CXL downstream port
534 * @dport: PCI bridge or firmware device representing the downstream link
535 * @port_id: unique hardware identifier for dport in decoder target list
536 * @component_reg_phys: downstream port component registers
537 * @rcrb: base address for the Root Complex Register Block
538 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
539 * @port: reference to cxl_port that contains this downstream port
542 struct device *dport;
544 resource_size_t component_reg_phys;
545 resource_size_t rcrb;
547 struct cxl_port *port;
551 * struct cxl_ep - track an endpoint's interest in a port
552 * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
553 * @dport: which dport routes to this endpoint on @port
554 * @next: cxl switch port across the link attached to @dport NULL if
555 * attached to an endpoint
559 struct cxl_dport *dport;
560 struct cxl_port *next;
564 * struct cxl_region_ref - track a region's interest in a port
565 * @port: point in topology to install this reference
566 * @decoder: decoder assigned for @region in @port
567 * @region: region for this reference
568 * @endpoints: cxl_ep references for region members beneath @port
569 * @nr_targets_set: track how many targets have been programmed during setup
570 * @nr_eps: number of endpoints beneath @port
571 * @nr_targets: number of distinct targets needed to reach @nr_eps
573 struct cxl_region_ref {
574 struct cxl_port *port;
575 struct cxl_decoder *decoder;
576 struct cxl_region *region;
577 struct xarray endpoints;
584 * The platform firmware device hosting the root is also the top of the
585 * CXL port topology. All other CXL ports have another CXL port as their
586 * parent and their ->uport / host device is out-of-line of the port
589 static inline bool is_cxl_root(struct cxl_port *port)
591 return port->uport == port->dev.parent;
594 bool is_cxl_port(struct device *dev);
595 struct cxl_port *to_cxl_port(struct device *dev);
597 int devm_cxl_register_pci_bus(struct device *host, struct device *uport,
598 struct pci_bus *bus);
599 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
600 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
601 resource_size_t component_reg_phys,
602 struct cxl_dport *parent_dport);
603 struct cxl_port *find_cxl_root(struct device *dev);
604 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
605 void cxl_bus_rescan(void);
606 void cxl_bus_drain(void);
607 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
608 struct cxl_dport **dport);
609 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
611 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
612 struct device *dport, int port_id,
613 resource_size_t component_reg_phys);
614 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
615 struct device *dport_dev, int port_id,
616 resource_size_t component_reg_phys,
617 resource_size_t rcrb);
619 struct cxl_decoder *to_cxl_decoder(struct device *dev);
620 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
621 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
622 bool is_root_decoder(struct device *dev);
623 bool is_endpoint_decoder(struct device *dev);
624 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
625 unsigned int nr_targets,
626 cxl_calc_hb_fn calc_hb);
627 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos);
628 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
629 unsigned int nr_targets);
630 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
631 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
632 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
633 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
634 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
637 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port);
638 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm);
639 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
641 bool is_cxl_region(struct device *dev);
643 extern struct bus_type cxl_bus_type;
647 int (*probe)(struct device *dev);
648 void (*remove)(struct device *dev);
649 struct device_driver drv;
653 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
655 return container_of(drv, struct cxl_driver, drv);
658 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
659 const char *modname);
660 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
661 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
663 #define module_cxl_driver(__cxl_driver) \
664 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
666 #define CXL_DEVICE_NVDIMM_BRIDGE 1
667 #define CXL_DEVICE_NVDIMM 2
668 #define CXL_DEVICE_PORT 3
669 #define CXL_DEVICE_ROOT 4
670 #define CXL_DEVICE_MEMORY_EXPANDER 5
671 #define CXL_DEVICE_REGION 6
672 #define CXL_DEVICE_PMEM_REGION 7
674 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
675 #define CXL_MODALIAS_FMT "cxl:t%d"
677 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
678 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
679 struct cxl_port *port);
680 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
681 bool is_cxl_nvdimm(struct device *dev);
682 bool is_cxl_nvdimm_bridge(struct device *dev);
683 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd);
684 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct device *dev);
686 #ifdef CONFIG_CXL_REGION
687 bool is_cxl_pmem_region(struct device *dev);
688 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
690 static inline bool is_cxl_pmem_region(struct device *dev)
694 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
701 * Unit test builds overrides this to __weak, find the 'strong' version
702 * of these symbols in tools/testing/cxl/.
705 #define __mock static
708 #endif /* __CXL_H__ */