1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
7 #include <linux/libnvdimm.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/log2.h>
16 * The CXL core objects like ports, decoders, and regions are shared
17 * between the subsystem drivers cxl_acpi, cxl_pci, and core drivers
18 * (port-driver, region-driver, nvdimm object-drivers... etc).
21 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
22 #define CXL_COMPONENT_REG_BLOCK_SIZE SZ_64K
24 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
25 #define CXL_CM_OFFSET 0x1000
26 #define CXL_CM_CAP_HDR_OFFSET 0x0
27 #define CXL_CM_CAP_HDR_ID_MASK GENMASK(15, 0)
28 #define CM_CAP_HDR_CAP_ID 1
29 #define CXL_CM_CAP_HDR_VERSION_MASK GENMASK(19, 16)
30 #define CM_CAP_HDR_CAP_VERSION 1
31 #define CXL_CM_CAP_HDR_CACHE_MEM_VERSION_MASK GENMASK(23, 20)
32 #define CM_CAP_HDR_CACHE_MEM_VERSION 1
33 #define CXL_CM_CAP_HDR_ARRAY_SIZE_MASK GENMASK(31, 24)
34 #define CXL_CM_CAP_PTR_MASK GENMASK(31, 20)
36 #define CXL_CM_CAP_CAP_ID_RAS 0x2
37 #define CXL_CM_CAP_CAP_ID_HDM 0x5
38 #define CXL_CM_CAP_CAP_HDM_VERSION 1
40 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
41 #define CXL_HDM_DECODER_CAP_OFFSET 0x0
42 #define CXL_HDM_DECODER_COUNT_MASK GENMASK(3, 0)
43 #define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
44 #define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
45 #define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
46 #define CXL_HDM_DECODER_CTRL_OFFSET 0x4
47 #define CXL_HDM_DECODER_ENABLE BIT(1)
48 #define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
49 #define CXL_HDM_DECODER0_BASE_HIGH_OFFSET(i) (0x20 * (i) + 0x14)
50 #define CXL_HDM_DECODER0_SIZE_LOW_OFFSET(i) (0x20 * (i) + 0x18)
51 #define CXL_HDM_DECODER0_SIZE_HIGH_OFFSET(i) (0x20 * (i) + 0x1c)
52 #define CXL_HDM_DECODER0_CTRL_OFFSET(i) (0x20 * (i) + 0x20)
53 #define CXL_HDM_DECODER0_CTRL_IG_MASK GENMASK(3, 0)
54 #define CXL_HDM_DECODER0_CTRL_IW_MASK GENMASK(7, 4)
55 #define CXL_HDM_DECODER0_CTRL_LOCK BIT(8)
56 #define CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)
57 #define CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)
58 #define CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)
59 #define CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12)
60 #define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)
61 #define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)
62 #define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)
63 #define CXL_HDM_DECODER0_SKIP_HIGH(i) CXL_HDM_DECODER0_TL_HIGH(i)
65 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
66 #define CXL_DECODER_MIN_GRANULARITY 256
67 #define CXL_DECODER_MAX_ENCODED_IG 6
69 static inline int cxl_hdm_decoder_count(u32 cap_hdr)
71 int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
73 return val ? val * 2 : 1;
76 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
77 static inline int eig_to_granularity(u16 eig, unsigned int *granularity)
79 if (eig > CXL_DECODER_MAX_ENCODED_IG)
81 *granularity = CXL_DECODER_MIN_GRANULARITY << eig;
85 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
86 static inline int eiw_to_ways(u8 eiw, unsigned int *ways)
93 *ways = 3 << (eiw - 8);
102 static inline int granularity_to_eig(int granularity, u16 *eig)
104 if (granularity > SZ_16K || granularity < CXL_DECODER_MIN_GRANULARITY ||
105 !is_power_of_2(granularity))
107 *eig = ilog2(granularity) - 8;
111 static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
115 if (is_power_of_2(ways)) {
122 if (!is_power_of_2(ways))
124 *eiw = ilog2(ways) + 8;
128 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
129 #define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
130 #define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
131 #define CXL_RAS_UNCORRECTABLE_MASK_OFFSET 0x4
132 #define CXL_RAS_UNCORRECTABLE_MASK_MASK (GENMASK(16, 14) | GENMASK(11, 0))
133 #define CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK BIT(8)
134 #define CXL_RAS_UNCORRECTABLE_SEVERITY_OFFSET 0x8
135 #define CXL_RAS_UNCORRECTABLE_SEVERITY_MASK (GENMASK(16, 14) | GENMASK(11, 0))
136 #define CXL_RAS_CORRECTABLE_STATUS_OFFSET 0xC
137 #define CXL_RAS_CORRECTABLE_STATUS_MASK GENMASK(6, 0)
138 #define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
139 #define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
140 #define CXL_RAS_CAP_CONTROL_OFFSET 0x14
141 #define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
142 #define CXL_RAS_HEADER_LOG_OFFSET 0x18
143 #define CXL_RAS_CAPABILITY_LENGTH 0x58
144 #define CXL_HEADERLOG_SIZE SZ_512
145 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32)
147 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
148 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
149 #define CXLDEV_CAP_ARRAY_CAP_ID 0
150 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
151 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
152 /* CXL 2.0 8.2.8.2 CXL Device Capability Header Register */
153 #define CXLDEV_CAP_HDR_CAP_ID_MASK GENMASK(15, 0)
154 /* CXL 2.0 8.2.8.2.1 CXL Device Capabilities */
155 #define CXLDEV_CAP_CAP_ID_DEVICE_STATUS 0x1
156 #define CXLDEV_CAP_CAP_ID_PRIMARY_MAILBOX 0x2
157 #define CXLDEV_CAP_CAP_ID_SECONDARY_MAILBOX 0x3
158 #define CXLDEV_CAP_CAP_ID_MEMDEV 0x4000
160 /* CXL 3.0 8.2.8.3.1 Event Status Register */
161 #define CXLDEV_DEV_EVENT_STATUS_OFFSET 0x00
162 #define CXLDEV_EVENT_STATUS_INFO BIT(0)
163 #define CXLDEV_EVENT_STATUS_WARN BIT(1)
164 #define CXLDEV_EVENT_STATUS_FAIL BIT(2)
165 #define CXLDEV_EVENT_STATUS_FATAL BIT(3)
167 #define CXLDEV_EVENT_STATUS_ALL (CXLDEV_EVENT_STATUS_INFO | \
168 CXLDEV_EVENT_STATUS_WARN | \
169 CXLDEV_EVENT_STATUS_FAIL | \
170 CXLDEV_EVENT_STATUS_FATAL)
172 /* CXL rev 3.0 section 8.2.9.2.4; Table 8-52 */
173 #define CXLDEV_EVENT_INT_MODE_MASK GENMASK(1, 0)
174 #define CXLDEV_EVENT_INT_MSGNUM_MASK GENMASK(7, 4)
176 /* CXL 2.0 8.2.8.4 Mailbox Registers */
177 #define CXLDEV_MBOX_CAPS_OFFSET 0x00
178 #define CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
179 #define CXLDEV_MBOX_CAP_BG_CMD_IRQ BIT(6)
180 #define CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)
181 #define CXLDEV_MBOX_CTRL_OFFSET 0x04
182 #define CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
183 #define CXLDEV_MBOX_CTRL_BG_CMD_IRQ BIT(2)
184 #define CXLDEV_MBOX_CMD_OFFSET 0x08
185 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
186 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
187 #define CXLDEV_MBOX_STATUS_OFFSET 0x10
188 #define CXLDEV_MBOX_STATUS_BG_CMD BIT(0)
189 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
190 #define CXLDEV_MBOX_BG_CMD_STATUS_OFFSET 0x18
191 #define CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
192 #define CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK GENMASK_ULL(22, 16)
193 #define CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK GENMASK_ULL(47, 32)
194 #define CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
195 #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
198 * Using struct_group() allows for per register-block-type helper routines,
199 * without requiring block-type agnostic code to include the prefix.
203 * Common set of CXL Component register block base pointers
204 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
205 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
207 struct_group_tagged(cxl_component_regs, component,
208 void __iomem *hdm_decoder;
212 * Common set of CXL Device register block base pointers
213 * @status: CXL 2.0 8.2.8.3 Device Status Registers
214 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
215 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
217 struct_group_tagged(cxl_device_regs, device_regs,
218 void __iomem *status, *mbox, *memdev;
225 unsigned long offset;
229 struct cxl_component_reg_map {
230 struct cxl_reg_map hdm_decoder;
231 struct cxl_reg_map ras;
234 struct cxl_device_reg_map {
235 struct cxl_reg_map status;
236 struct cxl_reg_map mbox;
237 struct cxl_reg_map memdev;
241 * struct cxl_register_map - DVSEC harvested register block mapping parameters
242 * @base: virtual base of the register-block-BAR + @block_offset
243 * @resource: physical resource base of the register block
244 * @max_size: maximum mapping size to perform register search
245 * @reg_type: see enum cxl_regloc_type
246 * @component_map: cxl_reg_map for component registers
247 * @device_map: cxl_reg_maps for device registers
249 struct cxl_register_map {
251 resource_size_t resource;
252 resource_size_t max_size;
255 struct cxl_component_reg_map component_map;
256 struct cxl_device_reg_map device_map;
260 void cxl_probe_component_regs(struct device *dev, void __iomem *base,
261 struct cxl_component_reg_map *map);
262 void cxl_probe_device_regs(struct device *dev, void __iomem *base,
263 struct cxl_device_reg_map *map);
264 int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
265 const struct cxl_register_map *map,
266 unsigned long map_mask);
267 int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
268 const struct cxl_register_map *map);
270 enum cxl_regloc_type;
271 int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
272 struct cxl_register_map *map);
278 resource_size_t cxl_rcrb_to_component(struct device *dev,
279 resource_size_t rcrb,
280 enum cxl_rcrb which);
282 #define CXL_RESOURCE_NONE ((resource_size_t) -1)
283 #define CXL_TARGET_STRLEN 20
286 * cxl_decoder flags that define the type of memory / devices this
287 * decoder supports as well as configuration lock status See "CXL 2.0
288 * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details.
289 * Additionally indicate whether decoder settings were autodetected,
292 #define CXL_DECODER_F_RAM BIT(0)
293 #define CXL_DECODER_F_PMEM BIT(1)
294 #define CXL_DECODER_F_TYPE2 BIT(2)
295 #define CXL_DECODER_F_TYPE3 BIT(3)
296 #define CXL_DECODER_F_LOCK BIT(4)
297 #define CXL_DECODER_F_ENABLE BIT(5)
298 #define CXL_DECODER_F_MASK GENMASK(5, 0)
300 enum cxl_decoder_type {
301 CXL_DECODER_DEVMEM = 2,
302 CXL_DECODER_HOSTONLYMEM = 3,
306 * Current specification goes up to 8, double that seems a reasonable
307 * software max for the foreseeable future
309 #define CXL_DECODER_MAX_INTERLEAVE 16
313 * struct cxl_decoder - Common CXL HDM Decoder Attributes
314 * @dev: this decoder's device
315 * @id: kernel device name id
316 * @hpa_range: Host physical address range mapped by this decoder
317 * @interleave_ways: number of cxl_dports in this decode
318 * @interleave_granularity: data stride per dport
319 * @target_type: accelerator vs expander (type2 vs type3) selector
320 * @region: currently assigned region for this decoder
321 * @flags: memory type capabilities and locking
322 * @commit: device/decoder-type specific callback to commit settings to hw
323 * @reset: device/decoder-type specific callback to reset hw settings
328 struct range hpa_range;
330 int interleave_granularity;
331 enum cxl_decoder_type target_type;
332 struct cxl_region *region;
334 int (*commit)(struct cxl_decoder *cxld);
335 int (*reset)(struct cxl_decoder *cxld);
339 * CXL_DECODER_DEAD prevents endpoints from being reattached to regions
340 * while cxld_unregister() is running
342 enum cxl_decoder_mode {
350 static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode)
352 static const char * const names[] = {
353 [CXL_DECODER_NONE] = "none",
354 [CXL_DECODER_RAM] = "ram",
355 [CXL_DECODER_PMEM] = "pmem",
356 [CXL_DECODER_MIXED] = "mixed",
359 if (mode >= CXL_DECODER_NONE && mode <= CXL_DECODER_MIXED)
365 * Track whether this decoder is reserved for region autodiscovery, or
366 * free for userspace provisioning.
368 enum cxl_decoder_state {
369 CXL_DECODER_STATE_MANUAL,
370 CXL_DECODER_STATE_AUTO,
374 * struct cxl_endpoint_decoder - Endpoint / SPA to DPA decoder
375 * @cxld: base cxl_decoder_object
376 * @dpa_res: actively claimed DPA span of this decoder
377 * @skip: offset into @dpa_res where @cxld.hpa_range maps
378 * @mode: which memory type / access-mode-partition this decoder targets
379 * @state: autodiscovery state
380 * @pos: interleave position in @cxld.region
382 struct cxl_endpoint_decoder {
383 struct cxl_decoder cxld;
384 struct resource *dpa_res;
385 resource_size_t skip;
386 enum cxl_decoder_mode mode;
387 enum cxl_decoder_state state;
392 * struct cxl_switch_decoder - Switch specific CXL HDM Decoder
393 * @cxld: base cxl_decoder object
394 * @target_lock: coordinate coherent reads of the target list
395 * @nr_targets: number of elements in @target
396 * @target: active ordered target list in current decoder configuration
398 * The 'switch' decoder type represents the decoder instances of cxl_port's that
399 * route from the root of a CXL memory decode topology to the endpoints. They
400 * come in two flavors, root-level decoders, statically defined by platform
401 * firmware, and mid-level decoders, where interleave-granularity,
402 * interleave-width, and the target list are mutable.
404 struct cxl_switch_decoder {
405 struct cxl_decoder cxld;
406 seqlock_t target_lock;
408 struct cxl_dport *target[];
411 struct cxl_root_decoder;
412 typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd,
416 * struct cxl_root_decoder - Static platform CXL address decoder
417 * @res: host / parent resource for region allocations
418 * @region_id: region id for next region provisioning event
419 * @calc_hb: which host bridge covers the n'th position by granularity
420 * @platform_data: platform specific configuration data
421 * @range_lock: sync region autodiscovery by address range
422 * @cxlsd: base cxl switch decoder
424 struct cxl_root_decoder {
425 struct resource *res;
427 cxl_calc_hb_fn calc_hb;
429 struct mutex range_lock;
430 struct cxl_switch_decoder cxlsd;
434 * enum cxl_config_state - State machine for region configuration
435 * @CXL_CONFIG_IDLE: Any sysfs attribute can be written freely
436 * @CXL_CONFIG_INTERLEAVE_ACTIVE: region size has been set, no more
437 * changes to interleave_ways or interleave_granularity
438 * @CXL_CONFIG_ACTIVE: All targets have been added the region is now
440 * @CXL_CONFIG_RESET_PENDING: see commit_store()
441 * @CXL_CONFIG_COMMIT: Soft-config has been committed to hardware
443 enum cxl_config_state {
445 CXL_CONFIG_INTERLEAVE_ACTIVE,
447 CXL_CONFIG_RESET_PENDING,
452 * struct cxl_region_params - region settings
453 * @state: allow the driver to lockdown further parameter changes
454 * @uuid: unique id for persistent regions
455 * @interleave_ways: number of endpoints in the region
456 * @interleave_granularity: capacity each endpoint contributes to a stripe
457 * @res: allocated iomem capacity for this region
458 * @targets: active ordered targets in current decoder configuration
459 * @nr_targets: number of targets
461 * State transitions are protected by the cxl_region_rwsem
463 struct cxl_region_params {
464 enum cxl_config_state state;
467 int interleave_granularity;
468 struct resource *res;
469 struct cxl_endpoint_decoder *targets[CXL_DECODER_MAX_INTERLEAVE];
474 * Indicate whether this region has been assembled by autodetection or
475 * userspace assembly. Prevent endpoint decoders outside of automatic
476 * detection from being added to the region.
478 #define CXL_REGION_F_AUTO 0
481 * Require that a committed region successfully complete a teardown once
482 * any of its associated decoders have been torn down. This maintains
483 * the commit state for the region since there are committed decoders,
484 * but blocks cxl_region_probe().
486 #define CXL_REGION_F_NEEDS_RESET 1
489 * struct cxl_region - CXL region
490 * @dev: This region's device
491 * @id: This region's id. Id is globally unique across all regions
492 * @mode: Endpoint decoder allocation / access mode
493 * @type: Endpoint decoder target type
494 * @cxl_nvb: nvdimm bridge for coordinating @cxlr_pmem setup / shutdown
495 * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge
496 * @flags: Region state flags
497 * @params: active + config params for the region
502 enum cxl_decoder_mode mode;
503 enum cxl_decoder_type type;
504 struct cxl_nvdimm_bridge *cxl_nvb;
505 struct cxl_pmem_region *cxlr_pmem;
507 struct cxl_region_params params;
510 struct cxl_nvdimm_bridge {
513 struct cxl_port *port;
514 struct nvdimm_bus *nvdimm_bus;
515 struct nvdimm_bus_descriptor nd_desc;
518 #define CXL_DEV_ID_LEN 19
522 struct cxl_memdev *cxlmd;
523 u8 dev_id[CXL_DEV_ID_LEN]; /* for nvdimm, string of 'serial' */
526 struct cxl_pmem_region_mapping {
527 struct cxl_memdev *cxlmd;
528 struct cxl_nvdimm *cxl_nvd;
534 struct cxl_pmem_region {
536 struct cxl_region *cxlr;
537 struct nd_region *nd_region;
538 struct range hpa_range;
540 struct cxl_pmem_region_mapping mapping[];
543 struct cxl_dax_region {
545 struct cxl_region *cxlr;
546 struct range hpa_range;
550 * struct cxl_port - logical collection of upstream port devices and
551 * downstream port devices to construct a CXL memory
553 * @dev: this port's device
554 * @uport: PCI or platform device implementing the upstream port capability
555 * @host_bridge: Shortcut to the platform attach point for this port
556 * @id: id for port device-name
557 * @dports: cxl_dport instances referenced by decoders
558 * @endpoints: cxl_ep instances, endpoints that are a descendant of this port
559 * @regions: cxl_region_ref instances, regions mapped by this port
560 * @parent_dport: dport that points to this port in the parent
561 * @decoder_ida: allocator for decoder ids
562 * @nr_dports: number of entries in @dports
563 * @hdm_end: track last allocated HDM decoder instance for allocation ordering
564 * @commit_end: cursor to track highest committed decoder for commit ordering
565 * @component_reg_phys: component register capability base address (optional)
566 * @dead: last ep has been removed, force port re-creation
567 * @depth: How deep this port is relative to the root. depth 0 is the root.
568 * @cdat: Cached CDAT data
569 * @cdat_available: Should a CDAT attribute be available in sysfs
573 struct device *uport;
574 struct device *host_bridge;
576 struct xarray dports;
577 struct xarray endpoints;
578 struct xarray regions;
579 struct cxl_dport *parent_dport;
580 struct ida decoder_ida;
584 resource_size_t component_reg_phys;
594 static inline struct cxl_dport *
595 cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
597 return xa_load(&port->dports, (unsigned long)dport_dev);
601 * struct cxl_dport - CXL downstream port
602 * @dport: PCI bridge or firmware device representing the downstream link
603 * @port_id: unique hardware identifier for dport in decoder target list
604 * @component_reg_phys: downstream port component registers
605 * @rcrb: base address for the Root Complex Register Block
606 * @rch: Indicate whether this dport was enumerated in RCH or VH mode
607 * @port: reference to cxl_port that contains this downstream port
610 struct device *dport;
612 resource_size_t component_reg_phys;
613 resource_size_t rcrb;
615 struct cxl_port *port;
619 * struct cxl_ep - track an endpoint's interest in a port
620 * @ep: device that hosts a generic CXL endpoint (expander or accelerator)
621 * @dport: which dport routes to this endpoint on @port
622 * @next: cxl switch port across the link attached to @dport NULL if
623 * attached to an endpoint
627 struct cxl_dport *dport;
628 struct cxl_port *next;
632 * struct cxl_region_ref - track a region's interest in a port
633 * @port: point in topology to install this reference
634 * @decoder: decoder assigned for @region in @port
635 * @region: region for this reference
636 * @endpoints: cxl_ep references for region members beneath @port
637 * @nr_targets_set: track how many targets have been programmed during setup
638 * @nr_eps: number of endpoints beneath @port
639 * @nr_targets: number of distinct targets needed to reach @nr_eps
641 struct cxl_region_ref {
642 struct cxl_port *port;
643 struct cxl_decoder *decoder;
644 struct cxl_region *region;
645 struct xarray endpoints;
652 * The platform firmware device hosting the root is also the top of the
653 * CXL port topology. All other CXL ports have another CXL port as their
654 * parent and their ->uport / host device is out-of-line of the port
657 static inline bool is_cxl_root(struct cxl_port *port)
659 return port->uport == port->dev.parent;
662 bool is_cxl_port(const struct device *dev);
663 struct cxl_port *to_cxl_port(const struct device *dev);
665 int devm_cxl_register_pci_bus(struct device *host, struct device *uport,
666 struct pci_bus *bus);
667 struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port);
668 struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
669 resource_size_t component_reg_phys,
670 struct cxl_dport *parent_dport);
671 struct cxl_port *find_cxl_root(struct cxl_port *port);
672 int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
673 void cxl_bus_rescan(void);
674 void cxl_bus_drain(void);
675 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd,
676 struct cxl_dport **dport);
677 bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd);
679 struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port,
680 struct device *dport, int port_id,
681 resource_size_t component_reg_phys);
682 struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
683 struct device *dport_dev, int port_id,
684 resource_size_t component_reg_phys,
685 resource_size_t rcrb);
687 struct cxl_decoder *to_cxl_decoder(struct device *dev);
688 struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
689 struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
690 struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev);
691 bool is_root_decoder(struct device *dev);
692 bool is_switch_decoder(struct device *dev);
693 bool is_endpoint_decoder(struct device *dev);
694 struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port,
695 unsigned int nr_targets,
696 cxl_calc_hb_fn calc_hb);
697 struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos);
698 struct cxl_switch_decoder *cxl_switch_decoder_alloc(struct cxl_port *port,
699 unsigned int nr_targets);
700 int cxl_decoder_add(struct cxl_decoder *cxld, int *target_map);
701 struct cxl_endpoint_decoder *cxl_endpoint_decoder_alloc(struct cxl_port *port);
702 int cxl_decoder_add_locked(struct cxl_decoder *cxld, int *target_map);
703 int cxl_decoder_autoremove(struct device *host, struct cxl_decoder *cxld);
704 int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint);
707 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
708 * @mem_enabled: cached value of mem_enabled in the DVSEC at init time
709 * @ranges: Number of active HDM ranges this device uses.
710 * @port: endpoint port associated with this info instance
711 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
713 struct cxl_endpoint_dvsec_info {
716 struct cxl_port *port;
717 struct range dvsec_range[2];
721 struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
722 struct cxl_endpoint_dvsec_info *info);
723 int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
724 struct cxl_endpoint_dvsec_info *info);
725 int devm_cxl_add_passthrough_decoder(struct cxl_port *port);
726 int cxl_dvsec_rr_decode(struct device *dev, int dvsec,
727 struct cxl_endpoint_dvsec_info *info);
729 bool is_cxl_region(struct device *dev);
731 extern struct bus_type cxl_bus_type;
735 int (*probe)(struct device *dev);
736 void (*remove)(struct device *dev);
737 struct device_driver drv;
741 static inline struct cxl_driver *to_cxl_drv(struct device_driver *drv)
743 return container_of(drv, struct cxl_driver, drv);
746 int __cxl_driver_register(struct cxl_driver *cxl_drv, struct module *owner,
747 const char *modname);
748 #define cxl_driver_register(x) __cxl_driver_register(x, THIS_MODULE, KBUILD_MODNAME)
749 void cxl_driver_unregister(struct cxl_driver *cxl_drv);
751 #define module_cxl_driver(__cxl_driver) \
752 module_driver(__cxl_driver, cxl_driver_register, cxl_driver_unregister)
754 #define CXL_DEVICE_NVDIMM_BRIDGE 1
755 #define CXL_DEVICE_NVDIMM 2
756 #define CXL_DEVICE_PORT 3
757 #define CXL_DEVICE_ROOT 4
758 #define CXL_DEVICE_MEMORY_EXPANDER 5
759 #define CXL_DEVICE_REGION 6
760 #define CXL_DEVICE_PMEM_REGION 7
761 #define CXL_DEVICE_DAX_REGION 8
763 #define MODULE_ALIAS_CXL(type) MODULE_ALIAS("cxl:t" __stringify(type) "*")
764 #define CXL_MODALIAS_FMT "cxl:t%d"
766 struct cxl_nvdimm_bridge *to_cxl_nvdimm_bridge(struct device *dev);
767 struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
768 struct cxl_port *port);
769 struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
770 bool is_cxl_nvdimm(struct device *dev);
771 bool is_cxl_nvdimm_bridge(struct device *dev);
772 int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd);
773 struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd);
775 #ifdef CONFIG_CXL_REGION
776 bool is_cxl_pmem_region(struct device *dev);
777 struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev);
778 int cxl_add_to_region(struct cxl_port *root,
779 struct cxl_endpoint_decoder *cxled);
780 struct cxl_dax_region *to_cxl_dax_region(struct device *dev);
782 static inline bool is_cxl_pmem_region(struct device *dev)
786 static inline struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev)
790 static inline int cxl_add_to_region(struct cxl_port *root,
791 struct cxl_endpoint_decoder *cxled)
795 static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
802 * Unit test builds overrides this to __weak, find the 'strong' version
803 * of these symbols in tools/testing/cxl/.
806 #define __mock static
809 #endif /* __CXL_H__ */