drivers/cxl/acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
   3 #include <linux/platform_device.h>
   4 #include <linux/module.h>
   5 #include <linux/device.h>
   6 #include <linux/kernel.h>
   7 #include <linux/acpi.h>
   8 #include <linux/pci.h>
   9 #include "cxlpci.h"
  10 #include "cxl.h"
  11
  12 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
  13 #define CFMWS_INTERLEAVE_WAYS(x)        (1 << (x)->interleave_ways)
  14 #define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8)
  15
  16 static unsigned long cfmws_to_decoder_flags(int restrictions)
  17 {
  18         unsigned long flags = CXL_DECODER_F_ENABLE;
  19
  20         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2)
  21                 flags |= CXL_DECODER_F_TYPE2;
  22         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3)
  23                 flags |= CXL_DECODER_F_TYPE3;
  24         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE)
  25                 flags |= CXL_DECODER_F_RAM;
  26         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM)
  27                 flags |= CXL_DECODER_F_PMEM;
  28         if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED)
  29                 flags |= CXL_DECODER_F_LOCK;
  30
  31         return flags;
  32 }
  33
  34 static int cxl_acpi_cfmws_verify(struct device *dev,
  35                                  struct acpi_cedt_cfmws *cfmws)
  36 {
  37         int expected_len;
  38
  39         if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) {
  40                 dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n");
  41                 return -EINVAL;
  42         }
  43
  44         if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
  45                 dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
  46                 return -EINVAL;
  47         }
  48
  49         if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) {
  50                 dev_err(dev, "CFMWS Window Size not 256MB aligned\n");
  51                 return -EINVAL;
  52         }
  53
  54         if (CFMWS_INTERLEAVE_WAYS(cfmws) > CXL_DECODER_MAX_INTERLEAVE) {
  55                 dev_err(dev, "CFMWS Interleave Ways (%d) too large\n",
  56                         CFMWS_INTERLEAVE_WAYS(cfmws));
  57                 return -EINVAL;
  58         }
  59
  60         expected_len = struct_size((cfmws), interleave_targets,
  61                                    CFMWS_INTERLEAVE_WAYS(cfmws));
  62
  63         if (cfmws->header.length < expected_len) {
  64                 dev_err(dev, "CFMWS length %d less than expected %d\n",
  65                         cfmws->header.length, expected_len);
  66                 return -EINVAL;
  67         }
  68
  69         if (cfmws->header.length > expected_len)
  70                 dev_dbg(dev, "CFMWS length %d greater than expected %d\n",
  71                         cfmws->header.length, expected_len);
  72
  73         return 0;
  74 }
  75
  76 struct cxl_cfmws_context {
  77         struct device *dev;
  78         struct cxl_port *root_port;
  79 };
  80
  81 static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
  82                            const unsigned long end)
  83 {
  84         int target_map[CXL_DECODER_MAX_INTERLEAVE];
  85         struct cxl_cfmws_context *ctx = arg;
  86         struct cxl_port *root_port = ctx->root_port;
  87         struct device *dev = ctx->dev;
  88         struct acpi_cedt_cfmws *cfmws;
  89         struct cxl_decoder *cxld;
  90         int rc, i;
  91
  92         cfmws = (struct acpi_cedt_cfmws *) header;
  93
  94         rc = cxl_acpi_cfmws_verify(dev, cfmws);
  95         if (rc) {
  96                 dev_err(dev, "CFMWS range %#llx-%#llx not registered\n",
  97                         cfmws->base_hpa,
  98                         cfmws->base_hpa + cfmws->window_size - 1);
  99                 return 0;
 100         }
 101
 102         for (i = 0; i < CFMWS_INTERLEAVE_WAYS(cfmws); i++)
 103                 target_map[i] = cfmws->interleave_targets[i];
 104
 105         cxld = cxl_root_decoder_alloc(root_port, CFMWS_INTERLEAVE_WAYS(cfmws));
 106         if (IS_ERR(cxld))
 107                 return 0;
 108
 109         cxld->flags = cfmws_to_decoder_flags(cfmws->restrictions);
 110         cxld->target_type = CXL_DECODER_EXPANDER;
 111         cxld->hpa_range = (struct range) {
 112                 .start = cfmws->base_hpa,
 113                 .end = cfmws->base_hpa + cfmws->window_size - 1,
 114         };
 115         cxld->interleave_ways = CFMWS_INTERLEAVE_WAYS(cfmws);
 116         cxld->interleave_granularity = CFMWS_INTERLEAVE_GRANULARITY(cfmws);
 117
 118         rc = cxl_decoder_add(cxld, target_map);
 119         if (rc)
 120                 put_device(&cxld->dev);
 121         else
 122                 rc = cxl_decoder_autoremove(dev, cxld);
 123         if (rc) {
 124                 dev_err(dev, "Failed to add decode range [%#llx - %#llx]\n",
 125                         cxld->hpa_range.start, cxld->hpa_range.end);
 126                 return 0;
 127         }
 128         dev_dbg(dev, "add: %s node: %d range [%#llx - %#llx]\n",
 129                 dev_name(&cxld->dev),
 130                 phys_to_target_node(cxld->hpa_range.start),
 131                 cxld->hpa_range.start, cxld->hpa_range.end);
 132
 133         return 0;
 134 }
 135
 136 __mock struct acpi_device *to_cxl_host_bridge(struct device *host,
 137                                               struct device *dev)
 138 {
 139         struct acpi_device *adev = to_acpi_device(dev);
 140
 141         if (!acpi_pci_find_root(adev->handle))
 142                 return NULL;
 143
 144         if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0)
 145                 return adev;
 146         return NULL;
 147 }
 148
 149 /*
 150  * A host bridge is a dport to a CFMWS decode and it is a uport to the
 151  * dport (PCIe Root Ports) in the host bridge.
 152  */
 153 static int add_host_bridge_uport(struct device *match, void *arg)
 154 {
 155         struct cxl_port *root_port = arg;
 156         struct device *host = root_port->dev.parent;
 157         struct acpi_device *bridge = to_cxl_host_bridge(host, match);
 158         struct acpi_pci_root *pci_root;
 159         struct cxl_dport *dport;
 160         struct cxl_port *port;
 161         int rc;
 162
 163         if (!bridge)
 164                 return 0;
 165
 166         dport = cxl_find_dport_by_dev(root_port, match);
 167         if (!dport) {
 168                 dev_dbg(host, "host bridge expected and not found\n");
 169                 return 0;
 170         }
 171
 172         /*
 173          * Note that this lookup already succeeded in
 174          * to_cxl_host_bridge(), so no need to check for failure here
 175          */
 176         pci_root = acpi_pci_find_root(bridge->handle);
 177         rc = devm_cxl_register_pci_bus(host, match, pci_root->bus);
 178         if (rc)
 179                 return rc;
 180
 181         port = devm_cxl_add_port(host, match, dport->component_reg_phys,
 182                                  root_port);
 183         if (IS_ERR(port))
 184                 return PTR_ERR(port);
 185         dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev));
 186
 187         return 0;
 188 }
 189
 190 struct cxl_chbs_context {
 191         struct device *dev;
 192         unsigned long long uid;
 193         resource_size_t chbcr;
 194 };
 195
 196 static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
 197                          const unsigned long end)
 198 {
 199         struct cxl_chbs_context *ctx = arg;
 200         struct acpi_cedt_chbs *chbs;
 201
 202         if (ctx->chbcr)
 203                 return 0;
 204
 205         chbs = (struct acpi_cedt_chbs *) header;
 206
 207         if (ctx->uid != chbs->uid)
 208                 return 0;
 209         ctx->chbcr = chbs->base;
 210
 211         return 0;
 212 }
 213
 214 static int add_host_bridge_dport(struct device *match, void *arg)
 215 {
 216         acpi_status status;
 217         unsigned long long uid;
 218         struct cxl_dport *dport;
 219         struct cxl_chbs_context ctx;
 220         struct cxl_port *root_port = arg;
 221         struct device *host = root_port->dev.parent;
 222         struct acpi_device *bridge = to_cxl_host_bridge(host, match);
 223
 224         if (!bridge)
 225                 return 0;
 226
 227         status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL,
 228                                        &uid);
 229         if (status != AE_OK) {
 230                 dev_err(host, "unable to retrieve _UID of %s\n",
 231                         dev_name(match));
 232                 return -ENODEV;
 233         }
 234
 235         ctx = (struct cxl_chbs_context) {
 236                 .dev = host,
 237                 .uid = uid,
 238         };
 239         acpi_table_parse_cedt(ACPI_CEDT_TYPE_CHBS, cxl_get_chbcr, &ctx);
 240
 241         if (ctx.chbcr == 0) {
 242                 dev_warn(host, "No CHBS found for Host Bridge: %s\n",
 243                          dev_name(match));
 244                 return 0;
 245         }
 246
 247         dport = devm_cxl_add_dport(root_port, match, uid, ctx.chbcr);
 248         if (IS_ERR(dport)) {
 249                 dev_err(host, "failed to add downstream port: %s\n",
 250                         dev_name(match));
 251                 return PTR_ERR(dport);
 252         }
 253         dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match));
 254         return 0;
 255 }
 256
 257 static int add_root_nvdimm_bridge(struct device *match, void *data)
 258 {
 259         struct cxl_decoder *cxld;
 260         struct cxl_port *root_port = data;
 261         struct cxl_nvdimm_bridge *cxl_nvb;
 262         struct device *host = root_port->dev.parent;
 263
 264         if (!is_root_decoder(match))
 265                 return 0;
 266
 267         cxld = to_cxl_decoder(match);
 268         if (!(cxld->flags & CXL_DECODER_F_PMEM))
 269                 return 0;
 270
 271         cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port);
 272         if (IS_ERR(cxl_nvb)) {
 273                 dev_dbg(host, "failed to register pmem\n");
 274                 return PTR_ERR(cxl_nvb);
 275         }
 276         dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev),
 277                 dev_name(&cxl_nvb->dev));
 278         return 1;
 279 }
 280
 281 static struct lock_class_key cxl_root_key;
 282
 283 static void cxl_acpi_lock_reset_class(void *dev)
 284 {
 285         device_lock_reset_class(dev);
 286 }
 287
 288 static int cxl_acpi_probe(struct platform_device *pdev)
 289 {
 290         int rc;
 291         struct cxl_port *root_port;
 292         struct device *host = &pdev->dev;
 293         struct acpi_device *adev = ACPI_COMPANION(host);
 294         struct cxl_cfmws_context ctx;
 295
 296         device_lock_set_class(&pdev->dev, &cxl_root_key);
 297         rc = devm_add_action_or_reset(&pdev->dev, cxl_acpi_lock_reset_class,
 298                                       &pdev->dev);
 299         if (rc)
 300                 return rc;
 301
 302         root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL);
 303         if (IS_ERR(root_port))
 304                 return PTR_ERR(root_port);
 305         dev_dbg(host, "add: %s\n", dev_name(&root_port->dev));
 306
 307         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 308                               add_host_bridge_dport);
 309         if (rc < 0)
 310                 return rc;
 311
 312         ctx = (struct cxl_cfmws_context) {
 313                 .dev = host,
 314                 .root_port = root_port,
 315         };
 316         acpi_table_parse_cedt(ACPI_CEDT_TYPE_CFMWS, cxl_parse_cfmws, &ctx);
 317
 318         /*
 319          * Root level scanned with host-bridge as dports, now scan host-bridges
 320          * for their role as CXL uports to their CXL-capable PCIe Root Ports.
 321          */
 322         rc = bus_for_each_dev(adev->dev.bus, NULL, root_port,
 323                               add_host_bridge_uport);
 324         if (rc < 0)
 325                 return rc;
 326
 327         if (IS_ENABLED(CONFIG_CXL_PMEM))
 328                 rc = device_for_each_child(&root_port->dev, root_port,
 329                                            add_root_nvdimm_bridge);
 330         if (rc < 0)
 331                 return rc;
 332
 333         /* In case PCI is scanned before ACPI re-trigger memdev attach */
 334         return cxl_bus_rescan();
 335 }
 336
 337 static const struct acpi_device_id cxl_acpi_ids[] = {
 338         { "ACPI0017" },
 339         { },
 340 };
 341 MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids);
 342
 343 static struct platform_driver cxl_acpi_driver = {
 344         .probe = cxl_acpi_probe,
 345         .driver = {
 346                 .name = KBUILD_MODNAME,
 347                 .acpi_match_table = cxl_acpi_ids,
 348         },
 349 };
 350
 351 module_platform_driver(cxl_acpi_driver);
 352 MODULE_LICENSE("GPL v2");
 353 MODULE_IMPORT_NS(CXL);
 354 MODULE_IMPORT_NS(ACPI);