drivers/crypto/stm32/stm32_crc32.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2017
   3  * Author: Fabien Dessenne <fabien.dessenne@st.com>
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/bitrev.h>
   8 #include <linux/clk.h>
   9 #include <linux/crc32poly.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/pm_runtime.h>
  13
  14 #include <crypto/internal/hash.h>
  15
  16 #include <asm/unaligned.h>
  17
  18 #define DRIVER_NAME             "stm32-crc32"
  19 #define CHKSUM_DIGEST_SIZE      4
  20 #define CHKSUM_BLOCK_SIZE       1
  21
  22 /* Registers */
  23 #define CRC_DR                  0x00000000
  24 #define CRC_CR                  0x00000008
  25 #define CRC_INIT                0x00000010
  26 #define CRC_POL                 0x00000014
  27
  28 /* Registers values */
  29 #define CRC_CR_RESET            BIT(0)
  30 #define CRC_CR_REVERSE          (BIT(7) | BIT(6) | BIT(5))
  31 #define CRC_INIT_DEFAULT        0xFFFFFFFF
  32
  33 #define CRC_AUTOSUSPEND_DELAY   50
  34
  35 struct stm32_crc {
  36         struct list_head list;
  37         struct device    *dev;
  38         void __iomem     *regs;
  39         struct clk       *clk;
  40         u8               pending_data[sizeof(u32)];
  41         size_t           nb_pending_bytes;
  42 };
  43
  44 struct stm32_crc_list {
  45         struct list_head dev_list;
  46         spinlock_t       lock; /* protect dev_list */
  47 };
  48
  49 static struct stm32_crc_list crc_list = {
  50         .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
  51         .lock     = __SPIN_LOCK_UNLOCKED(crc_list.lock),
  52 };
  53
  54 struct stm32_crc_ctx {
  55         u32 key;
  56         u32 poly;
  57 };
  58
  59 struct stm32_crc_desc_ctx {
  60         u32    partial; /* crc32c: partial in first 4 bytes of that struct */
  61         struct stm32_crc *crc;
  62 };
  63
  64 static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
  65 {
  66         struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  67
  68         mctx->key = CRC_INIT_DEFAULT;
  69         mctx->poly = CRC32_POLY_LE;
  70         return 0;
  71 }
  72
  73 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
  74 {
  75         struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
  76
  77         mctx->key = CRC_INIT_DEFAULT;
  78         mctx->poly = CRC32C_POLY_LE;
  79         return 0;
  80 }
  81
  82 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
  83                             unsigned int keylen)
  84 {
  85         struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
  86
  87         if (keylen != sizeof(u32)) {
  88                 crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  89                 return -EINVAL;
  90         }
  91
  92         mctx->key = get_unaligned_le32(key);
  93         return 0;
  94 }
  95
  96 static int stm32_crc_init(struct shash_desc *desc)
  97 {
  98         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
  99         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
 100         struct stm32_crc *crc;
 101
 102         spin_lock_bh(&crc_list.lock);
 103         list_for_each_entry(crc, &crc_list.dev_list, list) {
 104                 ctx->crc = crc;
 105                 break;
 106         }
 107         spin_unlock_bh(&crc_list.lock);
 108
 109         pm_runtime_get_sync(ctx->crc->dev);
 110
 111         /* Reset, set key, poly and configure in bit reverse mode */
 112         writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
 113         writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
 114         writel_relaxed(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
 115
 116         /* Store partial result */
 117         ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
 118         ctx->crc->nb_pending_bytes = 0;
 119
 120         pm_runtime_mark_last_busy(ctx->crc->dev);
 121         pm_runtime_put_autosuspend(ctx->crc->dev);
 122
 123         return 0;
 124 }
 125
 126 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
 127                             unsigned int length)
 128 {
 129         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
 130         struct stm32_crc *crc = ctx->crc;
 131         u32 *d32;
 132         unsigned int i;
 133
 134         pm_runtime_get_sync(crc->dev);
 135
 136         if (unlikely(crc->nb_pending_bytes)) {
 137                 while (crc->nb_pending_bytes != sizeof(u32) && length) {
 138                         /* Fill in pending data */
 139                         crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
 140                         length--;
 141                 }
 142
 143                 if (crc->nb_pending_bytes == sizeof(u32)) {
 144                         /* Process completed pending data */
 145                         writel_relaxed(*(u32 *)crc->pending_data,
 146                                        crc->regs + CRC_DR);
 147                         crc->nb_pending_bytes = 0;
 148                 }
 149         }
 150
 151         d32 = (u32 *)d8;
 152         for (i = 0; i < length >> 2; i++)
 153                 /* Process 32 bits data */
 154                 writel_relaxed(*(d32++), crc->regs + CRC_DR);
 155
 156         /* Store partial result */
 157         ctx->partial = readl_relaxed(crc->regs + CRC_DR);
 158
 159         pm_runtime_mark_last_busy(crc->dev);
 160         pm_runtime_put_autosuspend(crc->dev);
 161
 162         /* Check for pending data (non 32 bits) */
 163         length &= 3;
 164         if (likely(!length))
 165                 return 0;
 166
 167         if ((crc->nb_pending_bytes + length) >= sizeof(u32)) {
 168                 /* Shall not happen */
 169                 dev_err(crc->dev, "Pending data overflow\n");
 170                 return -EINVAL;
 171         }
 172
 173         d8 = (const u8 *)d32;
 174         for (i = 0; i < length; i++)
 175                 /* Store pending data */
 176                 crc->pending_data[crc->nb_pending_bytes++] = *(d8++);
 177
 178         return 0;
 179 }
 180
 181 static int stm32_crc_final(struct shash_desc *desc, u8 *out)
 182 {
 183         struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
 184         struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
 185
 186         /* Send computed CRC */
 187         put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
 188                            ~ctx->partial : ctx->partial, out);
 189
 190         return 0;
 191 }
 192
 193 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
 194                            unsigned int length, u8 *out)
 195 {
 196         return stm32_crc_update(desc, data, length) ?:
 197                stm32_crc_final(desc, out);
 198 }
 199
 200 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
 201                             unsigned int length, u8 *out)
 202 {
 203         return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
 204 }
 205
 206 static struct shash_alg algs[] = {
 207         /* CRC-32 */
 208         {
 209                 .setkey         = stm32_crc_setkey,
 210                 .init           = stm32_crc_init,
 211                 .update         = stm32_crc_update,
 212                 .final          = stm32_crc_final,
 213                 .finup          = stm32_crc_finup,
 214                 .digest         = stm32_crc_digest,
 215                 .descsize       = sizeof(struct stm32_crc_desc_ctx),
 216                 .digestsize     = CHKSUM_DIGEST_SIZE,
 217                 .base           = {
 218                         .cra_name               = "crc32",
 219                         .cra_driver_name        = DRIVER_NAME,
 220                         .cra_priority           = 200,
 221                         .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
 222                         .cra_blocksize          = CHKSUM_BLOCK_SIZE,
 223                         .cra_alignmask          = 3,
 224                         .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
 225                         .cra_module             = THIS_MODULE,
 226                         .cra_init               = stm32_crc32_cra_init,
 227                 }
 228         },
 229         /* CRC-32Castagnoli */
 230         {
 231                 .setkey         = stm32_crc_setkey,
 232                 .init           = stm32_crc_init,
 233                 .update         = stm32_crc_update,
 234                 .final          = stm32_crc_final,
 235                 .finup          = stm32_crc_finup,
 236                 .digest         = stm32_crc_digest,
 237                 .descsize       = sizeof(struct stm32_crc_desc_ctx),
 238                 .digestsize     = CHKSUM_DIGEST_SIZE,
 239                 .base           = {
 240                         .cra_name               = "crc32c",
 241                         .cra_driver_name        = DRIVER_NAME,
 242                         .cra_priority           = 200,
 243                         .cra_flags              = CRYPTO_ALG_OPTIONAL_KEY,
 244                         .cra_blocksize          = CHKSUM_BLOCK_SIZE,
 245                         .cra_alignmask          = 3,
 246                         .cra_ctxsize            = sizeof(struct stm32_crc_ctx),
 247                         .cra_module             = THIS_MODULE,
 248                         .cra_init               = stm32_crc32c_cra_init,
 249                 }
 250         }
 251 };
 252
 253 static int stm32_crc_probe(struct platform_device *pdev)
 254 {
 255         struct device *dev = &pdev->dev;
 256         struct stm32_crc *crc;
 257         struct resource *res;
 258         int ret;
 259
 260         crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
 261         if (!crc)
 262                 return -ENOMEM;
 263
 264         crc->dev = dev;
 265
 266         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 267         crc->regs = devm_ioremap_resource(dev, res);
 268         if (IS_ERR(crc->regs)) {
 269                 dev_err(dev, "Cannot map CRC IO\n");
 270                 return PTR_ERR(crc->regs);
 271         }
 272
 273         crc->clk = devm_clk_get(dev, NULL);
 274         if (IS_ERR(crc->clk)) {
 275                 dev_err(dev, "Could not get clock\n");
 276                 return PTR_ERR(crc->clk);
 277         }
 278
 279         ret = clk_prepare_enable(crc->clk);
 280         if (ret) {
 281                 dev_err(crc->dev, "Failed to enable clock\n");
 282                 return ret;
 283         }
 284
 285         pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
 286         pm_runtime_use_autosuspend(dev);
 287
 288         pm_runtime_get_noresume(dev);
 289         pm_runtime_set_active(dev);
 290         pm_runtime_enable(dev);
 291
 292         platform_set_drvdata(pdev, crc);
 293
 294         spin_lock(&crc_list.lock);
 295         list_add(&crc->list, &crc_list.dev_list);
 296         spin_unlock(&crc_list.lock);
 297
 298         ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
 299         if (ret) {
 300                 dev_err(dev, "Failed to register\n");
 301                 clk_disable_unprepare(crc->clk);
 302                 return ret;
 303         }
 304
 305         dev_info(dev, "Initialized\n");
 306
 307         pm_runtime_put_sync(dev);
 308
 309         return 0;
 310 }
 311
 312 static int stm32_crc_remove(struct platform_device *pdev)
 313 {
 314         struct stm32_crc *crc = platform_get_drvdata(pdev);
 315         int ret = pm_runtime_get_sync(crc->dev);
 316
 317         if (ret < 0)
 318                 return ret;
 319
 320         spin_lock(&crc_list.lock);
 321         list_del(&crc->list);
 322         spin_unlock(&crc_list.lock);
 323
 324         crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 325
 326         pm_runtime_disable(crc->dev);
 327         pm_runtime_put_noidle(crc->dev);
 328
 329         clk_disable_unprepare(crc->clk);
 330
 331         return 0;
 332 }
 333
 334 #ifdef CONFIG_PM
 335 static int stm32_crc_runtime_suspend(struct device *dev)
 336 {
 337         struct stm32_crc *crc = dev_get_drvdata(dev);
 338
 339         clk_disable_unprepare(crc->clk);
 340
 341         return 0;
 342 }
 343
 344 static int stm32_crc_runtime_resume(struct device *dev)
 345 {
 346         struct stm32_crc *crc = dev_get_drvdata(dev);
 347         int ret;
 348
 349         ret = clk_prepare_enable(crc->clk);
 350         if (ret) {
 351                 dev_err(crc->dev, "Failed to prepare_enable clock\n");
 352                 return ret;
 353         }
 354
 355         return 0;
 356 }
 357 #endif
 358
 359 static const struct dev_pm_ops stm32_crc_pm_ops = {
 360         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 361                                 pm_runtime_force_resume)
 362         SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
 363                            stm32_crc_runtime_resume, NULL)
 364 };
 365
 366 static const struct of_device_id stm32_dt_ids[] = {
 367         { .compatible = "st,stm32f7-crc", },
 368         {},
 369 };
 370 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
 371
 372 static struct platform_driver stm32_crc_driver = {
 373         .probe  = stm32_crc_probe,
 374         .remove = stm32_crc_remove,
 375         .driver = {
 376                 .name           = DRIVER_NAME,
 377                 .pm             = &stm32_crc_pm_ops,
 378                 .of_match_table = stm32_dt_ids,
 379         },
 380 };
 381
 382 module_platform_driver(stm32_crc_driver);
 383
 384 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
 385 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
 386 MODULE_LICENSE("GPL");