drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         struct omap_sham_dev    *dd;
 172
 173         unsigned long           flags;
 174
 175         /* fallback stuff */
 176         struct crypto_shash     *fallback;
 177
 178         struct omap_sham_hmac_ctx base[0];
 179 };
 180
 181 #define OMAP_SHAM_QUEUE_LENGTH  10
 182
 183 struct omap_sham_algs_info {
 184         struct ahash_alg        *algs_list;
 185         unsigned int            size;
 186         unsigned int            registered;
 187 };
 188
 189 struct omap_sham_pdata {
 190         struct omap_sham_algs_info      *algs_info;
 191         unsigned int    algs_info_size;
 192         unsigned long   flags;
 193         int             digest_size;
 194
 195         void            (*copy_hash)(struct ahash_request *req, int out);
 196         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 197                                       int final, int dma);
 198         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 199         int             (*poll_irq)(struct omap_sham_dev *dd);
 200         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 201
 202         u32             odigest_ofs;
 203         u32             idigest_ofs;
 204         u32             din_ofs;
 205         u32             digcnt_ofs;
 206         u32             rev_ofs;
 207         u32             mask_ofs;
 208         u32             sysstatus_ofs;
 209         u32             mode_ofs;
 210         u32             length_ofs;
 211
 212         u32             major_mask;
 213         u32             major_shift;
 214         u32             minor_mask;
 215         u32             minor_shift;
 216 };
 217
 218 struct omap_sham_dev {
 219         struct list_head        list;
 220         unsigned long           phys_base;
 221         struct device           *dev;
 222         void __iomem            *io_base;
 223         int                     irq;
 224         spinlock_t              lock;
 225         int                     err;
 226         struct dma_chan         *dma_lch;
 227         struct tasklet_struct   done_task;
 228         u8                      polling_mode;
 229         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 230
 231         unsigned long           flags;
 232         int                     fallback_sz;
 233         struct crypto_queue     queue;
 234         struct ahash_request    *req;
 235
 236         const struct omap_sham_pdata    *pdata;
 237 };
 238
 239 struct omap_sham_drv {
 240         struct list_head        dev_list;
 241         spinlock_t              lock;
 242         unsigned long           flags;
 243 };
 244
 245 static struct omap_sham_drv sham = {
 246         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 247         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 248 };
 249
 250 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 251 {
 252         return __raw_readl(dd->io_base + offset);
 253 }
 254
 255 static inline void omap_sham_write(struct omap_sham_dev *dd,
 256                                         u32 offset, u32 value)
 257 {
 258         __raw_writel(value, dd->io_base + offset);
 259 }
 260
 261 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 262                                         u32 value, u32 mask)
 263 {
 264         u32 val;
 265
 266         val = omap_sham_read(dd, address);
 267         val &= ~mask;
 268         val |= value;
 269         omap_sham_write(dd, address, val);
 270 }
 271
 272 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 273 {
 274         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 275
 276         while (!(omap_sham_read(dd, offset) & bit)) {
 277                 if (time_is_before_jiffies(timeout))
 278                         return -ETIMEDOUT;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 285 {
 286         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 287         struct omap_sham_dev *dd = ctx->dd;
 288         u32 *hash = (u32 *)ctx->digest;
 289         int i;
 290
 291         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 292                 if (out)
 293                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 294                 else
 295                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 296         }
 297 }
 298
 299 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 300 {
 301         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 302         struct omap_sham_dev *dd = ctx->dd;
 303         int i;
 304
 305         if (ctx->flags & BIT(FLAGS_HMAC)) {
 306                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 307                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 308                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 309                 u32 *opad = (u32 *)bctx->opad;
 310
 311                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 312                         if (out)
 313                                 opad[i] = omap_sham_read(dd,
 314                                                 SHA_REG_ODIGEST(dd, i));
 315                         else
 316                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 317                                                 opad[i]);
 318                 }
 319         }
 320
 321         omap_sham_copy_hash_omap2(req, out);
 322 }
 323
 324 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 325 {
 326         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 327         u32 *in = (u32 *)ctx->digest;
 328         u32 *hash = (u32 *)req->result;
 329         int i, d, big_endian = 0;
 330
 331         if (!hash)
 332                 return;
 333
 334         switch (ctx->flags & FLAGS_MODE_MASK) {
 335         case FLAGS_MODE_MD5:
 336                 d = MD5_DIGEST_SIZE / sizeof(u32);
 337                 break;
 338         case FLAGS_MODE_SHA1:
 339                 /* OMAP2 SHA1 is big endian */
 340                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 341                         big_endian = 1;
 342                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 343                 break;
 344         case FLAGS_MODE_SHA224:
 345                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 346                 break;
 347         case FLAGS_MODE_SHA256:
 348                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 349                 break;
 350         case FLAGS_MODE_SHA384:
 351                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 352                 break;
 353         case FLAGS_MODE_SHA512:
 354                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 355                 break;
 356         default:
 357                 d = 0;
 358         }
 359
 360         if (big_endian)
 361                 for (i = 0; i < d; i++)
 362                         hash[i] = be32_to_cpu(in[i]);
 363         else
 364                 for (i = 0; i < d; i++)
 365                         hash[i] = le32_to_cpu(in[i]);
 366 }
 367
 368 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 369 {
 370         int err;
 371
 372         err = pm_runtime_get_sync(dd->dev);
 373         if (err < 0) {
 374                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 375                 return err;
 376         }
 377
 378         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 379                 set_bit(FLAGS_INIT, &dd->flags);
 380                 dd->err = 0;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 387                                  int final, int dma)
 388 {
 389         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 390         u32 val = length << 5, mask;
 391
 392         if (likely(ctx->digcnt))
 393                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 394
 395         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 396                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 397                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 398         /*
 399          * Setting ALGO_CONST only for the first iteration
 400          * and CLOSE_HASH only for the last one.
 401          */
 402         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 403                 val |= SHA_REG_CTRL_ALGO;
 404         if (!ctx->digcnt)
 405                 val |= SHA_REG_CTRL_ALGO_CONST;
 406         if (final)
 407                 val |= SHA_REG_CTRL_CLOSE_HASH;
 408
 409         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 410                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 411
 412         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 413 }
 414
 415 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 416 {
 417 }
 418
 419 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 420 {
 421         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 422 }
 423
 424 static int get_block_size(struct omap_sham_reqctx *ctx)
 425 {
 426         int d;
 427
 428         switch (ctx->flags & FLAGS_MODE_MASK) {
 429         case FLAGS_MODE_MD5:
 430         case FLAGS_MODE_SHA1:
 431                 d = SHA1_BLOCK_SIZE;
 432                 break;
 433         case FLAGS_MODE_SHA224:
 434         case FLAGS_MODE_SHA256:
 435                 d = SHA256_BLOCK_SIZE;
 436                 break;
 437         case FLAGS_MODE_SHA384:
 438         case FLAGS_MODE_SHA512:
 439                 d = SHA512_BLOCK_SIZE;
 440                 break;
 441         default:
 442                 d = 0;
 443         }
 444
 445         return d;
 446 }
 447
 448 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 449                                     u32 *value, int count)
 450 {
 451         for (; count--; value++, offset += 4)
 452                 omap_sham_write(dd, offset, *value);
 453 }
 454
 455 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 456                                  int final, int dma)
 457 {
 458         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 459         u32 val, mask;
 460
 461         /*
 462          * Setting ALGO_CONST only for the first iteration and
 463          * CLOSE_HASH only for the last one. Note that flags mode bits
 464          * correspond to algorithm encoding in mode register.
 465          */
 466         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 467         if (!ctx->digcnt) {
 468                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 469                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 470                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 471                 int bs, nr_dr;
 472
 473                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 474
 475                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 476                         bs = get_block_size(ctx);
 477                         nr_dr = bs / (2 * sizeof(u32));
 478                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 479                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 480                                           (u32 *)bctx->ipad, nr_dr);
 481                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 482                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 483                         ctx->digcnt += bs;
 484                 }
 485         }
 486
 487         if (final) {
 488                 val |= SHA_REG_MODE_CLOSE_HASH;
 489
 490                 if (ctx->flags & BIT(FLAGS_HMAC))
 491                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 492         }
 493
 494         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 495                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 496                SHA_REG_MODE_HMAC_KEY_PROC;
 497
 498         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 499         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 500         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 501         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 502                              SHA_REG_MASK_IT_EN |
 503                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 504                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 505 }
 506
 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 508 {
 509         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 510 }
 511
 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 513 {
 514         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 515                               SHA_REG_IRQSTATUS_INPUT_RDY);
 516 }
 517
 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 519                               int final)
 520 {
 521         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 522         int count, len32, bs32, offset = 0;
 523         const u32 *buffer;
 524         int mlen;
 525         struct sg_mapping_iter mi;
 526
 527         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 528                                                 ctx->digcnt, length, final);
 529
 530         dd->pdata->write_ctrl(dd, length, final, 0);
 531         dd->pdata->trigger(dd, length);
 532
 533         /* should be non-zero before next lines to disable clocks later */
 534         ctx->digcnt += length;
 535         ctx->total -= length;
 536
 537         if (final)
 538                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 539
 540         set_bit(FLAGS_CPU, &dd->flags);
 541
 542         len32 = DIV_ROUND_UP(length, sizeof(u32));
 543         bs32 = get_block_size(ctx) / sizeof(u32);
 544
 545         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 546                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 547
 548         mlen = 0;
 549
 550         while (len32) {
 551                 if (dd->pdata->poll_irq(dd))
 552                         return -ETIMEDOUT;
 553
 554                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 555                         if (!mlen) {
 556                                 sg_miter_next(&mi);
 557                                 mlen = mi.length;
 558                                 if (!mlen) {
 559                                         pr_err("sg miter failure.\n");
 560                                         return -EINVAL;
 561                                 }
 562                                 offset = 0;
 563                                 buffer = mi.addr;
 564                         }
 565                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 566                                         buffer[offset]);
 567                         mlen -= 4;
 568                 }
 569                 len32 -= min(len32, bs32);
 570         }
 571
 572         sg_miter_stop(&mi);
 573
 574         return -EINPROGRESS;
 575 }
 576
 577 static void omap_sham_dma_callback(void *param)
 578 {
 579         struct omap_sham_dev *dd = param;
 580
 581         set_bit(FLAGS_DMA_READY, &dd->flags);
 582         tasklet_schedule(&dd->done_task);
 583 }
 584
 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 586                               int final)
 587 {
 588         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 589         struct dma_async_tx_descriptor *tx;
 590         struct dma_slave_config cfg;
 591         int ret;
 592
 593         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 594                                                 ctx->digcnt, length, final);
 595
 596         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 597                 dev_err(dd->dev, "dma_map_sg error\n");
 598                 return -EINVAL;
 599         }
 600
 601         memset(&cfg, 0, sizeof(cfg));
 602
 603         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 604         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 605         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 606
 607         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 608         if (ret) {
 609                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 610                 return ret;
 611         }
 612
 613         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 614                                      DMA_MEM_TO_DEV,
 615                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 616
 617         if (!tx) {
 618                 dev_err(dd->dev, "prep_slave_sg failed\n");
 619                 return -EINVAL;
 620         }
 621
 622         tx->callback = omap_sham_dma_callback;
 623         tx->callback_param = dd;
 624
 625         dd->pdata->write_ctrl(dd, length, final, 1);
 626
 627         ctx->digcnt += length;
 628         ctx->total -= length;
 629
 630         if (final)
 631                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 632
 633         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 634
 635         dmaengine_submit(tx);
 636         dma_async_issue_pending(dd->dma_lch);
 637
 638         dd->pdata->trigger(dd, length);
 639
 640         return -EINPROGRESS;
 641 }
 642
 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 644                                    struct scatterlist *sg, int bs, int new_len)
 645 {
 646         int n = sg_nents(sg);
 647         struct scatterlist *tmp;
 648         int offset = ctx->offset;
 649
 650         if (ctx->bufcnt)
 651                 n++;
 652
 653         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 654         if (!ctx->sg)
 655                 return -ENOMEM;
 656
 657         sg_init_table(ctx->sg, n);
 658
 659         tmp = ctx->sg;
 660
 661         ctx->sg_len = 0;
 662
 663         if (ctx->bufcnt) {
 664                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 665                 tmp = sg_next(tmp);
 666                 ctx->sg_len++;
 667         }
 668
 669         while (sg && new_len) {
 670                 int len = sg->length - offset;
 671
 672                 if (offset) {
 673                         offset -= sg->length;
 674                         if (offset < 0)
 675                                 offset = 0;
 676                 }
 677
 678                 if (new_len < len)
 679                         len = new_len;
 680
 681                 if (len > 0) {
 682                         new_len -= len;
 683                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 684                         if (new_len <= 0)
 685                                 sg_mark_end(tmp);
 686                         tmp = sg_next(tmp);
 687                         ctx->sg_len++;
 688                 }
 689
 690                 sg = sg_next(sg);
 691         }
 692
 693         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 694
 695         ctx->bufcnt = 0;
 696
 697         return 0;
 698 }
 699
 700 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 701                               struct scatterlist *sg, int bs, int new_len)
 702 {
 703         int pages;
 704         void *buf;
 705         int len;
 706
 707         len = new_len + ctx->bufcnt;
 708
 709         pages = get_order(ctx->total);
 710
 711         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 712         if (!buf) {
 713                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 714                 return -ENOMEM;
 715         }
 716
 717         if (ctx->bufcnt)
 718                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 719
 720         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 721                                  ctx->total - ctx->bufcnt, 0);
 722         sg_init_table(ctx->sgl, 1);
 723         sg_set_buf(ctx->sgl, buf, len);
 724         ctx->sg = ctx->sgl;
 725         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 726         ctx->sg_len = 1;
 727         ctx->bufcnt = 0;
 728         ctx->offset = 0;
 729
 730         return 0;
 731 }
 732
 733 static int omap_sham_align_sgs(struct scatterlist *sg,
 734                                int nbytes, int bs, bool final,
 735                                struct omap_sham_reqctx *rctx)
 736 {
 737         int n = 0;
 738         bool aligned = true;
 739         bool list_ok = true;
 740         struct scatterlist *sg_tmp = sg;
 741         int new_len;
 742         int offset = rctx->offset;
 743
 744         if (!sg || !sg->length || !nbytes)
 745                 return 0;
 746
 747         new_len = nbytes;
 748
 749         if (offset)
 750                 list_ok = false;
 751
 752         if (final)
 753                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 754         else
 755                 new_len = (new_len - 1) / bs * bs;
 756
 757         if (nbytes != new_len)
 758                 list_ok = false;
 759
 760         while (nbytes > 0 && sg_tmp) {
 761                 n++;
 762
 763 #ifdef CONFIG_ZONE_DMA
 764                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 765                         aligned = false;
 766                         break;
 767                 }
 768 #endif
 769
 770                 if (offset < sg_tmp->length) {
 771                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 772                                 aligned = false;
 773                                 break;
 774                         }
 775
 776                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 777                                 aligned = false;
 778                                 break;
 779                         }
 780                 }
 781
 782                 if (offset) {
 783                         offset -= sg_tmp->length;
 784                         if (offset < 0) {
 785                                 nbytes += offset;
 786                                 offset = 0;
 787                         }
 788                 } else {
 789                         nbytes -= sg_tmp->length;
 790                 }
 791
 792                 sg_tmp = sg_next(sg_tmp);
 793
 794                 if (nbytes < 0) {
 795                         list_ok = false;
 796                         break;
 797                 }
 798         }
 799
 800         if (!aligned)
 801                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 802         else if (!list_ok)
 803                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 804
 805         rctx->sg_len = n;
 806         rctx->sg = sg;
 807
 808         return 0;
 809 }
 810
 811 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 812 {
 813         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 814         int bs;
 815         int ret;
 816         int nbytes;
 817         bool final = rctx->flags & BIT(FLAGS_FINUP);
 818         int xmit_len, hash_later;
 819
 820         if (!req)
 821                 return 0;
 822
 823         bs = get_block_size(rctx);
 824
 825         if (update)
 826                 nbytes = req->nbytes;
 827         else
 828                 nbytes = 0;
 829
 830         rctx->total = nbytes + rctx->bufcnt;
 831
 832         if (!rctx->total)
 833                 return 0;
 834
 835         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 836                 int len = bs - rctx->bufcnt % bs;
 837
 838                 if (len > nbytes)
 839                         len = nbytes;
 840                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 841                                          0, len, 0);
 842                 rctx->bufcnt += len;
 843                 nbytes -= len;
 844                 rctx->offset = len;
 845         }
 846
 847         if (rctx->bufcnt)
 848                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 849
 850         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 851         if (ret)
 852                 return ret;
 853
 854         xmit_len = rctx->total;
 855
 856         if (!IS_ALIGNED(xmit_len, bs)) {
 857                 if (final)
 858                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 859                 else
 860                         xmit_len = xmit_len / bs * bs;
 861         } else if (!final) {
 862                 xmit_len -= bs;
 863         }
 864
 865         hash_later = rctx->total - xmit_len;
 866         if (hash_later < 0)
 867                 hash_later = 0;
 868
 869         if (rctx->bufcnt && nbytes) {
 870                 /* have data from previous operation and current */
 871                 sg_init_table(rctx->sgl, 2);
 872                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 873
 874                 sg_chain(rctx->sgl, 2, req->src);
 875
 876                 rctx->sg = rctx->sgl;
 877
 878                 rctx->sg_len++;
 879         } else if (rctx->bufcnt) {
 880                 /* have buffered data only */
 881                 sg_init_table(rctx->sgl, 1);
 882                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 883
 884                 rctx->sg = rctx->sgl;
 885
 886                 rctx->sg_len = 1;
 887         }
 888
 889         if (hash_later) {
 890                 int offset = 0;
 891
 892                 if (hash_later > req->nbytes) {
 893                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 894                                hash_later - req->nbytes);
 895                         offset = hash_later - req->nbytes;
 896                 }
 897
 898                 if (req->nbytes) {
 899                         scatterwalk_map_and_copy(rctx->buffer + offset,
 900                                                  req->src,
 901                                                  offset + req->nbytes -
 902                                                  hash_later, hash_later, 0);
 903                 }
 904
 905                 rctx->bufcnt = hash_later;
 906         } else {
 907                 rctx->bufcnt = 0;
 908         }
 909
 910         if (!final)
 911                 rctx->total = xmit_len;
 912
 913         return 0;
 914 }
 915
 916 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 917 {
 918         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 919
 920         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 921
 922         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 923
 924         return 0;
 925 }
 926
 927 static int omap_sham_init(struct ahash_request *req)
 928 {
 929         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 930         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 931         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 932         struct omap_sham_dev *dd = NULL, *tmp;
 933         int bs = 0;
 934
 935         spin_lock_bh(&sham.lock);
 936         if (!tctx->dd) {
 937                 list_for_each_entry(tmp, &sham.dev_list, list) {
 938                         dd = tmp;
 939                         break;
 940                 }
 941                 tctx->dd = dd;
 942         } else {
 943                 dd = tctx->dd;
 944         }
 945         spin_unlock_bh(&sham.lock);
 946
 947         ctx->dd = dd;
 948
 949         ctx->flags = 0;
 950
 951         dev_dbg(dd->dev, "init: digest size: %d\n",
 952                 crypto_ahash_digestsize(tfm));
 953
 954         switch (crypto_ahash_digestsize(tfm)) {
 955         case MD5_DIGEST_SIZE:
 956                 ctx->flags |= FLAGS_MODE_MD5;
 957                 bs = SHA1_BLOCK_SIZE;
 958                 break;
 959         case SHA1_DIGEST_SIZE:
 960                 ctx->flags |= FLAGS_MODE_SHA1;
 961                 bs = SHA1_BLOCK_SIZE;
 962                 break;
 963         case SHA224_DIGEST_SIZE:
 964                 ctx->flags |= FLAGS_MODE_SHA224;
 965                 bs = SHA224_BLOCK_SIZE;
 966                 break;
 967         case SHA256_DIGEST_SIZE:
 968                 ctx->flags |= FLAGS_MODE_SHA256;
 969                 bs = SHA256_BLOCK_SIZE;
 970                 break;
 971         case SHA384_DIGEST_SIZE:
 972                 ctx->flags |= FLAGS_MODE_SHA384;
 973                 bs = SHA384_BLOCK_SIZE;
 974                 break;
 975         case SHA512_DIGEST_SIZE:
 976                 ctx->flags |= FLAGS_MODE_SHA512;
 977                 bs = SHA512_BLOCK_SIZE;
 978                 break;
 979         }
 980
 981         ctx->bufcnt = 0;
 982         ctx->digcnt = 0;
 983         ctx->total = 0;
 984         ctx->offset = 0;
 985         ctx->buflen = BUFLEN;
 986
 987         if (tctx->flags & BIT(FLAGS_HMAC)) {
 988                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 989                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 990
 991                         memcpy(ctx->buffer, bctx->ipad, bs);
 992                         ctx->bufcnt = bs;
 993                 }
 994
 995                 ctx->flags |= BIT(FLAGS_HMAC);
 996         }
 997
 998         return 0;
 999
1000 }
1001
1002 static int omap_sham_update_req(struct omap_sham_dev *dd)
1003 {
1004         struct ahash_request *req = dd->req;
1005         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1006         int err;
1007         bool final = ctx->flags & BIT(FLAGS_FINUP);
1008
1009         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1010                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1011
1012         if (ctx->total < get_block_size(ctx) ||
1013             ctx->total < dd->fallback_sz)
1014                 ctx->flags |= BIT(FLAGS_CPU);
1015
1016         if (ctx->flags & BIT(FLAGS_CPU))
1017                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1018         else
1019                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1020
1021         /* wait for dma completion before can take more data */
1022         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1023
1024         return err;
1025 }
1026
1027 static int omap_sham_final_req(struct omap_sham_dev *dd)
1028 {
1029         struct ahash_request *req = dd->req;
1030         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1031         int err = 0, use_dma = 1;
1032
1033         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1034                 /*
1035                  * faster to handle last block with cpu or
1036                  * use cpu when dma is not present.
1037                  */
1038                 use_dma = 0;
1039
1040         if (use_dma)
1041                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1042         else
1043                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1044
1045         ctx->bufcnt = 0;
1046
1047         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1048
1049         return err;
1050 }
1051
1052 static int omap_sham_finish_hmac(struct ahash_request *req)
1053 {
1054         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1055         struct omap_sham_hmac_ctx *bctx = tctx->base;
1056         int bs = crypto_shash_blocksize(bctx->shash);
1057         int ds = crypto_shash_digestsize(bctx->shash);
1058         SHASH_DESC_ON_STACK(shash, bctx->shash);
1059
1060         shash->tfm = bctx->shash;
1061         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1062
1063         return crypto_shash_init(shash) ?:
1064                crypto_shash_update(shash, bctx->opad, bs) ?:
1065                crypto_shash_finup(shash, req->result, ds, req->result);
1066 }
1067
1068 static int omap_sham_finish(struct ahash_request *req)
1069 {
1070         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1071         struct omap_sham_dev *dd = ctx->dd;
1072         int err = 0;
1073
1074         if (ctx->digcnt) {
1075                 omap_sham_copy_ready_hash(req);
1076                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1077                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1078                         err = omap_sham_finish_hmac(req);
1079         }
1080
1081         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1082
1083         return err;
1084 }
1085
1086 static void omap_sham_finish_req(struct ahash_request *req, int err)
1087 {
1088         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1089         struct omap_sham_dev *dd = ctx->dd;
1090
1091         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1092                 free_pages((unsigned long)sg_virt(ctx->sg),
1093                            get_order(ctx->sg->length));
1094
1095         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1096                 kfree(ctx->sg);
1097
1098         ctx->sg = NULL;
1099
1100         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1101
1102         if (!err) {
1103                 dd->pdata->copy_hash(req, 1);
1104                 if (test_bit(FLAGS_FINAL, &dd->flags))
1105                         err = omap_sham_finish(req);
1106         } else {
1107                 ctx->flags |= BIT(FLAGS_ERROR);
1108         }
1109
1110         /* atomic operation is not needed here */
1111         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1112                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1113
1114         pm_runtime_mark_last_busy(dd->dev);
1115         pm_runtime_put_autosuspend(dd->dev);
1116
1117         if (req->base.complete)
1118                 req->base.complete(&req->base, err);
1119 }
1120
1121 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1122                                   struct ahash_request *req)
1123 {
1124         struct crypto_async_request *async_req, *backlog;
1125         struct omap_sham_reqctx *ctx;
1126         unsigned long flags;
1127         int err = 0, ret = 0;
1128
1129 retry:
1130         spin_lock_irqsave(&dd->lock, flags);
1131         if (req)
1132                 ret = ahash_enqueue_request(&dd->queue, req);
1133         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1134                 spin_unlock_irqrestore(&dd->lock, flags);
1135                 return ret;
1136         }
1137         backlog = crypto_get_backlog(&dd->queue);
1138         async_req = crypto_dequeue_request(&dd->queue);
1139         if (async_req)
1140                 set_bit(FLAGS_BUSY, &dd->flags);
1141         spin_unlock_irqrestore(&dd->lock, flags);
1142
1143         if (!async_req)
1144                 return ret;
1145
1146         if (backlog)
1147                 backlog->complete(backlog, -EINPROGRESS);
1148
1149         req = ahash_request_cast(async_req);
1150         dd->req = req;
1151         ctx = ahash_request_ctx(req);
1152
1153         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1154         if (err || !ctx->total)
1155                 goto err1;
1156
1157         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1158                                                 ctx->op, req->nbytes);
1159
1160         err = omap_sham_hw_init(dd);
1161         if (err)
1162                 goto err1;
1163
1164         if (ctx->digcnt)
1165                 /* request has changed - restore hash */
1166                 dd->pdata->copy_hash(req, 0);
1167
1168         if (ctx->op == OP_UPDATE) {
1169                 err = omap_sham_update_req(dd);
1170                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1171                         /* no final() after finup() */
1172                         err = omap_sham_final_req(dd);
1173         } else if (ctx->op == OP_FINAL) {
1174                 err = omap_sham_final_req(dd);
1175         }
1176 err1:
1177         dev_dbg(dd->dev, "exit, err: %d\n", err);
1178
1179         if (err != -EINPROGRESS) {
1180                 /* done_task will not finish it, so do it here */
1181                 omap_sham_finish_req(req, err);
1182                 req = NULL;
1183
1184                 /*
1185                  * Execute next request immediately if there is anything
1186                  * in queue.
1187                  */
1188                 goto retry;
1189         }
1190
1191         return ret;
1192 }
1193
1194 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1195 {
1196         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1197         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1198         struct omap_sham_dev *dd = tctx->dd;
1199
1200         ctx->op = op;
1201
1202         return omap_sham_handle_queue(dd, req);
1203 }
1204
1205 static int omap_sham_update(struct ahash_request *req)
1206 {
1207         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1208         struct omap_sham_dev *dd = ctx->dd;
1209
1210         if (!req->nbytes)
1211                 return 0;
1212
1213         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1214                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1215                                          0, req->nbytes, 0);
1216                 ctx->bufcnt += req->nbytes;
1217                 return 0;
1218         }
1219
1220         if (dd->polling_mode)
1221                 ctx->flags |= BIT(FLAGS_CPU);
1222
1223         return omap_sham_enqueue(req, OP_UPDATE);
1224 }
1225
1226 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1227                                   const u8 *data, unsigned int len, u8 *out)
1228 {
1229         SHASH_DESC_ON_STACK(shash, tfm);
1230
1231         shash->tfm = tfm;
1232         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1233
1234         return crypto_shash_digest(shash, data, len, out);
1235 }
1236
1237 static int omap_sham_final_shash(struct ahash_request *req)
1238 {
1239         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1240         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1241         int offset = 0;
1242
1243         /*
1244          * If we are running HMAC on limited hardware support, skip
1245          * the ipad in the beginning of the buffer if we are going for
1246          * software fallback algorithm.
1247          */
1248         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1249             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1250                 offset = get_block_size(ctx);
1251
1252         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1253                                       ctx->buffer + offset,
1254                                       ctx->bufcnt - offset, req->result);
1255 }
1256
1257 static int omap_sham_final(struct ahash_request *req)
1258 {
1259         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1260
1261         ctx->flags |= BIT(FLAGS_FINUP);
1262
1263         if (ctx->flags & BIT(FLAGS_ERROR))
1264                 return 0; /* uncompleted hash is not needed */
1265
1266         /*
1267          * OMAP HW accel works only with buffers >= 9.
1268          * HMAC is always >= 9 because ipad == block size.
1269          * If buffersize is less than fallback_sz, we use fallback
1270          * SW encoding, as using DMA + HW in this case doesn't provide
1271          * any benefit.
1272          */
1273         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1274                 return omap_sham_final_shash(req);
1275         else if (ctx->bufcnt)
1276                 return omap_sham_enqueue(req, OP_FINAL);
1277
1278         /* copy ready hash (+ finalize hmac) */
1279         return omap_sham_finish(req);
1280 }
1281
1282 static int omap_sham_finup(struct ahash_request *req)
1283 {
1284         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1285         int err1, err2;
1286
1287         ctx->flags |= BIT(FLAGS_FINUP);
1288
1289         err1 = omap_sham_update(req);
1290         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1291                 return err1;
1292         /*
1293          * final() has to be always called to cleanup resources
1294          * even if udpate() failed, except EINPROGRESS
1295          */
1296         err2 = omap_sham_final(req);
1297
1298         return err1 ?: err2;
1299 }
1300
1301 static int omap_sham_digest(struct ahash_request *req)
1302 {
1303         return omap_sham_init(req) ?: omap_sham_finup(req);
1304 }
1305
1306 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1307                       unsigned int keylen)
1308 {
1309         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1310         struct omap_sham_hmac_ctx *bctx = tctx->base;
1311         int bs = crypto_shash_blocksize(bctx->shash);
1312         int ds = crypto_shash_digestsize(bctx->shash);
1313         struct omap_sham_dev *dd = NULL, *tmp;
1314         int err, i;
1315
1316         spin_lock_bh(&sham.lock);
1317         if (!tctx->dd) {
1318                 list_for_each_entry(tmp, &sham.dev_list, list) {
1319                         dd = tmp;
1320                         break;
1321                 }
1322                 tctx->dd = dd;
1323         } else {
1324                 dd = tctx->dd;
1325         }
1326         spin_unlock_bh(&sham.lock);
1327
1328         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1329         if (err)
1330                 return err;
1331
1332         if (keylen > bs) {
1333                 err = omap_sham_shash_digest(bctx->shash,
1334                                 crypto_shash_get_flags(bctx->shash),
1335                                 key, keylen, bctx->ipad);
1336                 if (err)
1337                         return err;
1338                 keylen = ds;
1339         } else {
1340                 memcpy(bctx->ipad, key, keylen);
1341         }
1342
1343         memset(bctx->ipad + keylen, 0, bs - keylen);
1344
1345         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1346                 memcpy(bctx->opad, bctx->ipad, bs);
1347
1348                 for (i = 0; i < bs; i++) {
1349                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1350                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1351                 }
1352         }
1353
1354         return err;
1355 }
1356
1357 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1358 {
1359         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1360         const char *alg_name = crypto_tfm_alg_name(tfm);
1361
1362         /* Allocate a fallback and abort if it failed. */
1363         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1364                                             CRYPTO_ALG_NEED_FALLBACK);
1365         if (IS_ERR(tctx->fallback)) {
1366                 pr_err("omap-sham: fallback driver '%s' "
1367                                 "could not be loaded.\n", alg_name);
1368                 return PTR_ERR(tctx->fallback);
1369         }
1370
1371         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1372                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1373
1374         if (alg_base) {
1375                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1376                 tctx->flags |= BIT(FLAGS_HMAC);
1377                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1378                                                 CRYPTO_ALG_NEED_FALLBACK);
1379                 if (IS_ERR(bctx->shash)) {
1380                         pr_err("omap-sham: base driver '%s' "
1381                                         "could not be loaded.\n", alg_base);
1382                         crypto_free_shash(tctx->fallback);
1383                         return PTR_ERR(bctx->shash);
1384                 }
1385
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1392 {
1393         return omap_sham_cra_init_alg(tfm, NULL);
1394 }
1395
1396 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1397 {
1398         return omap_sham_cra_init_alg(tfm, "sha1");
1399 }
1400
1401 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1402 {
1403         return omap_sham_cra_init_alg(tfm, "sha224");
1404 }
1405
1406 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1407 {
1408         return omap_sham_cra_init_alg(tfm, "sha256");
1409 }
1410
1411 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1412 {
1413         return omap_sham_cra_init_alg(tfm, "md5");
1414 }
1415
1416 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1417 {
1418         return omap_sham_cra_init_alg(tfm, "sha384");
1419 }
1420
1421 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1422 {
1423         return omap_sham_cra_init_alg(tfm, "sha512");
1424 }
1425
1426 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1427 {
1428         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1429
1430         crypto_free_shash(tctx->fallback);
1431         tctx->fallback = NULL;
1432
1433         if (tctx->flags & BIT(FLAGS_HMAC)) {
1434                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1435                 crypto_free_shash(bctx->shash);
1436         }
1437 }
1438
1439 static int omap_sham_export(struct ahash_request *req, void *out)
1440 {
1441         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1442
1443         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1444
1445         return 0;
1446 }
1447
1448 static int omap_sham_import(struct ahash_request *req, const void *in)
1449 {
1450         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1451         const struct omap_sham_reqctx *ctx_in = in;
1452
1453         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1454
1455         return 0;
1456 }
1457
1458 static struct ahash_alg algs_sha1_md5[] = {
1459 {
1460         .init           = omap_sham_init,
1461         .update         = omap_sham_update,
1462         .final          = omap_sham_final,
1463         .finup          = omap_sham_finup,
1464         .digest         = omap_sham_digest,
1465         .halg.digestsize        = SHA1_DIGEST_SIZE,
1466         .halg.base      = {
1467                 .cra_name               = "sha1",
1468                 .cra_driver_name        = "omap-sha1",
1469                 .cra_priority           = 400,
1470                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1471                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1472                                                 CRYPTO_ALG_ASYNC |
1473                                                 CRYPTO_ALG_NEED_FALLBACK,
1474                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1475                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1476                 .cra_alignmask          = OMAP_ALIGN_MASK,
1477                 .cra_module             = THIS_MODULE,
1478                 .cra_init               = omap_sham_cra_init,
1479                 .cra_exit               = omap_sham_cra_exit,
1480         }
1481 },
1482 {
1483         .init           = omap_sham_init,
1484         .update         = omap_sham_update,
1485         .final          = omap_sham_final,
1486         .finup          = omap_sham_finup,
1487         .digest         = omap_sham_digest,
1488         .halg.digestsize        = MD5_DIGEST_SIZE,
1489         .halg.base      = {
1490                 .cra_name               = "md5",
1491                 .cra_driver_name        = "omap-md5",
1492                 .cra_priority           = 400,
1493                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1494                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1495                                                 CRYPTO_ALG_ASYNC |
1496                                                 CRYPTO_ALG_NEED_FALLBACK,
1497                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1498                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1499                 .cra_alignmask          = OMAP_ALIGN_MASK,
1500                 .cra_module             = THIS_MODULE,
1501                 .cra_init               = omap_sham_cra_init,
1502                 .cra_exit               = omap_sham_cra_exit,
1503         }
1504 },
1505 {
1506         .init           = omap_sham_init,
1507         .update         = omap_sham_update,
1508         .final          = omap_sham_final,
1509         .finup          = omap_sham_finup,
1510         .digest         = omap_sham_digest,
1511         .setkey         = omap_sham_setkey,
1512         .halg.digestsize        = SHA1_DIGEST_SIZE,
1513         .halg.base      = {
1514                 .cra_name               = "hmac(sha1)",
1515                 .cra_driver_name        = "omap-hmac-sha1",
1516                 .cra_priority           = 400,
1517                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1518                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1519                                                 CRYPTO_ALG_ASYNC |
1520                                                 CRYPTO_ALG_NEED_FALLBACK,
1521                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1522                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1523                                         sizeof(struct omap_sham_hmac_ctx),
1524                 .cra_alignmask          = OMAP_ALIGN_MASK,
1525                 .cra_module             = THIS_MODULE,
1526                 .cra_init               = omap_sham_cra_sha1_init,
1527                 .cra_exit               = omap_sham_cra_exit,
1528         }
1529 },
1530 {
1531         .init           = omap_sham_init,
1532         .update         = omap_sham_update,
1533         .final          = omap_sham_final,
1534         .finup          = omap_sham_finup,
1535         .digest         = omap_sham_digest,
1536         .setkey         = omap_sham_setkey,
1537         .halg.digestsize        = MD5_DIGEST_SIZE,
1538         .halg.base      = {
1539                 .cra_name               = "hmac(md5)",
1540                 .cra_driver_name        = "omap-hmac-md5",
1541                 .cra_priority           = 400,
1542                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1543                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1544                                                 CRYPTO_ALG_ASYNC |
1545                                                 CRYPTO_ALG_NEED_FALLBACK,
1546                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1547                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1548                                         sizeof(struct omap_sham_hmac_ctx),
1549                 .cra_alignmask          = OMAP_ALIGN_MASK,
1550                 .cra_module             = THIS_MODULE,
1551                 .cra_init               = omap_sham_cra_md5_init,
1552                 .cra_exit               = omap_sham_cra_exit,
1553         }
1554 }
1555 };
1556
1557 /* OMAP4 has some algs in addition to what OMAP2 has */
1558 static struct ahash_alg algs_sha224_sha256[] = {
1559 {
1560         .init           = omap_sham_init,
1561         .update         = omap_sham_update,
1562         .final          = omap_sham_final,
1563         .finup          = omap_sham_finup,
1564         .digest         = omap_sham_digest,
1565         .halg.digestsize        = SHA224_DIGEST_SIZE,
1566         .halg.base      = {
1567                 .cra_name               = "sha224",
1568                 .cra_driver_name        = "omap-sha224",
1569                 .cra_priority           = 400,
1570                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1571                                                 CRYPTO_ALG_ASYNC |
1572                                                 CRYPTO_ALG_NEED_FALLBACK,
1573                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1574                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1575                 .cra_alignmask          = OMAP_ALIGN_MASK,
1576                 .cra_module             = THIS_MODULE,
1577                 .cra_init               = omap_sham_cra_init,
1578                 .cra_exit               = omap_sham_cra_exit,
1579         }
1580 },
1581 {
1582         .init           = omap_sham_init,
1583         .update         = omap_sham_update,
1584         .final          = omap_sham_final,
1585         .finup          = omap_sham_finup,
1586         .digest         = omap_sham_digest,
1587         .halg.digestsize        = SHA256_DIGEST_SIZE,
1588         .halg.base      = {
1589                 .cra_name               = "sha256",
1590                 .cra_driver_name        = "omap-sha256",
1591                 .cra_priority           = 400,
1592                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1593                                                 CRYPTO_ALG_ASYNC |
1594                                                 CRYPTO_ALG_NEED_FALLBACK,
1595                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1596                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1597                 .cra_alignmask          = OMAP_ALIGN_MASK,
1598                 .cra_module             = THIS_MODULE,
1599                 .cra_init               = omap_sham_cra_init,
1600                 .cra_exit               = omap_sham_cra_exit,
1601         }
1602 },
1603 {
1604         .init           = omap_sham_init,
1605         .update         = omap_sham_update,
1606         .final          = omap_sham_final,
1607         .finup          = omap_sham_finup,
1608         .digest         = omap_sham_digest,
1609         .setkey         = omap_sham_setkey,
1610         .halg.digestsize        = SHA224_DIGEST_SIZE,
1611         .halg.base      = {
1612                 .cra_name               = "hmac(sha224)",
1613                 .cra_driver_name        = "omap-hmac-sha224",
1614                 .cra_priority           = 400,
1615                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1616                                                 CRYPTO_ALG_ASYNC |
1617                                                 CRYPTO_ALG_NEED_FALLBACK,
1618                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1619                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1620                                         sizeof(struct omap_sham_hmac_ctx),
1621                 .cra_alignmask          = OMAP_ALIGN_MASK,
1622                 .cra_module             = THIS_MODULE,
1623                 .cra_init               = omap_sham_cra_sha224_init,
1624                 .cra_exit               = omap_sham_cra_exit,
1625         }
1626 },
1627 {
1628         .init           = omap_sham_init,
1629         .update         = omap_sham_update,
1630         .final          = omap_sham_final,
1631         .finup          = omap_sham_finup,
1632         .digest         = omap_sham_digest,
1633         .setkey         = omap_sham_setkey,
1634         .halg.digestsize        = SHA256_DIGEST_SIZE,
1635         .halg.base      = {
1636                 .cra_name               = "hmac(sha256)",
1637                 .cra_driver_name        = "omap-hmac-sha256",
1638                 .cra_priority           = 400,
1639                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1640                                                 CRYPTO_ALG_ASYNC |
1641                                                 CRYPTO_ALG_NEED_FALLBACK,
1642                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1643                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1644                                         sizeof(struct omap_sham_hmac_ctx),
1645                 .cra_alignmask          = OMAP_ALIGN_MASK,
1646                 .cra_module             = THIS_MODULE,
1647                 .cra_init               = omap_sham_cra_sha256_init,
1648                 .cra_exit               = omap_sham_cra_exit,
1649         }
1650 },
1651 };
1652
1653 static struct ahash_alg algs_sha384_sha512[] = {
1654 {
1655         .init           = omap_sham_init,
1656         .update         = omap_sham_update,
1657         .final          = omap_sham_final,
1658         .finup          = omap_sham_finup,
1659         .digest         = omap_sham_digest,
1660         .halg.digestsize        = SHA384_DIGEST_SIZE,
1661         .halg.base      = {
1662                 .cra_name               = "sha384",
1663                 .cra_driver_name        = "omap-sha384",
1664                 .cra_priority           = 400,
1665                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1666                                                 CRYPTO_ALG_ASYNC |
1667                                                 CRYPTO_ALG_NEED_FALLBACK,
1668                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1669                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1670                 .cra_alignmask          = OMAP_ALIGN_MASK,
1671                 .cra_module             = THIS_MODULE,
1672                 .cra_init               = omap_sham_cra_init,
1673                 .cra_exit               = omap_sham_cra_exit,
1674         }
1675 },
1676 {
1677         .init           = omap_sham_init,
1678         .update         = omap_sham_update,
1679         .final          = omap_sham_final,
1680         .finup          = omap_sham_finup,
1681         .digest         = omap_sham_digest,
1682         .halg.digestsize        = SHA512_DIGEST_SIZE,
1683         .halg.base      = {
1684                 .cra_name               = "sha512",
1685                 .cra_driver_name        = "omap-sha512",
1686                 .cra_priority           = 400,
1687                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1688                                                 CRYPTO_ALG_ASYNC |
1689                                                 CRYPTO_ALG_NEED_FALLBACK,
1690                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1691                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1692                 .cra_alignmask          = OMAP_ALIGN_MASK,
1693                 .cra_module             = THIS_MODULE,
1694                 .cra_init               = omap_sham_cra_init,
1695                 .cra_exit               = omap_sham_cra_exit,
1696         }
1697 },
1698 {
1699         .init           = omap_sham_init,
1700         .update         = omap_sham_update,
1701         .final          = omap_sham_final,
1702         .finup          = omap_sham_finup,
1703         .digest         = omap_sham_digest,
1704         .setkey         = omap_sham_setkey,
1705         .halg.digestsize        = SHA384_DIGEST_SIZE,
1706         .halg.base      = {
1707                 .cra_name               = "hmac(sha384)",
1708                 .cra_driver_name        = "omap-hmac-sha384",
1709                 .cra_priority           = 400,
1710                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1711                                                 CRYPTO_ALG_ASYNC |
1712                                                 CRYPTO_ALG_NEED_FALLBACK,
1713                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1714                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1715                                         sizeof(struct omap_sham_hmac_ctx),
1716                 .cra_alignmask          = OMAP_ALIGN_MASK,
1717                 .cra_module             = THIS_MODULE,
1718                 .cra_init               = omap_sham_cra_sha384_init,
1719                 .cra_exit               = omap_sham_cra_exit,
1720         }
1721 },
1722 {
1723         .init           = omap_sham_init,
1724         .update         = omap_sham_update,
1725         .final          = omap_sham_final,
1726         .finup          = omap_sham_finup,
1727         .digest         = omap_sham_digest,
1728         .setkey         = omap_sham_setkey,
1729         .halg.digestsize        = SHA512_DIGEST_SIZE,
1730         .halg.base      = {
1731                 .cra_name               = "hmac(sha512)",
1732                 .cra_driver_name        = "omap-hmac-sha512",
1733                 .cra_priority           = 400,
1734                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1735                                                 CRYPTO_ALG_ASYNC |
1736                                                 CRYPTO_ALG_NEED_FALLBACK,
1737                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1738                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1739                                         sizeof(struct omap_sham_hmac_ctx),
1740                 .cra_alignmask          = OMAP_ALIGN_MASK,
1741                 .cra_module             = THIS_MODULE,
1742                 .cra_init               = omap_sham_cra_sha512_init,
1743                 .cra_exit               = omap_sham_cra_exit,
1744         }
1745 },
1746 };
1747
1748 static void omap_sham_done_task(unsigned long data)
1749 {
1750         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1751         int err = 0;
1752
1753         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1754                 omap_sham_handle_queue(dd, NULL);
1755                 return;
1756         }
1757
1758         if (test_bit(FLAGS_CPU, &dd->flags)) {
1759                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1760                         goto finish;
1761         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1762                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1763                         omap_sham_update_dma_stop(dd);
1764                         if (dd->err) {
1765                                 err = dd->err;
1766                                 goto finish;
1767                         }
1768                 }
1769                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1770                         /* hash or semi-hash ready */
1771                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1772                                 goto finish;
1773                 }
1774         }
1775
1776         return;
1777
1778 finish:
1779         dev_dbg(dd->dev, "update done: err: %d\n", err);
1780         /* finish curent request */
1781         omap_sham_finish_req(dd->req, err);
1782
1783         /* If we are not busy, process next req */
1784         if (!test_bit(FLAGS_BUSY, &dd->flags))
1785                 omap_sham_handle_queue(dd, NULL);
1786 }
1787
1788 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1789 {
1790         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1791                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1792         } else {
1793                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1794                 tasklet_schedule(&dd->done_task);
1795         }
1796
1797         return IRQ_HANDLED;
1798 }
1799
1800 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1801 {
1802         struct omap_sham_dev *dd = dev_id;
1803
1804         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1805                 /* final -> allow device to go to power-saving mode */
1806                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1807
1808         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1809                                  SHA_REG_CTRL_OUTPUT_READY);
1810         omap_sham_read(dd, SHA_REG_CTRL);
1811
1812         return omap_sham_irq_common(dd);
1813 }
1814
1815 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1816 {
1817         struct omap_sham_dev *dd = dev_id;
1818
1819         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1820
1821         return omap_sham_irq_common(dd);
1822 }
1823
1824 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1825         {
1826                 .algs_list      = algs_sha1_md5,
1827                 .size           = ARRAY_SIZE(algs_sha1_md5),
1828         },
1829 };
1830
1831 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1832         .algs_info      = omap_sham_algs_info_omap2,
1833         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1834         .flags          = BIT(FLAGS_BE32_SHA1),
1835         .digest_size    = SHA1_DIGEST_SIZE,
1836         .copy_hash      = omap_sham_copy_hash_omap2,
1837         .write_ctrl     = omap_sham_write_ctrl_omap2,
1838         .trigger        = omap_sham_trigger_omap2,
1839         .poll_irq       = omap_sham_poll_irq_omap2,
1840         .intr_hdlr      = omap_sham_irq_omap2,
1841         .idigest_ofs    = 0x00,
1842         .din_ofs        = 0x1c,
1843         .digcnt_ofs     = 0x14,
1844         .rev_ofs        = 0x5c,
1845         .mask_ofs       = 0x60,
1846         .sysstatus_ofs  = 0x64,
1847         .major_mask     = 0xf0,
1848         .major_shift    = 4,
1849         .minor_mask     = 0x0f,
1850         .minor_shift    = 0,
1851 };
1852
1853 #ifdef CONFIG_OF
1854 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1855         {
1856                 .algs_list      = algs_sha1_md5,
1857                 .size           = ARRAY_SIZE(algs_sha1_md5),
1858         },
1859         {
1860                 .algs_list      = algs_sha224_sha256,
1861                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1862         },
1863 };
1864
1865 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1866         .algs_info      = omap_sham_algs_info_omap4,
1867         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1868         .flags          = BIT(FLAGS_AUTO_XOR),
1869         .digest_size    = SHA256_DIGEST_SIZE,
1870         .copy_hash      = omap_sham_copy_hash_omap4,
1871         .write_ctrl     = omap_sham_write_ctrl_omap4,
1872         .trigger        = omap_sham_trigger_omap4,
1873         .poll_irq       = omap_sham_poll_irq_omap4,
1874         .intr_hdlr      = omap_sham_irq_omap4,
1875         .idigest_ofs    = 0x020,
1876         .odigest_ofs    = 0x0,
1877         .din_ofs        = 0x080,
1878         .digcnt_ofs     = 0x040,
1879         .rev_ofs        = 0x100,
1880         .mask_ofs       = 0x110,
1881         .sysstatus_ofs  = 0x114,
1882         .mode_ofs       = 0x44,
1883         .length_ofs     = 0x48,
1884         .major_mask     = 0x0700,
1885         .major_shift    = 8,
1886         .minor_mask     = 0x003f,
1887         .minor_shift    = 0,
1888 };
1889
1890 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1891         {
1892                 .algs_list      = algs_sha1_md5,
1893                 .size           = ARRAY_SIZE(algs_sha1_md5),
1894         },
1895         {
1896                 .algs_list      = algs_sha224_sha256,
1897                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1898         },
1899         {
1900                 .algs_list      = algs_sha384_sha512,
1901                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1902         },
1903 };
1904
1905 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1906         .algs_info      = omap_sham_algs_info_omap5,
1907         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1908         .flags          = BIT(FLAGS_AUTO_XOR),
1909         .digest_size    = SHA512_DIGEST_SIZE,
1910         .copy_hash      = omap_sham_copy_hash_omap4,
1911         .write_ctrl     = omap_sham_write_ctrl_omap4,
1912         .trigger        = omap_sham_trigger_omap4,
1913         .poll_irq       = omap_sham_poll_irq_omap4,
1914         .intr_hdlr      = omap_sham_irq_omap4,
1915         .idigest_ofs    = 0x240,
1916         .odigest_ofs    = 0x200,
1917         .din_ofs        = 0x080,
1918         .digcnt_ofs     = 0x280,
1919         .rev_ofs        = 0x100,
1920         .mask_ofs       = 0x110,
1921         .sysstatus_ofs  = 0x114,
1922         .mode_ofs       = 0x284,
1923         .length_ofs     = 0x288,
1924         .major_mask     = 0x0700,
1925         .major_shift    = 8,
1926         .minor_mask     = 0x003f,
1927         .minor_shift    = 0,
1928 };
1929
1930 static const struct of_device_id omap_sham_of_match[] = {
1931         {
1932                 .compatible     = "ti,omap2-sham",
1933                 .data           = &omap_sham_pdata_omap2,
1934         },
1935         {
1936                 .compatible     = "ti,omap3-sham",
1937                 .data           = &omap_sham_pdata_omap2,
1938         },
1939         {
1940                 .compatible     = "ti,omap4-sham",
1941                 .data           = &omap_sham_pdata_omap4,
1942         },
1943         {
1944                 .compatible     = "ti,omap5-sham",
1945                 .data           = &omap_sham_pdata_omap5,
1946         },
1947         {},
1948 };
1949 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1950
1951 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1952                 struct device *dev, struct resource *res)
1953 {
1954         struct device_node *node = dev->of_node;
1955         int err = 0;
1956
1957         dd->pdata = of_device_get_match_data(dev);
1958         if (!dd->pdata) {
1959                 dev_err(dev, "no compatible OF match\n");
1960                 err = -EINVAL;
1961                 goto err;
1962         }
1963
1964         err = of_address_to_resource(node, 0, res);
1965         if (err < 0) {
1966                 dev_err(dev, "can't translate OF node address\n");
1967                 err = -EINVAL;
1968                 goto err;
1969         }
1970
1971         dd->irq = irq_of_parse_and_map(node, 0);
1972         if (!dd->irq) {
1973                 dev_err(dev, "can't translate OF irq value\n");
1974                 err = -EINVAL;
1975                 goto err;
1976         }
1977
1978 err:
1979         return err;
1980 }
1981 #else
1982 static const struct of_device_id omap_sham_of_match[] = {
1983         {},
1984 };
1985
1986 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1987                 struct device *dev, struct resource *res)
1988 {
1989         return -EINVAL;
1990 }
1991 #endif
1992
1993 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1994                 struct platform_device *pdev, struct resource *res)
1995 {
1996         struct device *dev = &pdev->dev;
1997         struct resource *r;
1998         int err = 0;
1999
2000         /* Get the base address */
2001         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2002         if (!r) {
2003                 dev_err(dev, "no MEM resource info\n");
2004                 err = -ENODEV;
2005                 goto err;
2006         }
2007         memcpy(res, r, sizeof(*res));
2008
2009         /* Get the IRQ */
2010         dd->irq = platform_get_irq(pdev, 0);
2011         if (dd->irq < 0) {
2012                 dev_err(dev, "no IRQ resource info\n");
2013                 err = dd->irq;
2014                 goto err;
2015         }
2016
2017         /* Only OMAP2/3 can be non-DT */
2018         dd->pdata = &omap_sham_pdata_omap2;
2019
2020 err:
2021         return err;
2022 }
2023
2024 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2025                              char *buf)
2026 {
2027         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2028
2029         return sprintf(buf, "%d\n", dd->fallback_sz);
2030 }
2031
2032 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2033                               const char *buf, size_t size)
2034 {
2035         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2036         ssize_t status;
2037         long value;
2038
2039         status = kstrtol(buf, 0, &value);
2040         if (status)
2041                 return status;
2042
2043         /* HW accelerator only works with buffers > 9 */
2044         if (value < 9) {
2045                 dev_err(dev, "minimum fallback size 9\n");
2046                 return -EINVAL;
2047         }
2048
2049         dd->fallback_sz = value;
2050
2051         return size;
2052 }
2053
2054 static DEVICE_ATTR_RW(fallback);
2055
2056 static struct attribute *omap_sham_attrs[] = {
2057         &dev_attr_fallback.attr,
2058         NULL,
2059 };
2060
2061 static struct attribute_group omap_sham_attr_group = {
2062         .attrs = omap_sham_attrs,
2063 };
2064
2065 static int omap_sham_probe(struct platform_device *pdev)
2066 {
2067         struct omap_sham_dev *dd;
2068         struct device *dev = &pdev->dev;
2069         struct resource res;
2070         dma_cap_mask_t mask;
2071         int err, i, j;
2072         u32 rev;
2073
2074         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2075         if (dd == NULL) {
2076                 dev_err(dev, "unable to alloc data struct.\n");
2077                 err = -ENOMEM;
2078                 goto data_err;
2079         }
2080         dd->dev = dev;
2081         platform_set_drvdata(pdev, dd);
2082
2083         INIT_LIST_HEAD(&dd->list);
2084         spin_lock_init(&dd->lock);
2085         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2086         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2087
2088         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2089                                omap_sham_get_res_pdev(dd, pdev, &res);
2090         if (err)
2091                 goto data_err;
2092
2093         dd->io_base = devm_ioremap_resource(dev, &res);
2094         if (IS_ERR(dd->io_base)) {
2095                 err = PTR_ERR(dd->io_base);
2096                 goto data_err;
2097         }
2098         dd->phys_base = res.start;
2099
2100         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2101                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2102         if (err) {
2103                 dev_err(dev, "unable to request irq %d, err = %d\n",
2104                         dd->irq, err);
2105                 goto data_err;
2106         }
2107
2108         dma_cap_zero(mask);
2109         dma_cap_set(DMA_SLAVE, mask);
2110
2111         dd->dma_lch = dma_request_chan(dev, "rx");
2112         if (IS_ERR(dd->dma_lch)) {
2113                 err = PTR_ERR(dd->dma_lch);
2114                 if (err == -EPROBE_DEFER)
2115                         goto data_err;
2116
2117                 dd->polling_mode = 1;
2118                 dev_dbg(dev, "using polling mode instead of dma\n");
2119         }
2120
2121         dd->flags |= dd->pdata->flags;
2122
2123         pm_runtime_use_autosuspend(dev);
2124         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2125
2126         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2127
2128         pm_runtime_enable(dev);
2129         pm_runtime_irq_safe(dev);
2130
2131         err = pm_runtime_get_sync(dev);
2132         if (err < 0) {
2133                 dev_err(dev, "failed to get sync: %d\n", err);
2134                 goto err_pm;
2135         }
2136
2137         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2138         pm_runtime_put_sync(&pdev->dev);
2139
2140         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2141                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2142                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2143
2144         spin_lock(&sham.lock);
2145         list_add_tail(&dd->list, &sham.dev_list);
2146         spin_unlock(&sham.lock);
2147
2148         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2149                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2150                         struct ahash_alg *alg;
2151
2152                         alg = &dd->pdata->algs_info[i].algs_list[j];
2153                         alg->export = omap_sham_export;
2154                         alg->import = omap_sham_import;
2155                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2156                                               BUFLEN;
2157                         err = crypto_register_ahash(alg);
2158                         if (err)
2159                                 goto err_algs;
2160
2161                         dd->pdata->algs_info[i].registered++;
2162                 }
2163         }
2164
2165         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2166         if (err) {
2167                 dev_err(dev, "could not create sysfs device attrs\n");
2168                 goto err_algs;
2169         }
2170
2171         return 0;
2172
2173 err_algs:
2174         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2175                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2176                         crypto_unregister_ahash(
2177                                         &dd->pdata->algs_info[i].algs_list[j]);
2178 err_pm:
2179         pm_runtime_disable(dev);
2180         if (!dd->polling_mode)
2181                 dma_release_channel(dd->dma_lch);
2182 data_err:
2183         dev_err(dev, "initialization failed.\n");
2184
2185         return err;
2186 }
2187
2188 static int omap_sham_remove(struct platform_device *pdev)
2189 {
2190         struct omap_sham_dev *dd;
2191         int i, j;
2192
2193         dd = platform_get_drvdata(pdev);
2194         if (!dd)
2195                 return -ENODEV;
2196         spin_lock(&sham.lock);
2197         list_del(&dd->list);
2198         spin_unlock(&sham.lock);
2199         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2200                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2201                         crypto_unregister_ahash(
2202                                         &dd->pdata->algs_info[i].algs_list[j]);
2203         tasklet_kill(&dd->done_task);
2204         pm_runtime_disable(&pdev->dev);
2205
2206         if (!dd->polling_mode)
2207                 dma_release_channel(dd->dma_lch);
2208
2209         return 0;
2210 }
2211
2212 #ifdef CONFIG_PM_SLEEP
2213 static int omap_sham_suspend(struct device *dev)
2214 {
2215         pm_runtime_put_sync(dev);
2216         return 0;
2217 }
2218
2219 static int omap_sham_resume(struct device *dev)
2220 {
2221         int err = pm_runtime_get_sync(dev);
2222         if (err < 0) {
2223                 dev_err(dev, "failed to get sync: %d\n", err);
2224                 return err;
2225         }
2226         return 0;
2227 }
2228 #endif
2229
2230 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2231
2232 static struct platform_driver omap_sham_driver = {
2233         .probe  = omap_sham_probe,
2234         .remove = omap_sham_remove,
2235         .driver = {
2236                 .name   = "omap-sham",
2237                 .pm     = &omap_sham_pm_ops,
2238                 .of_match_table = omap_sham_of_match,
2239         },
2240 };
2241
2242 module_platform_driver(omap_sham_driver);
2243
2244 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2245 MODULE_LICENSE("GPL v2");
2246 MODULE_AUTHOR("Dmitry Kasatkin");
2247 MODULE_ALIAS("platform:omap-sham");