drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         struct omap_sham_dev    *dd;
 172
 173         unsigned long           flags;
 174
 175         /* fallback stuff */
 176         struct crypto_shash     *fallback;
 177
 178         struct omap_sham_hmac_ctx base[0];
 179 };
 180
 181 #define OMAP_SHAM_QUEUE_LENGTH  10
 182
 183 struct omap_sham_algs_info {
 184         struct ahash_alg        *algs_list;
 185         unsigned int            size;
 186         unsigned int            registered;
 187 };
 188
 189 struct omap_sham_pdata {
 190         struct omap_sham_algs_info      *algs_info;
 191         unsigned int    algs_info_size;
 192         unsigned long   flags;
 193         int             digest_size;
 194
 195         void            (*copy_hash)(struct ahash_request *req, int out);
 196         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 197                                       int final, int dma);
 198         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 199         int             (*poll_irq)(struct omap_sham_dev *dd);
 200         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 201
 202         u32             odigest_ofs;
 203         u32             idigest_ofs;
 204         u32             din_ofs;
 205         u32             digcnt_ofs;
 206         u32             rev_ofs;
 207         u32             mask_ofs;
 208         u32             sysstatus_ofs;
 209         u32             mode_ofs;
 210         u32             length_ofs;
 211
 212         u32             major_mask;
 213         u32             major_shift;
 214         u32             minor_mask;
 215         u32             minor_shift;
 216 };
 217
 218 struct omap_sham_dev {
 219         struct list_head        list;
 220         unsigned long           phys_base;
 221         struct device           *dev;
 222         void __iomem            *io_base;
 223         int                     irq;
 224         spinlock_t              lock;
 225         int                     err;
 226         struct dma_chan         *dma_lch;
 227         struct tasklet_struct   done_task;
 228         u8                      polling_mode;
 229         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 230
 231         unsigned long           flags;
 232         struct crypto_queue     queue;
 233         struct ahash_request    *req;
 234
 235         const struct omap_sham_pdata    *pdata;
 236 };
 237
 238 struct omap_sham_drv {
 239         struct list_head        dev_list;
 240         spinlock_t              lock;
 241         unsigned long           flags;
 242 };
 243
 244 static struct omap_sham_drv sham = {
 245         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 246         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 247 };
 248
 249 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 250 {
 251         return __raw_readl(dd->io_base + offset);
 252 }
 253
 254 static inline void omap_sham_write(struct omap_sham_dev *dd,
 255                                         u32 offset, u32 value)
 256 {
 257         __raw_writel(value, dd->io_base + offset);
 258 }
 259
 260 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 261                                         u32 value, u32 mask)
 262 {
 263         u32 val;
 264
 265         val = omap_sham_read(dd, address);
 266         val &= ~mask;
 267         val |= value;
 268         omap_sham_write(dd, address, val);
 269 }
 270
 271 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 272 {
 273         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 274
 275         while (!(omap_sham_read(dd, offset) & bit)) {
 276                 if (time_is_before_jiffies(timeout))
 277                         return -ETIMEDOUT;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 284 {
 285         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 286         struct omap_sham_dev *dd = ctx->dd;
 287         u32 *hash = (u32 *)ctx->digest;
 288         int i;
 289
 290         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 291                 if (out)
 292                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 293                 else
 294                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 295         }
 296 }
 297
 298 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 299 {
 300         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 301         struct omap_sham_dev *dd = ctx->dd;
 302         int i;
 303
 304         if (ctx->flags & BIT(FLAGS_HMAC)) {
 305                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 306                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 307                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 308                 u32 *opad = (u32 *)bctx->opad;
 309
 310                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 311                         if (out)
 312                                 opad[i] = omap_sham_read(dd,
 313                                                 SHA_REG_ODIGEST(dd, i));
 314                         else
 315                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 316                                                 opad[i]);
 317                 }
 318         }
 319
 320         omap_sham_copy_hash_omap2(req, out);
 321 }
 322
 323 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 324 {
 325         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 326         u32 *in = (u32 *)ctx->digest;
 327         u32 *hash = (u32 *)req->result;
 328         int i, d, big_endian = 0;
 329
 330         if (!hash)
 331                 return;
 332
 333         switch (ctx->flags & FLAGS_MODE_MASK) {
 334         case FLAGS_MODE_MD5:
 335                 d = MD5_DIGEST_SIZE / sizeof(u32);
 336                 break;
 337         case FLAGS_MODE_SHA1:
 338                 /* OMAP2 SHA1 is big endian */
 339                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 340                         big_endian = 1;
 341                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 342                 break;
 343         case FLAGS_MODE_SHA224:
 344                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 345                 break;
 346         case FLAGS_MODE_SHA256:
 347                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 348                 break;
 349         case FLAGS_MODE_SHA384:
 350                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 351                 break;
 352         case FLAGS_MODE_SHA512:
 353                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 354                 break;
 355         default:
 356                 d = 0;
 357         }
 358
 359         if (big_endian)
 360                 for (i = 0; i < d; i++)
 361                         hash[i] = be32_to_cpu(in[i]);
 362         else
 363                 for (i = 0; i < d; i++)
 364                         hash[i] = le32_to_cpu(in[i]);
 365 }
 366
 367 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 368 {
 369         int err;
 370
 371         err = pm_runtime_get_sync(dd->dev);
 372         if (err < 0) {
 373                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 374                 return err;
 375         }
 376
 377         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 378                 set_bit(FLAGS_INIT, &dd->flags);
 379                 dd->err = 0;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 386                                  int final, int dma)
 387 {
 388         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 389         u32 val = length << 5, mask;
 390
 391         if (likely(ctx->digcnt))
 392                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 393
 394         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 395                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 396                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 397         /*
 398          * Setting ALGO_CONST only for the first iteration
 399          * and CLOSE_HASH only for the last one.
 400          */
 401         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 402                 val |= SHA_REG_CTRL_ALGO;
 403         if (!ctx->digcnt)
 404                 val |= SHA_REG_CTRL_ALGO_CONST;
 405         if (final)
 406                 val |= SHA_REG_CTRL_CLOSE_HASH;
 407
 408         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 409                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 410
 411         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 412 }
 413
 414 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 415 {
 416 }
 417
 418 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 419 {
 420         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 421 }
 422
 423 static int get_block_size(struct omap_sham_reqctx *ctx)
 424 {
 425         int d;
 426
 427         switch (ctx->flags & FLAGS_MODE_MASK) {
 428         case FLAGS_MODE_MD5:
 429         case FLAGS_MODE_SHA1:
 430                 d = SHA1_BLOCK_SIZE;
 431                 break;
 432         case FLAGS_MODE_SHA224:
 433         case FLAGS_MODE_SHA256:
 434                 d = SHA256_BLOCK_SIZE;
 435                 break;
 436         case FLAGS_MODE_SHA384:
 437         case FLAGS_MODE_SHA512:
 438                 d = SHA512_BLOCK_SIZE;
 439                 break;
 440         default:
 441                 d = 0;
 442         }
 443
 444         return d;
 445 }
 446
 447 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 448                                     u32 *value, int count)
 449 {
 450         for (; count--; value++, offset += 4)
 451                 omap_sham_write(dd, offset, *value);
 452 }
 453
 454 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 455                                  int final, int dma)
 456 {
 457         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 458         u32 val, mask;
 459
 460         /*
 461          * Setting ALGO_CONST only for the first iteration and
 462          * CLOSE_HASH only for the last one. Note that flags mode bits
 463          * correspond to algorithm encoding in mode register.
 464          */
 465         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 466         if (!ctx->digcnt) {
 467                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 468                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 469                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 470                 int bs, nr_dr;
 471
 472                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 473
 474                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 475                         bs = get_block_size(ctx);
 476                         nr_dr = bs / (2 * sizeof(u32));
 477                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 478                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 479                                           (u32 *)bctx->ipad, nr_dr);
 480                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 482                         ctx->digcnt += bs;
 483                 }
 484         }
 485
 486         if (final) {
 487                 val |= SHA_REG_MODE_CLOSE_HASH;
 488
 489                 if (ctx->flags & BIT(FLAGS_HMAC))
 490                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 491         }
 492
 493         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 494                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 495                SHA_REG_MODE_HMAC_KEY_PROC;
 496
 497         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 498         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 499         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 500         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 501                              SHA_REG_MASK_IT_EN |
 502                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 503                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 504 }
 505
 506 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 507 {
 508         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 509 }
 510
 511 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 512 {
 513         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 514                               SHA_REG_IRQSTATUS_INPUT_RDY);
 515 }
 516
 517 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 518                               int final)
 519 {
 520         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 521         int count, len32, bs32, offset = 0;
 522         const u32 *buffer;
 523         int mlen;
 524         struct sg_mapping_iter mi;
 525
 526         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 527                                                 ctx->digcnt, length, final);
 528
 529         dd->pdata->write_ctrl(dd, length, final, 0);
 530         dd->pdata->trigger(dd, length);
 531
 532         /* should be non-zero before next lines to disable clocks later */
 533         ctx->digcnt += length;
 534         ctx->total -= length;
 535
 536         if (final)
 537                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 538
 539         set_bit(FLAGS_CPU, &dd->flags);
 540
 541         len32 = DIV_ROUND_UP(length, sizeof(u32));
 542         bs32 = get_block_size(ctx) / sizeof(u32);
 543
 544         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 545                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 546
 547         mlen = 0;
 548
 549         while (len32) {
 550                 if (dd->pdata->poll_irq(dd))
 551                         return -ETIMEDOUT;
 552
 553                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 554                         if (!mlen) {
 555                                 sg_miter_next(&mi);
 556                                 mlen = mi.length;
 557                                 if (!mlen) {
 558                                         pr_err("sg miter failure.\n");
 559                                         return -EINVAL;
 560                                 }
 561                                 offset = 0;
 562                                 buffer = mi.addr;
 563                         }
 564                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 565                                         buffer[offset]);
 566                         mlen -= 4;
 567                 }
 568                 len32 -= min(len32, bs32);
 569         }
 570
 571         sg_miter_stop(&mi);
 572
 573         return -EINPROGRESS;
 574 }
 575
 576 static void omap_sham_dma_callback(void *param)
 577 {
 578         struct omap_sham_dev *dd = param;
 579
 580         set_bit(FLAGS_DMA_READY, &dd->flags);
 581         tasklet_schedule(&dd->done_task);
 582 }
 583
 584 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 585                               int final)
 586 {
 587         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 588         struct dma_async_tx_descriptor *tx;
 589         struct dma_slave_config cfg;
 590         int ret;
 591
 592         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 593                                                 ctx->digcnt, length, final);
 594
 595         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 596                 dev_err(dd->dev, "dma_map_sg error\n");
 597                 return -EINVAL;
 598         }
 599
 600         memset(&cfg, 0, sizeof(cfg));
 601
 602         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 603         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 604         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 605
 606         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 607         if (ret) {
 608                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 609                 return ret;
 610         }
 611
 612         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 613                                      DMA_MEM_TO_DEV,
 614                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 615
 616         if (!tx) {
 617                 dev_err(dd->dev, "prep_slave_sg failed\n");
 618                 return -EINVAL;
 619         }
 620
 621         tx->callback = omap_sham_dma_callback;
 622         tx->callback_param = dd;
 623
 624         dd->pdata->write_ctrl(dd, length, final, 1);
 625
 626         ctx->digcnt += length;
 627         ctx->total -= length;
 628
 629         if (final)
 630                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 631
 632         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 633
 634         dmaengine_submit(tx);
 635         dma_async_issue_pending(dd->dma_lch);
 636
 637         dd->pdata->trigger(dd, length);
 638
 639         return -EINPROGRESS;
 640 }
 641
 642 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 643                                    struct scatterlist *sg, int bs, int new_len)
 644 {
 645         int n = sg_nents(sg);
 646         struct scatterlist *tmp;
 647         int offset = ctx->offset;
 648
 649         if (ctx->bufcnt)
 650                 n++;
 651
 652         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 653         if (!ctx->sg)
 654                 return -ENOMEM;
 655
 656         sg_init_table(ctx->sg, n);
 657
 658         tmp = ctx->sg;
 659
 660         ctx->sg_len = 0;
 661
 662         if (ctx->bufcnt) {
 663                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 664                 tmp = sg_next(tmp);
 665                 ctx->sg_len++;
 666         }
 667
 668         while (sg && new_len) {
 669                 int len = sg->length - offset;
 670
 671                 if (offset) {
 672                         offset -= sg->length;
 673                         if (offset < 0)
 674                                 offset = 0;
 675                 }
 676
 677                 if (new_len < len)
 678                         len = new_len;
 679
 680                 if (len > 0) {
 681                         new_len -= len;
 682                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 683                         if (new_len <= 0)
 684                                 sg_mark_end(tmp);
 685                         tmp = sg_next(tmp);
 686                         ctx->sg_len++;
 687                 }
 688
 689                 sg = sg_next(sg);
 690         }
 691
 692         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 693
 694         ctx->bufcnt = 0;
 695
 696         return 0;
 697 }
 698
 699 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 700                               struct scatterlist *sg, int bs, int new_len)
 701 {
 702         int pages;
 703         void *buf;
 704         int len;
 705
 706         len = new_len + ctx->bufcnt;
 707
 708         pages = get_order(ctx->total);
 709
 710         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 711         if (!buf) {
 712                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 713                 return -ENOMEM;
 714         }
 715
 716         if (ctx->bufcnt)
 717                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 718
 719         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 720                                  ctx->total - ctx->bufcnt, 0);
 721         sg_init_table(ctx->sgl, 1);
 722         sg_set_buf(ctx->sgl, buf, len);
 723         ctx->sg = ctx->sgl;
 724         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 725         ctx->sg_len = 1;
 726         ctx->bufcnt = 0;
 727         ctx->offset = 0;
 728
 729         return 0;
 730 }
 731
 732 static int omap_sham_align_sgs(struct scatterlist *sg,
 733                                int nbytes, int bs, bool final,
 734                                struct omap_sham_reqctx *rctx)
 735 {
 736         int n = 0;
 737         bool aligned = true;
 738         bool list_ok = true;
 739         struct scatterlist *sg_tmp = sg;
 740         int new_len;
 741         int offset = rctx->offset;
 742
 743         if (!sg || !sg->length || !nbytes)
 744                 return 0;
 745
 746         new_len = nbytes;
 747
 748         if (offset)
 749                 list_ok = false;
 750
 751         if (final)
 752                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 753         else
 754                 new_len = (new_len - 1) / bs * bs;
 755
 756         if (nbytes != new_len)
 757                 list_ok = false;
 758
 759         while (nbytes > 0 && sg_tmp) {
 760                 n++;
 761
 762 #ifdef CONFIG_ZONE_DMA
 763                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 764                         aligned = false;
 765                         break;
 766                 }
 767 #endif
 768
 769                 if (offset < sg_tmp->length) {
 770                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 771                                 aligned = false;
 772                                 break;
 773                         }
 774
 775                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 776                                 aligned = false;
 777                                 break;
 778                         }
 779                 }
 780
 781                 if (offset) {
 782                         offset -= sg_tmp->length;
 783                         if (offset < 0) {
 784                                 nbytes += offset;
 785                                 offset = 0;
 786                         }
 787                 } else {
 788                         nbytes -= sg_tmp->length;
 789                 }
 790
 791                 sg_tmp = sg_next(sg_tmp);
 792
 793                 if (nbytes < 0) {
 794                         list_ok = false;
 795                         break;
 796                 }
 797         }
 798
 799         if (!aligned)
 800                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 801         else if (!list_ok)
 802                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 803
 804         rctx->sg_len = n;
 805         rctx->sg = sg;
 806
 807         return 0;
 808 }
 809
 810 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 811 {
 812         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 813         int bs;
 814         int ret;
 815         int nbytes;
 816         bool final = rctx->flags & BIT(FLAGS_FINUP);
 817         int xmit_len, hash_later;
 818
 819         if (!req)
 820                 return 0;
 821
 822         bs = get_block_size(rctx);
 823
 824         if (update)
 825                 nbytes = req->nbytes;
 826         else
 827                 nbytes = 0;
 828
 829         rctx->total = nbytes + rctx->bufcnt;
 830
 831         if (!rctx->total)
 832                 return 0;
 833
 834         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 835                 int len = bs - rctx->bufcnt % bs;
 836
 837                 if (len > nbytes)
 838                         len = nbytes;
 839                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 840                                          0, len, 0);
 841                 rctx->bufcnt += len;
 842                 nbytes -= len;
 843                 rctx->offset = len;
 844         }
 845
 846         if (rctx->bufcnt)
 847                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 848
 849         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 850         if (ret)
 851                 return ret;
 852
 853         xmit_len = rctx->total;
 854
 855         if (!IS_ALIGNED(xmit_len, bs)) {
 856                 if (final)
 857                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 858                 else
 859                         xmit_len = xmit_len / bs * bs;
 860         } else if (!final) {
 861                 xmit_len -= bs;
 862         }
 863
 864         hash_later = rctx->total - xmit_len;
 865         if (hash_later < 0)
 866                 hash_later = 0;
 867
 868         if (rctx->bufcnt && nbytes) {
 869                 /* have data from previous operation and current */
 870                 sg_init_table(rctx->sgl, 2);
 871                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 872
 873                 sg_chain(rctx->sgl, 2, req->src);
 874
 875                 rctx->sg = rctx->sgl;
 876
 877                 rctx->sg_len++;
 878         } else if (rctx->bufcnt) {
 879                 /* have buffered data only */
 880                 sg_init_table(rctx->sgl, 1);
 881                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 882
 883                 rctx->sg = rctx->sgl;
 884
 885                 rctx->sg_len = 1;
 886         }
 887
 888         if (hash_later) {
 889                 int offset = 0;
 890
 891                 if (hash_later > req->nbytes) {
 892                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 893                                hash_later - req->nbytes);
 894                         offset = hash_later - req->nbytes;
 895                 }
 896
 897                 if (req->nbytes) {
 898                         scatterwalk_map_and_copy(rctx->buffer + offset,
 899                                                  req->src,
 900                                                  offset + req->nbytes -
 901                                                  hash_later, hash_later, 0);
 902                 }
 903
 904                 rctx->bufcnt = hash_later;
 905         } else {
 906                 rctx->bufcnt = 0;
 907         }
 908
 909         if (!final)
 910                 rctx->total = xmit_len;
 911
 912         return 0;
 913 }
 914
 915 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 916 {
 917         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 918
 919         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 920
 921         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 922
 923         return 0;
 924 }
 925
 926 static int omap_sham_init(struct ahash_request *req)
 927 {
 928         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 929         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 930         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 931         struct omap_sham_dev *dd = NULL, *tmp;
 932         int bs = 0;
 933
 934         spin_lock_bh(&sham.lock);
 935         if (!tctx->dd) {
 936                 list_for_each_entry(tmp, &sham.dev_list, list) {
 937                         dd = tmp;
 938                         break;
 939                 }
 940                 tctx->dd = dd;
 941         } else {
 942                 dd = tctx->dd;
 943         }
 944         spin_unlock_bh(&sham.lock);
 945
 946         ctx->dd = dd;
 947
 948         ctx->flags = 0;
 949
 950         dev_dbg(dd->dev, "init: digest size: %d\n",
 951                 crypto_ahash_digestsize(tfm));
 952
 953         switch (crypto_ahash_digestsize(tfm)) {
 954         case MD5_DIGEST_SIZE:
 955                 ctx->flags |= FLAGS_MODE_MD5;
 956                 bs = SHA1_BLOCK_SIZE;
 957                 break;
 958         case SHA1_DIGEST_SIZE:
 959                 ctx->flags |= FLAGS_MODE_SHA1;
 960                 bs = SHA1_BLOCK_SIZE;
 961                 break;
 962         case SHA224_DIGEST_SIZE:
 963                 ctx->flags |= FLAGS_MODE_SHA224;
 964                 bs = SHA224_BLOCK_SIZE;
 965                 break;
 966         case SHA256_DIGEST_SIZE:
 967                 ctx->flags |= FLAGS_MODE_SHA256;
 968                 bs = SHA256_BLOCK_SIZE;
 969                 break;
 970         case SHA384_DIGEST_SIZE:
 971                 ctx->flags |= FLAGS_MODE_SHA384;
 972                 bs = SHA384_BLOCK_SIZE;
 973                 break;
 974         case SHA512_DIGEST_SIZE:
 975                 ctx->flags |= FLAGS_MODE_SHA512;
 976                 bs = SHA512_BLOCK_SIZE;
 977                 break;
 978         }
 979
 980         ctx->bufcnt = 0;
 981         ctx->digcnt = 0;
 982         ctx->total = 0;
 983         ctx->offset = 0;
 984         ctx->buflen = BUFLEN;
 985
 986         if (tctx->flags & BIT(FLAGS_HMAC)) {
 987                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 988                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 989
 990                         memcpy(ctx->buffer, bctx->ipad, bs);
 991                         ctx->bufcnt = bs;
 992                 }
 993
 994                 ctx->flags |= BIT(FLAGS_HMAC);
 995         }
 996
 997         return 0;
 998
 999 }
1000
1001 static int omap_sham_update_req(struct omap_sham_dev *dd)
1002 {
1003         struct ahash_request *req = dd->req;
1004         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1005         int err;
1006         bool final = ctx->flags & BIT(FLAGS_FINUP);
1007
1008         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1009                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1010
1011         if (ctx->total < get_block_size(ctx) ||
1012             ctx->total < OMAP_SHA_DMA_THRESHOLD)
1013                 ctx->flags |= BIT(FLAGS_CPU);
1014
1015         if (ctx->flags & BIT(FLAGS_CPU))
1016                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1017         else
1018                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1019
1020         /* wait for dma completion before can take more data */
1021         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1022
1023         return err;
1024 }
1025
1026 static int omap_sham_final_req(struct omap_sham_dev *dd)
1027 {
1028         struct ahash_request *req = dd->req;
1029         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1030         int err = 0, use_dma = 1;
1031
1032         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1033                 /*
1034                  * faster to handle last block with cpu or
1035                  * use cpu when dma is not present.
1036                  */
1037                 use_dma = 0;
1038
1039         if (use_dma)
1040                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1041         else
1042                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1043
1044         ctx->bufcnt = 0;
1045
1046         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1047
1048         return err;
1049 }
1050
1051 static int omap_sham_finish_hmac(struct ahash_request *req)
1052 {
1053         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1054         struct omap_sham_hmac_ctx *bctx = tctx->base;
1055         int bs = crypto_shash_blocksize(bctx->shash);
1056         int ds = crypto_shash_digestsize(bctx->shash);
1057         SHASH_DESC_ON_STACK(shash, bctx->shash);
1058
1059         shash->tfm = bctx->shash;
1060         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1061
1062         return crypto_shash_init(shash) ?:
1063                crypto_shash_update(shash, bctx->opad, bs) ?:
1064                crypto_shash_finup(shash, req->result, ds, req->result);
1065 }
1066
1067 static int omap_sham_finish(struct ahash_request *req)
1068 {
1069         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1070         struct omap_sham_dev *dd = ctx->dd;
1071         int err = 0;
1072
1073         if (ctx->digcnt) {
1074                 omap_sham_copy_ready_hash(req);
1075                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1076                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1077                         err = omap_sham_finish_hmac(req);
1078         }
1079
1080         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1081
1082         return err;
1083 }
1084
1085 static void omap_sham_finish_req(struct ahash_request *req, int err)
1086 {
1087         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1088         struct omap_sham_dev *dd = ctx->dd;
1089
1090         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1091                 free_pages((unsigned long)sg_virt(ctx->sg),
1092                            get_order(ctx->sg->length));
1093
1094         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1095                 kfree(ctx->sg);
1096
1097         ctx->sg = NULL;
1098
1099         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1100
1101         if (!err) {
1102                 dd->pdata->copy_hash(req, 1);
1103                 if (test_bit(FLAGS_FINAL, &dd->flags))
1104                         err = omap_sham_finish(req);
1105         } else {
1106                 ctx->flags |= BIT(FLAGS_ERROR);
1107         }
1108
1109         /* atomic operation is not needed here */
1110         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1111                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1112
1113         pm_runtime_mark_last_busy(dd->dev);
1114         pm_runtime_put_autosuspend(dd->dev);
1115
1116         if (req->base.complete)
1117                 req->base.complete(&req->base, err);
1118 }
1119
1120 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1121                                   struct ahash_request *req)
1122 {
1123         struct crypto_async_request *async_req, *backlog;
1124         struct omap_sham_reqctx *ctx;
1125         unsigned long flags;
1126         int err = 0, ret = 0;
1127
1128 retry:
1129         spin_lock_irqsave(&dd->lock, flags);
1130         if (req)
1131                 ret = ahash_enqueue_request(&dd->queue, req);
1132         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1133                 spin_unlock_irqrestore(&dd->lock, flags);
1134                 return ret;
1135         }
1136         backlog = crypto_get_backlog(&dd->queue);
1137         async_req = crypto_dequeue_request(&dd->queue);
1138         if (async_req)
1139                 set_bit(FLAGS_BUSY, &dd->flags);
1140         spin_unlock_irqrestore(&dd->lock, flags);
1141
1142         if (!async_req)
1143                 return ret;
1144
1145         if (backlog)
1146                 backlog->complete(backlog, -EINPROGRESS);
1147
1148         req = ahash_request_cast(async_req);
1149         dd->req = req;
1150         ctx = ahash_request_ctx(req);
1151
1152         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1153         if (err || !ctx->total)
1154                 goto err1;
1155
1156         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1157                                                 ctx->op, req->nbytes);
1158
1159         err = omap_sham_hw_init(dd);
1160         if (err)
1161                 goto err1;
1162
1163         if (ctx->digcnt)
1164                 /* request has changed - restore hash */
1165                 dd->pdata->copy_hash(req, 0);
1166
1167         if (ctx->op == OP_UPDATE) {
1168                 err = omap_sham_update_req(dd);
1169                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1170                         /* no final() after finup() */
1171                         err = omap_sham_final_req(dd);
1172         } else if (ctx->op == OP_FINAL) {
1173                 err = omap_sham_final_req(dd);
1174         }
1175 err1:
1176         dev_dbg(dd->dev, "exit, err: %d\n", err);
1177
1178         if (err != -EINPROGRESS) {
1179                 /* done_task will not finish it, so do it here */
1180                 omap_sham_finish_req(req, err);
1181                 req = NULL;
1182
1183                 /*
1184                  * Execute next request immediately if there is anything
1185                  * in queue.
1186                  */
1187                 goto retry;
1188         }
1189
1190         return ret;
1191 }
1192
1193 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1194 {
1195         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1196         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1197         struct omap_sham_dev *dd = tctx->dd;
1198
1199         ctx->op = op;
1200
1201         return omap_sham_handle_queue(dd, req);
1202 }
1203
1204 static int omap_sham_update(struct ahash_request *req)
1205 {
1206         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1207         struct omap_sham_dev *dd = ctx->dd;
1208
1209         if (!req->nbytes)
1210                 return 0;
1211
1212         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1213                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1214                                          0, req->nbytes, 0);
1215                 ctx->bufcnt += req->nbytes;
1216                 return 0;
1217         }
1218
1219         if (dd->polling_mode)
1220                 ctx->flags |= BIT(FLAGS_CPU);
1221
1222         return omap_sham_enqueue(req, OP_UPDATE);
1223 }
1224
1225 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1226                                   const u8 *data, unsigned int len, u8 *out)
1227 {
1228         SHASH_DESC_ON_STACK(shash, tfm);
1229
1230         shash->tfm = tfm;
1231         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1232
1233         return crypto_shash_digest(shash, data, len, out);
1234 }
1235
1236 static int omap_sham_final_shash(struct ahash_request *req)
1237 {
1238         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1239         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1240         int offset = 0;
1241
1242         /*
1243          * If we are running HMAC on limited hardware support, skip
1244          * the ipad in the beginning of the buffer if we are going for
1245          * software fallback algorithm.
1246          */
1247         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1248             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1249                 offset = get_block_size(ctx);
1250
1251         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1252                                       ctx->buffer + offset,
1253                                       ctx->bufcnt - offset, req->result);
1254 }
1255
1256 static int omap_sham_final(struct ahash_request *req)
1257 {
1258         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1259
1260         ctx->flags |= BIT(FLAGS_FINUP);
1261
1262         if (ctx->flags & BIT(FLAGS_ERROR))
1263                 return 0; /* uncompleted hash is not needed */
1264
1265         /*
1266          * OMAP HW accel works only with buffers >= 9.
1267          * HMAC is always >= 9 because ipad == block size.
1268          * If buffersize is less than DMA_THRESHOLD, we use fallback
1269          * SW encoding, as using DMA + HW in this case doesn't provide
1270          * any benefit.
1271          */
1272         if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1273                 return omap_sham_final_shash(req);
1274         else if (ctx->bufcnt)
1275                 return omap_sham_enqueue(req, OP_FINAL);
1276
1277         /* copy ready hash (+ finalize hmac) */
1278         return omap_sham_finish(req);
1279 }
1280
1281 static int omap_sham_finup(struct ahash_request *req)
1282 {
1283         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1284         int err1, err2;
1285
1286         ctx->flags |= BIT(FLAGS_FINUP);
1287
1288         err1 = omap_sham_update(req);
1289         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1290                 return err1;
1291         /*
1292          * final() has to be always called to cleanup resources
1293          * even if udpate() failed, except EINPROGRESS
1294          */
1295         err2 = omap_sham_final(req);
1296
1297         return err1 ?: err2;
1298 }
1299
1300 static int omap_sham_digest(struct ahash_request *req)
1301 {
1302         return omap_sham_init(req) ?: omap_sham_finup(req);
1303 }
1304
1305 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1306                       unsigned int keylen)
1307 {
1308         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1309         struct omap_sham_hmac_ctx *bctx = tctx->base;
1310         int bs = crypto_shash_blocksize(bctx->shash);
1311         int ds = crypto_shash_digestsize(bctx->shash);
1312         struct omap_sham_dev *dd = NULL, *tmp;
1313         int err, i;
1314
1315         spin_lock_bh(&sham.lock);
1316         if (!tctx->dd) {
1317                 list_for_each_entry(tmp, &sham.dev_list, list) {
1318                         dd = tmp;
1319                         break;
1320                 }
1321                 tctx->dd = dd;
1322         } else {
1323                 dd = tctx->dd;
1324         }
1325         spin_unlock_bh(&sham.lock);
1326
1327         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1328         if (err)
1329                 return err;
1330
1331         if (keylen > bs) {
1332                 err = omap_sham_shash_digest(bctx->shash,
1333                                 crypto_shash_get_flags(bctx->shash),
1334                                 key, keylen, bctx->ipad);
1335                 if (err)
1336                         return err;
1337                 keylen = ds;
1338         } else {
1339                 memcpy(bctx->ipad, key, keylen);
1340         }
1341
1342         memset(bctx->ipad + keylen, 0, bs - keylen);
1343
1344         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1345                 memcpy(bctx->opad, bctx->ipad, bs);
1346
1347                 for (i = 0; i < bs; i++) {
1348                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1349                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1350                 }
1351         }
1352
1353         return err;
1354 }
1355
1356 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1357 {
1358         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1359         const char *alg_name = crypto_tfm_alg_name(tfm);
1360
1361         /* Allocate a fallback and abort if it failed. */
1362         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1363                                             CRYPTO_ALG_NEED_FALLBACK);
1364         if (IS_ERR(tctx->fallback)) {
1365                 pr_err("omap-sham: fallback driver '%s' "
1366                                 "could not be loaded.\n", alg_name);
1367                 return PTR_ERR(tctx->fallback);
1368         }
1369
1370         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1371                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1372
1373         if (alg_base) {
1374                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1375                 tctx->flags |= BIT(FLAGS_HMAC);
1376                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1377                                                 CRYPTO_ALG_NEED_FALLBACK);
1378                 if (IS_ERR(bctx->shash)) {
1379                         pr_err("omap-sham: base driver '%s' "
1380                                         "could not be loaded.\n", alg_base);
1381                         crypto_free_shash(tctx->fallback);
1382                         return PTR_ERR(bctx->shash);
1383                 }
1384
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1391 {
1392         return omap_sham_cra_init_alg(tfm, NULL);
1393 }
1394
1395 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1396 {
1397         return omap_sham_cra_init_alg(tfm, "sha1");
1398 }
1399
1400 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1401 {
1402         return omap_sham_cra_init_alg(tfm, "sha224");
1403 }
1404
1405 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1406 {
1407         return omap_sham_cra_init_alg(tfm, "sha256");
1408 }
1409
1410 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1411 {
1412         return omap_sham_cra_init_alg(tfm, "md5");
1413 }
1414
1415 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1416 {
1417         return omap_sham_cra_init_alg(tfm, "sha384");
1418 }
1419
1420 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1421 {
1422         return omap_sham_cra_init_alg(tfm, "sha512");
1423 }
1424
1425 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1426 {
1427         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1428
1429         crypto_free_shash(tctx->fallback);
1430         tctx->fallback = NULL;
1431
1432         if (tctx->flags & BIT(FLAGS_HMAC)) {
1433                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1434                 crypto_free_shash(bctx->shash);
1435         }
1436 }
1437
1438 static int omap_sham_export(struct ahash_request *req, void *out)
1439 {
1440         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1441
1442         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1443
1444         return 0;
1445 }
1446
1447 static int omap_sham_import(struct ahash_request *req, const void *in)
1448 {
1449         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1450         const struct omap_sham_reqctx *ctx_in = in;
1451
1452         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1453
1454         return 0;
1455 }
1456
1457 static struct ahash_alg algs_sha1_md5[] = {
1458 {
1459         .init           = omap_sham_init,
1460         .update         = omap_sham_update,
1461         .final          = omap_sham_final,
1462         .finup          = omap_sham_finup,
1463         .digest         = omap_sham_digest,
1464         .halg.digestsize        = SHA1_DIGEST_SIZE,
1465         .halg.base      = {
1466                 .cra_name               = "sha1",
1467                 .cra_driver_name        = "omap-sha1",
1468                 .cra_priority           = 400,
1469                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1470                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1471                                                 CRYPTO_ALG_ASYNC |
1472                                                 CRYPTO_ALG_NEED_FALLBACK,
1473                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1474                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1475                 .cra_alignmask          = OMAP_ALIGN_MASK,
1476                 .cra_module             = THIS_MODULE,
1477                 .cra_init               = omap_sham_cra_init,
1478                 .cra_exit               = omap_sham_cra_exit,
1479         }
1480 },
1481 {
1482         .init           = omap_sham_init,
1483         .update         = omap_sham_update,
1484         .final          = omap_sham_final,
1485         .finup          = omap_sham_finup,
1486         .digest         = omap_sham_digest,
1487         .halg.digestsize        = MD5_DIGEST_SIZE,
1488         .halg.base      = {
1489                 .cra_name               = "md5",
1490                 .cra_driver_name        = "omap-md5",
1491                 .cra_priority           = 400,
1492                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1493                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1494                                                 CRYPTO_ALG_ASYNC |
1495                                                 CRYPTO_ALG_NEED_FALLBACK,
1496                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1497                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1498                 .cra_alignmask          = OMAP_ALIGN_MASK,
1499                 .cra_module             = THIS_MODULE,
1500                 .cra_init               = omap_sham_cra_init,
1501                 .cra_exit               = omap_sham_cra_exit,
1502         }
1503 },
1504 {
1505         .init           = omap_sham_init,
1506         .update         = omap_sham_update,
1507         .final          = omap_sham_final,
1508         .finup          = omap_sham_finup,
1509         .digest         = omap_sham_digest,
1510         .setkey         = omap_sham_setkey,
1511         .halg.digestsize        = SHA1_DIGEST_SIZE,
1512         .halg.base      = {
1513                 .cra_name               = "hmac(sha1)",
1514                 .cra_driver_name        = "omap-hmac-sha1",
1515                 .cra_priority           = 400,
1516                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1517                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1518                                                 CRYPTO_ALG_ASYNC |
1519                                                 CRYPTO_ALG_NEED_FALLBACK,
1520                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1521                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1522                                         sizeof(struct omap_sham_hmac_ctx),
1523                 .cra_alignmask          = OMAP_ALIGN_MASK,
1524                 .cra_module             = THIS_MODULE,
1525                 .cra_init               = omap_sham_cra_sha1_init,
1526                 .cra_exit               = omap_sham_cra_exit,
1527         }
1528 },
1529 {
1530         .init           = omap_sham_init,
1531         .update         = omap_sham_update,
1532         .final          = omap_sham_final,
1533         .finup          = omap_sham_finup,
1534         .digest         = omap_sham_digest,
1535         .setkey         = omap_sham_setkey,
1536         .halg.digestsize        = MD5_DIGEST_SIZE,
1537         .halg.base      = {
1538                 .cra_name               = "hmac(md5)",
1539                 .cra_driver_name        = "omap-hmac-md5",
1540                 .cra_priority           = 400,
1541                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1542                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1543                                                 CRYPTO_ALG_ASYNC |
1544                                                 CRYPTO_ALG_NEED_FALLBACK,
1545                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1546                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1547                                         sizeof(struct omap_sham_hmac_ctx),
1548                 .cra_alignmask          = OMAP_ALIGN_MASK,
1549                 .cra_module             = THIS_MODULE,
1550                 .cra_init               = omap_sham_cra_md5_init,
1551                 .cra_exit               = omap_sham_cra_exit,
1552         }
1553 }
1554 };
1555
1556 /* OMAP4 has some algs in addition to what OMAP2 has */
1557 static struct ahash_alg algs_sha224_sha256[] = {
1558 {
1559         .init           = omap_sham_init,
1560         .update         = omap_sham_update,
1561         .final          = omap_sham_final,
1562         .finup          = omap_sham_finup,
1563         .digest         = omap_sham_digest,
1564         .halg.digestsize        = SHA224_DIGEST_SIZE,
1565         .halg.base      = {
1566                 .cra_name               = "sha224",
1567                 .cra_driver_name        = "omap-sha224",
1568                 .cra_priority           = 400,
1569                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1570                                                 CRYPTO_ALG_ASYNC |
1571                                                 CRYPTO_ALG_NEED_FALLBACK,
1572                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1573                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1574                 .cra_alignmask          = OMAP_ALIGN_MASK,
1575                 .cra_module             = THIS_MODULE,
1576                 .cra_init               = omap_sham_cra_init,
1577                 .cra_exit               = omap_sham_cra_exit,
1578         }
1579 },
1580 {
1581         .init           = omap_sham_init,
1582         .update         = omap_sham_update,
1583         .final          = omap_sham_final,
1584         .finup          = omap_sham_finup,
1585         .digest         = omap_sham_digest,
1586         .halg.digestsize        = SHA256_DIGEST_SIZE,
1587         .halg.base      = {
1588                 .cra_name               = "sha256",
1589                 .cra_driver_name        = "omap-sha256",
1590                 .cra_priority           = 400,
1591                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1592                                                 CRYPTO_ALG_ASYNC |
1593                                                 CRYPTO_ALG_NEED_FALLBACK,
1594                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1595                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1596                 .cra_alignmask          = OMAP_ALIGN_MASK,
1597                 .cra_module             = THIS_MODULE,
1598                 .cra_init               = omap_sham_cra_init,
1599                 .cra_exit               = omap_sham_cra_exit,
1600         }
1601 },
1602 {
1603         .init           = omap_sham_init,
1604         .update         = omap_sham_update,
1605         .final          = omap_sham_final,
1606         .finup          = omap_sham_finup,
1607         .digest         = omap_sham_digest,
1608         .setkey         = omap_sham_setkey,
1609         .halg.digestsize        = SHA224_DIGEST_SIZE,
1610         .halg.base      = {
1611                 .cra_name               = "hmac(sha224)",
1612                 .cra_driver_name        = "omap-hmac-sha224",
1613                 .cra_priority           = 400,
1614                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1615                                                 CRYPTO_ALG_ASYNC |
1616                                                 CRYPTO_ALG_NEED_FALLBACK,
1617                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1618                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1619                                         sizeof(struct omap_sham_hmac_ctx),
1620                 .cra_alignmask          = OMAP_ALIGN_MASK,
1621                 .cra_module             = THIS_MODULE,
1622                 .cra_init               = omap_sham_cra_sha224_init,
1623                 .cra_exit               = omap_sham_cra_exit,
1624         }
1625 },
1626 {
1627         .init           = omap_sham_init,
1628         .update         = omap_sham_update,
1629         .final          = omap_sham_final,
1630         .finup          = omap_sham_finup,
1631         .digest         = omap_sham_digest,
1632         .setkey         = omap_sham_setkey,
1633         .halg.digestsize        = SHA256_DIGEST_SIZE,
1634         .halg.base      = {
1635                 .cra_name               = "hmac(sha256)",
1636                 .cra_driver_name        = "omap-hmac-sha256",
1637                 .cra_priority           = 400,
1638                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1639                                                 CRYPTO_ALG_ASYNC |
1640                                                 CRYPTO_ALG_NEED_FALLBACK,
1641                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1642                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1643                                         sizeof(struct omap_sham_hmac_ctx),
1644                 .cra_alignmask          = OMAP_ALIGN_MASK,
1645                 .cra_module             = THIS_MODULE,
1646                 .cra_init               = omap_sham_cra_sha256_init,
1647                 .cra_exit               = omap_sham_cra_exit,
1648         }
1649 },
1650 };
1651
1652 static struct ahash_alg algs_sha384_sha512[] = {
1653 {
1654         .init           = omap_sham_init,
1655         .update         = omap_sham_update,
1656         .final          = omap_sham_final,
1657         .finup          = omap_sham_finup,
1658         .digest         = omap_sham_digest,
1659         .halg.digestsize        = SHA384_DIGEST_SIZE,
1660         .halg.base      = {
1661                 .cra_name               = "sha384",
1662                 .cra_driver_name        = "omap-sha384",
1663                 .cra_priority           = 400,
1664                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1665                                                 CRYPTO_ALG_ASYNC |
1666                                                 CRYPTO_ALG_NEED_FALLBACK,
1667                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1668                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1669                 .cra_alignmask          = OMAP_ALIGN_MASK,
1670                 .cra_module             = THIS_MODULE,
1671                 .cra_init               = omap_sham_cra_init,
1672                 .cra_exit               = omap_sham_cra_exit,
1673         }
1674 },
1675 {
1676         .init           = omap_sham_init,
1677         .update         = omap_sham_update,
1678         .final          = omap_sham_final,
1679         .finup          = omap_sham_finup,
1680         .digest         = omap_sham_digest,
1681         .halg.digestsize        = SHA512_DIGEST_SIZE,
1682         .halg.base      = {
1683                 .cra_name               = "sha512",
1684                 .cra_driver_name        = "omap-sha512",
1685                 .cra_priority           = 400,
1686                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1687                                                 CRYPTO_ALG_ASYNC |
1688                                                 CRYPTO_ALG_NEED_FALLBACK,
1689                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1690                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1691                 .cra_alignmask          = OMAP_ALIGN_MASK,
1692                 .cra_module             = THIS_MODULE,
1693                 .cra_init               = omap_sham_cra_init,
1694                 .cra_exit               = omap_sham_cra_exit,
1695         }
1696 },
1697 {
1698         .init           = omap_sham_init,
1699         .update         = omap_sham_update,
1700         .final          = omap_sham_final,
1701         .finup          = omap_sham_finup,
1702         .digest         = omap_sham_digest,
1703         .setkey         = omap_sham_setkey,
1704         .halg.digestsize        = SHA384_DIGEST_SIZE,
1705         .halg.base      = {
1706                 .cra_name               = "hmac(sha384)",
1707                 .cra_driver_name        = "omap-hmac-sha384",
1708                 .cra_priority           = 400,
1709                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1710                                                 CRYPTO_ALG_ASYNC |
1711                                                 CRYPTO_ALG_NEED_FALLBACK,
1712                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1713                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1714                                         sizeof(struct omap_sham_hmac_ctx),
1715                 .cra_alignmask          = OMAP_ALIGN_MASK,
1716                 .cra_module             = THIS_MODULE,
1717                 .cra_init               = omap_sham_cra_sha384_init,
1718                 .cra_exit               = omap_sham_cra_exit,
1719         }
1720 },
1721 {
1722         .init           = omap_sham_init,
1723         .update         = omap_sham_update,
1724         .final          = omap_sham_final,
1725         .finup          = omap_sham_finup,
1726         .digest         = omap_sham_digest,
1727         .setkey         = omap_sham_setkey,
1728         .halg.digestsize        = SHA512_DIGEST_SIZE,
1729         .halg.base      = {
1730                 .cra_name               = "hmac(sha512)",
1731                 .cra_driver_name        = "omap-hmac-sha512",
1732                 .cra_priority           = 400,
1733                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1734                                                 CRYPTO_ALG_ASYNC |
1735                                                 CRYPTO_ALG_NEED_FALLBACK,
1736                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1737                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1738                                         sizeof(struct omap_sham_hmac_ctx),
1739                 .cra_alignmask          = OMAP_ALIGN_MASK,
1740                 .cra_module             = THIS_MODULE,
1741                 .cra_init               = omap_sham_cra_sha512_init,
1742                 .cra_exit               = omap_sham_cra_exit,
1743         }
1744 },
1745 };
1746
1747 static void omap_sham_done_task(unsigned long data)
1748 {
1749         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1750         int err = 0;
1751
1752         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1753                 omap_sham_handle_queue(dd, NULL);
1754                 return;
1755         }
1756
1757         if (test_bit(FLAGS_CPU, &dd->flags)) {
1758                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1759                         goto finish;
1760         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1761                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1762                         omap_sham_update_dma_stop(dd);
1763                         if (dd->err) {
1764                                 err = dd->err;
1765                                 goto finish;
1766                         }
1767                 }
1768                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1769                         /* hash or semi-hash ready */
1770                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1771                                 goto finish;
1772                 }
1773         }
1774
1775         return;
1776
1777 finish:
1778         dev_dbg(dd->dev, "update done: err: %d\n", err);
1779         /* finish curent request */
1780         omap_sham_finish_req(dd->req, err);
1781
1782         /* If we are not busy, process next req */
1783         if (!test_bit(FLAGS_BUSY, &dd->flags))
1784                 omap_sham_handle_queue(dd, NULL);
1785 }
1786
1787 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1788 {
1789         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1790                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1791         } else {
1792                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1793                 tasklet_schedule(&dd->done_task);
1794         }
1795
1796         return IRQ_HANDLED;
1797 }
1798
1799 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1800 {
1801         struct omap_sham_dev *dd = dev_id;
1802
1803         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1804                 /* final -> allow device to go to power-saving mode */
1805                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1806
1807         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1808                                  SHA_REG_CTRL_OUTPUT_READY);
1809         omap_sham_read(dd, SHA_REG_CTRL);
1810
1811         return omap_sham_irq_common(dd);
1812 }
1813
1814 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1815 {
1816         struct omap_sham_dev *dd = dev_id;
1817
1818         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1819
1820         return omap_sham_irq_common(dd);
1821 }
1822
1823 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1824         {
1825                 .algs_list      = algs_sha1_md5,
1826                 .size           = ARRAY_SIZE(algs_sha1_md5),
1827         },
1828 };
1829
1830 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1831         .algs_info      = omap_sham_algs_info_omap2,
1832         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1833         .flags          = BIT(FLAGS_BE32_SHA1),
1834         .digest_size    = SHA1_DIGEST_SIZE,
1835         .copy_hash      = omap_sham_copy_hash_omap2,
1836         .write_ctrl     = omap_sham_write_ctrl_omap2,
1837         .trigger        = omap_sham_trigger_omap2,
1838         .poll_irq       = omap_sham_poll_irq_omap2,
1839         .intr_hdlr      = omap_sham_irq_omap2,
1840         .idigest_ofs    = 0x00,
1841         .din_ofs        = 0x1c,
1842         .digcnt_ofs     = 0x14,
1843         .rev_ofs        = 0x5c,
1844         .mask_ofs       = 0x60,
1845         .sysstatus_ofs  = 0x64,
1846         .major_mask     = 0xf0,
1847         .major_shift    = 4,
1848         .minor_mask     = 0x0f,
1849         .minor_shift    = 0,
1850 };
1851
1852 #ifdef CONFIG_OF
1853 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1854         {
1855                 .algs_list      = algs_sha1_md5,
1856                 .size           = ARRAY_SIZE(algs_sha1_md5),
1857         },
1858         {
1859                 .algs_list      = algs_sha224_sha256,
1860                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1861         },
1862 };
1863
1864 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1865         .algs_info      = omap_sham_algs_info_omap4,
1866         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1867         .flags          = BIT(FLAGS_AUTO_XOR),
1868         .digest_size    = SHA256_DIGEST_SIZE,
1869         .copy_hash      = omap_sham_copy_hash_omap4,
1870         .write_ctrl     = omap_sham_write_ctrl_omap4,
1871         .trigger        = omap_sham_trigger_omap4,
1872         .poll_irq       = omap_sham_poll_irq_omap4,
1873         .intr_hdlr      = omap_sham_irq_omap4,
1874         .idigest_ofs    = 0x020,
1875         .odigest_ofs    = 0x0,
1876         .din_ofs        = 0x080,
1877         .digcnt_ofs     = 0x040,
1878         .rev_ofs        = 0x100,
1879         .mask_ofs       = 0x110,
1880         .sysstatus_ofs  = 0x114,
1881         .mode_ofs       = 0x44,
1882         .length_ofs     = 0x48,
1883         .major_mask     = 0x0700,
1884         .major_shift    = 8,
1885         .minor_mask     = 0x003f,
1886         .minor_shift    = 0,
1887 };
1888
1889 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1890         {
1891                 .algs_list      = algs_sha1_md5,
1892                 .size           = ARRAY_SIZE(algs_sha1_md5),
1893         },
1894         {
1895                 .algs_list      = algs_sha224_sha256,
1896                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1897         },
1898         {
1899                 .algs_list      = algs_sha384_sha512,
1900                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1901         },
1902 };
1903
1904 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1905         .algs_info      = omap_sham_algs_info_omap5,
1906         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1907         .flags          = BIT(FLAGS_AUTO_XOR),
1908         .digest_size    = SHA512_DIGEST_SIZE,
1909         .copy_hash      = omap_sham_copy_hash_omap4,
1910         .write_ctrl     = omap_sham_write_ctrl_omap4,
1911         .trigger        = omap_sham_trigger_omap4,
1912         .poll_irq       = omap_sham_poll_irq_omap4,
1913         .intr_hdlr      = omap_sham_irq_omap4,
1914         .idigest_ofs    = 0x240,
1915         .odigest_ofs    = 0x200,
1916         .din_ofs        = 0x080,
1917         .digcnt_ofs     = 0x280,
1918         .rev_ofs        = 0x100,
1919         .mask_ofs       = 0x110,
1920         .sysstatus_ofs  = 0x114,
1921         .mode_ofs       = 0x284,
1922         .length_ofs     = 0x288,
1923         .major_mask     = 0x0700,
1924         .major_shift    = 8,
1925         .minor_mask     = 0x003f,
1926         .minor_shift    = 0,
1927 };
1928
1929 static const struct of_device_id omap_sham_of_match[] = {
1930         {
1931                 .compatible     = "ti,omap2-sham",
1932                 .data           = &omap_sham_pdata_omap2,
1933         },
1934         {
1935                 .compatible     = "ti,omap3-sham",
1936                 .data           = &omap_sham_pdata_omap2,
1937         },
1938         {
1939                 .compatible     = "ti,omap4-sham",
1940                 .data           = &omap_sham_pdata_omap4,
1941         },
1942         {
1943                 .compatible     = "ti,omap5-sham",
1944                 .data           = &omap_sham_pdata_omap5,
1945         },
1946         {},
1947 };
1948 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1949
1950 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1951                 struct device *dev, struct resource *res)
1952 {
1953         struct device_node *node = dev->of_node;
1954         int err = 0;
1955
1956         dd->pdata = of_device_get_match_data(dev);
1957         if (!dd->pdata) {
1958                 dev_err(dev, "no compatible OF match\n");
1959                 err = -EINVAL;
1960                 goto err;
1961         }
1962
1963         err = of_address_to_resource(node, 0, res);
1964         if (err < 0) {
1965                 dev_err(dev, "can't translate OF node address\n");
1966                 err = -EINVAL;
1967                 goto err;
1968         }
1969
1970         dd->irq = irq_of_parse_and_map(node, 0);
1971         if (!dd->irq) {
1972                 dev_err(dev, "can't translate OF irq value\n");
1973                 err = -EINVAL;
1974                 goto err;
1975         }
1976
1977 err:
1978         return err;
1979 }
1980 #else
1981 static const struct of_device_id omap_sham_of_match[] = {
1982         {},
1983 };
1984
1985 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1986                 struct device *dev, struct resource *res)
1987 {
1988         return -EINVAL;
1989 }
1990 #endif
1991
1992 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1993                 struct platform_device *pdev, struct resource *res)
1994 {
1995         struct device *dev = &pdev->dev;
1996         struct resource *r;
1997         int err = 0;
1998
1999         /* Get the base address */
2000         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2001         if (!r) {
2002                 dev_err(dev, "no MEM resource info\n");
2003                 err = -ENODEV;
2004                 goto err;
2005         }
2006         memcpy(res, r, sizeof(*res));
2007
2008         /* Get the IRQ */
2009         dd->irq = platform_get_irq(pdev, 0);
2010         if (dd->irq < 0) {
2011                 dev_err(dev, "no IRQ resource info\n");
2012                 err = dd->irq;
2013                 goto err;
2014         }
2015
2016         /* Only OMAP2/3 can be non-DT */
2017         dd->pdata = &omap_sham_pdata_omap2;
2018
2019 err:
2020         return err;
2021 }
2022
2023 static int omap_sham_probe(struct platform_device *pdev)
2024 {
2025         struct omap_sham_dev *dd;
2026         struct device *dev = &pdev->dev;
2027         struct resource res;
2028         dma_cap_mask_t mask;
2029         int err, i, j;
2030         u32 rev;
2031
2032         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2033         if (dd == NULL) {
2034                 dev_err(dev, "unable to alloc data struct.\n");
2035                 err = -ENOMEM;
2036                 goto data_err;
2037         }
2038         dd->dev = dev;
2039         platform_set_drvdata(pdev, dd);
2040
2041         INIT_LIST_HEAD(&dd->list);
2042         spin_lock_init(&dd->lock);
2043         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2044         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2045
2046         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2047                                omap_sham_get_res_pdev(dd, pdev, &res);
2048         if (err)
2049                 goto data_err;
2050
2051         dd->io_base = devm_ioremap_resource(dev, &res);
2052         if (IS_ERR(dd->io_base)) {
2053                 err = PTR_ERR(dd->io_base);
2054                 goto data_err;
2055         }
2056         dd->phys_base = res.start;
2057
2058         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2059                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2060         if (err) {
2061                 dev_err(dev, "unable to request irq %d, err = %d\n",
2062                         dd->irq, err);
2063                 goto data_err;
2064         }
2065
2066         dma_cap_zero(mask);
2067         dma_cap_set(DMA_SLAVE, mask);
2068
2069         dd->dma_lch = dma_request_chan(dev, "rx");
2070         if (IS_ERR(dd->dma_lch)) {
2071                 err = PTR_ERR(dd->dma_lch);
2072                 if (err == -EPROBE_DEFER)
2073                         goto data_err;
2074
2075                 dd->polling_mode = 1;
2076                 dev_dbg(dev, "using polling mode instead of dma\n");
2077         }
2078
2079         dd->flags |= dd->pdata->flags;
2080
2081         pm_runtime_use_autosuspend(dev);
2082         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2083
2084         pm_runtime_enable(dev);
2085         pm_runtime_irq_safe(dev);
2086
2087         err = pm_runtime_get_sync(dev);
2088         if (err < 0) {
2089                 dev_err(dev, "failed to get sync: %d\n", err);
2090                 goto err_pm;
2091         }
2092
2093         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2094         pm_runtime_put_sync(&pdev->dev);
2095
2096         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2097                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2098                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2099
2100         spin_lock(&sham.lock);
2101         list_add_tail(&dd->list, &sham.dev_list);
2102         spin_unlock(&sham.lock);
2103
2104         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2105                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2106                         struct ahash_alg *alg;
2107
2108                         alg = &dd->pdata->algs_info[i].algs_list[j];
2109                         alg->export = omap_sham_export;
2110                         alg->import = omap_sham_import;
2111                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2112                                               BUFLEN;
2113                         err = crypto_register_ahash(alg);
2114                         if (err)
2115                                 goto err_algs;
2116
2117                         dd->pdata->algs_info[i].registered++;
2118                 }
2119         }
2120
2121         return 0;
2122
2123 err_algs:
2124         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2125                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2126                         crypto_unregister_ahash(
2127                                         &dd->pdata->algs_info[i].algs_list[j]);
2128 err_pm:
2129         pm_runtime_disable(dev);
2130         if (!dd->polling_mode)
2131                 dma_release_channel(dd->dma_lch);
2132 data_err:
2133         dev_err(dev, "initialization failed.\n");
2134
2135         return err;
2136 }
2137
2138 static int omap_sham_remove(struct platform_device *pdev)
2139 {
2140         struct omap_sham_dev *dd;
2141         int i, j;
2142
2143         dd = platform_get_drvdata(pdev);
2144         if (!dd)
2145                 return -ENODEV;
2146         spin_lock(&sham.lock);
2147         list_del(&dd->list);
2148         spin_unlock(&sham.lock);
2149         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2150                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2151                         crypto_unregister_ahash(
2152                                         &dd->pdata->algs_info[i].algs_list[j]);
2153         tasklet_kill(&dd->done_task);
2154         pm_runtime_disable(&pdev->dev);
2155
2156         if (!dd->polling_mode)
2157                 dma_release_channel(dd->dma_lch);
2158
2159         return 0;
2160 }
2161
2162 #ifdef CONFIG_PM_SLEEP
2163 static int omap_sham_suspend(struct device *dev)
2164 {
2165         pm_runtime_put_sync(dev);
2166         return 0;
2167 }
2168
2169 static int omap_sham_resume(struct device *dev)
2170 {
2171         int err = pm_runtime_get_sync(dev);
2172         if (err < 0) {
2173                 dev_err(dev, "failed to get sync: %d\n", err);
2174                 return err;
2175         }
2176         return 0;
2177 }
2178 #endif
2179
2180 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2181
2182 static struct platform_driver omap_sham_driver = {
2183         .probe  = omap_sham_probe,
2184         .remove = omap_sham_remove,
2185         .driver = {
2186                 .name   = "omap-sham",
2187                 .pm     = &omap_sham_pm_ops,
2188                 .of_match_table = omap_sham_of_match,
2189         },
2190 };
2191
2192 module_platform_driver(omap_sham_driver);
2193
2194 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2195 MODULE_LICENSE("GPL v2");
2196 MODULE_AUTHOR("Dmitry Kasatkin");
2197 MODULE_ALIAS("platform:omap-sham");