drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         struct omap_sham_dev    *dd;
 172
 173         unsigned long           flags;
 174
 175         /* fallback stuff */
 176         struct crypto_shash     *fallback;
 177
 178         struct omap_sham_hmac_ctx base[0];
 179 };
 180
 181 #define OMAP_SHAM_QUEUE_LENGTH  10
 182
 183 struct omap_sham_algs_info {
 184         struct ahash_alg        *algs_list;
 185         unsigned int            size;
 186         unsigned int            registered;
 187 };
 188
 189 struct omap_sham_pdata {
 190         struct omap_sham_algs_info      *algs_info;
 191         unsigned int    algs_info_size;
 192         unsigned long   flags;
 193         int             digest_size;
 194
 195         void            (*copy_hash)(struct ahash_request *req, int out);
 196         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 197                                       int final, int dma);
 198         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 199         int             (*poll_irq)(struct omap_sham_dev *dd);
 200         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 201
 202         u32             odigest_ofs;
 203         u32             idigest_ofs;
 204         u32             din_ofs;
 205         u32             digcnt_ofs;
 206         u32             rev_ofs;
 207         u32             mask_ofs;
 208         u32             sysstatus_ofs;
 209         u32             mode_ofs;
 210         u32             length_ofs;
 211
 212         u32             major_mask;
 213         u32             major_shift;
 214         u32             minor_mask;
 215         u32             minor_shift;
 216 };
 217
 218 struct omap_sham_dev {
 219         struct list_head        list;
 220         unsigned long           phys_base;
 221         struct device           *dev;
 222         void __iomem            *io_base;
 223         int                     irq;
 224         spinlock_t              lock;
 225         int                     err;
 226         struct dma_chan         *dma_lch;
 227         struct tasklet_struct   done_task;
 228         u8                      polling_mode;
 229         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 230
 231         unsigned long           flags;
 232         int                     fallback_sz;
 233         struct crypto_queue     queue;
 234         struct ahash_request    *req;
 235
 236         const struct omap_sham_pdata    *pdata;
 237 };
 238
 239 struct omap_sham_drv {
 240         struct list_head        dev_list;
 241         spinlock_t              lock;
 242         unsigned long           flags;
 243 };
 244
 245 static struct omap_sham_drv sham = {
 246         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 247         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 248 };
 249
 250 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 251 {
 252         return __raw_readl(dd->io_base + offset);
 253 }
 254
 255 static inline void omap_sham_write(struct omap_sham_dev *dd,
 256                                         u32 offset, u32 value)
 257 {
 258         __raw_writel(value, dd->io_base + offset);
 259 }
 260
 261 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 262                                         u32 value, u32 mask)
 263 {
 264         u32 val;
 265
 266         val = omap_sham_read(dd, address);
 267         val &= ~mask;
 268         val |= value;
 269         omap_sham_write(dd, address, val);
 270 }
 271
 272 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 273 {
 274         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 275
 276         while (!(omap_sham_read(dd, offset) & bit)) {
 277                 if (time_is_before_jiffies(timeout))
 278                         return -ETIMEDOUT;
 279         }
 280
 281         return 0;
 282 }
 283
 284 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 285 {
 286         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 287         struct omap_sham_dev *dd = ctx->dd;
 288         u32 *hash = (u32 *)ctx->digest;
 289         int i;
 290
 291         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 292                 if (out)
 293                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 294                 else
 295                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 296         }
 297 }
 298
 299 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 300 {
 301         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 302         struct omap_sham_dev *dd = ctx->dd;
 303         int i;
 304
 305         if (ctx->flags & BIT(FLAGS_HMAC)) {
 306                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 307                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 308                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 309                 u32 *opad = (u32 *)bctx->opad;
 310
 311                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 312                         if (out)
 313                                 opad[i] = omap_sham_read(dd,
 314                                                 SHA_REG_ODIGEST(dd, i));
 315                         else
 316                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 317                                                 opad[i]);
 318                 }
 319         }
 320
 321         omap_sham_copy_hash_omap2(req, out);
 322 }
 323
 324 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 325 {
 326         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 327         u32 *in = (u32 *)ctx->digest;
 328         u32 *hash = (u32 *)req->result;
 329         int i, d, big_endian = 0;
 330
 331         if (!hash)
 332                 return;
 333
 334         switch (ctx->flags & FLAGS_MODE_MASK) {
 335         case FLAGS_MODE_MD5:
 336                 d = MD5_DIGEST_SIZE / sizeof(u32);
 337                 break;
 338         case FLAGS_MODE_SHA1:
 339                 /* OMAP2 SHA1 is big endian */
 340                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 341                         big_endian = 1;
 342                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 343                 break;
 344         case FLAGS_MODE_SHA224:
 345                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 346                 break;
 347         case FLAGS_MODE_SHA256:
 348                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 349                 break;
 350         case FLAGS_MODE_SHA384:
 351                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 352                 break;
 353         case FLAGS_MODE_SHA512:
 354                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 355                 break;
 356         default:
 357                 d = 0;
 358         }
 359
 360         if (big_endian)
 361                 for (i = 0; i < d; i++)
 362                         hash[i] = be32_to_cpu(in[i]);
 363         else
 364                 for (i = 0; i < d; i++)
 365                         hash[i] = le32_to_cpu(in[i]);
 366 }
 367
 368 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 369 {
 370         int err;
 371
 372         err = pm_runtime_get_sync(dd->dev);
 373         if (err < 0) {
 374                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 375                 return err;
 376         }
 377
 378         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 379                 set_bit(FLAGS_INIT, &dd->flags);
 380                 dd->err = 0;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 387                                  int final, int dma)
 388 {
 389         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 390         u32 val = length << 5, mask;
 391
 392         if (likely(ctx->digcnt))
 393                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 394
 395         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 396                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 397                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 398         /*
 399          * Setting ALGO_CONST only for the first iteration
 400          * and CLOSE_HASH only for the last one.
 401          */
 402         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 403                 val |= SHA_REG_CTRL_ALGO;
 404         if (!ctx->digcnt)
 405                 val |= SHA_REG_CTRL_ALGO_CONST;
 406         if (final)
 407                 val |= SHA_REG_CTRL_CLOSE_HASH;
 408
 409         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 410                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 411
 412         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 413 }
 414
 415 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 416 {
 417 }
 418
 419 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 420 {
 421         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 422 }
 423
 424 static int get_block_size(struct omap_sham_reqctx *ctx)
 425 {
 426         int d;
 427
 428         switch (ctx->flags & FLAGS_MODE_MASK) {
 429         case FLAGS_MODE_MD5:
 430         case FLAGS_MODE_SHA1:
 431                 d = SHA1_BLOCK_SIZE;
 432                 break;
 433         case FLAGS_MODE_SHA224:
 434         case FLAGS_MODE_SHA256:
 435                 d = SHA256_BLOCK_SIZE;
 436                 break;
 437         case FLAGS_MODE_SHA384:
 438         case FLAGS_MODE_SHA512:
 439                 d = SHA512_BLOCK_SIZE;
 440                 break;
 441         default:
 442                 d = 0;
 443         }
 444
 445         return d;
 446 }
 447
 448 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 449                                     u32 *value, int count)
 450 {
 451         for (; count--; value++, offset += 4)
 452                 omap_sham_write(dd, offset, *value);
 453 }
 454
 455 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 456                                  int final, int dma)
 457 {
 458         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 459         u32 val, mask;
 460
 461         /*
 462          * Setting ALGO_CONST only for the first iteration and
 463          * CLOSE_HASH only for the last one. Note that flags mode bits
 464          * correspond to algorithm encoding in mode register.
 465          */
 466         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 467         if (!ctx->digcnt) {
 468                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 469                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 470                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 471                 int bs, nr_dr;
 472
 473                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 474
 475                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 476                         bs = get_block_size(ctx);
 477                         nr_dr = bs / (2 * sizeof(u32));
 478                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 479                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 480                                           (u32 *)bctx->ipad, nr_dr);
 481                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 482                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 483                         ctx->digcnt += bs;
 484                 }
 485         }
 486
 487         if (final) {
 488                 val |= SHA_REG_MODE_CLOSE_HASH;
 489
 490                 if (ctx->flags & BIT(FLAGS_HMAC))
 491                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 492         }
 493
 494         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 495                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 496                SHA_REG_MODE_HMAC_KEY_PROC;
 497
 498         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 499         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 500         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 501         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 502                              SHA_REG_MASK_IT_EN |
 503                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 504                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 505 }
 506
 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 508 {
 509         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 510 }
 511
 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 513 {
 514         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 515                               SHA_REG_IRQSTATUS_INPUT_RDY);
 516 }
 517
 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 519                               int final)
 520 {
 521         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 522         int count, len32, bs32, offset = 0;
 523         const u32 *buffer;
 524         int mlen;
 525         struct sg_mapping_iter mi;
 526
 527         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 528                                                 ctx->digcnt, length, final);
 529
 530         dd->pdata->write_ctrl(dd, length, final, 0);
 531         dd->pdata->trigger(dd, length);
 532
 533         /* should be non-zero before next lines to disable clocks later */
 534         ctx->digcnt += length;
 535         ctx->total -= length;
 536
 537         if (final)
 538                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 539
 540         set_bit(FLAGS_CPU, &dd->flags);
 541
 542         len32 = DIV_ROUND_UP(length, sizeof(u32));
 543         bs32 = get_block_size(ctx) / sizeof(u32);
 544
 545         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 546                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 547
 548         mlen = 0;
 549
 550         while (len32) {
 551                 if (dd->pdata->poll_irq(dd))
 552                         return -ETIMEDOUT;
 553
 554                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 555                         if (!mlen) {
 556                                 sg_miter_next(&mi);
 557                                 mlen = mi.length;
 558                                 if (!mlen) {
 559                                         pr_err("sg miter failure.\n");
 560                                         return -EINVAL;
 561                                 }
 562                                 offset = 0;
 563                                 buffer = mi.addr;
 564                         }
 565                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 566                                         buffer[offset]);
 567                         mlen -= 4;
 568                 }
 569                 len32 -= min(len32, bs32);
 570         }
 571
 572         sg_miter_stop(&mi);
 573
 574         return -EINPROGRESS;
 575 }
 576
 577 static void omap_sham_dma_callback(void *param)
 578 {
 579         struct omap_sham_dev *dd = param;
 580
 581         set_bit(FLAGS_DMA_READY, &dd->flags);
 582         tasklet_schedule(&dd->done_task);
 583 }
 584
 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 586                               int final)
 587 {
 588         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 589         struct dma_async_tx_descriptor *tx;
 590         struct dma_slave_config cfg;
 591         int ret;
 592
 593         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 594                                                 ctx->digcnt, length, final);
 595
 596         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 597                 dev_err(dd->dev, "dma_map_sg error\n");
 598                 return -EINVAL;
 599         }
 600
 601         memset(&cfg, 0, sizeof(cfg));
 602
 603         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 604         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 605         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 606
 607         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 608         if (ret) {
 609                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 610                 return ret;
 611         }
 612
 613         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 614                                      DMA_MEM_TO_DEV,
 615                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 616
 617         if (!tx) {
 618                 dev_err(dd->dev, "prep_slave_sg failed\n");
 619                 return -EINVAL;
 620         }
 621
 622         tx->callback = omap_sham_dma_callback;
 623         tx->callback_param = dd;
 624
 625         dd->pdata->write_ctrl(dd, length, final, 1);
 626
 627         ctx->digcnt += length;
 628         ctx->total -= length;
 629
 630         if (final)
 631                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 632
 633         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 634
 635         dmaengine_submit(tx);
 636         dma_async_issue_pending(dd->dma_lch);
 637
 638         dd->pdata->trigger(dd, length);
 639
 640         return -EINPROGRESS;
 641 }
 642
 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 644                                    struct scatterlist *sg, int bs, int new_len)
 645 {
 646         int n = sg_nents(sg);
 647         struct scatterlist *tmp;
 648         int offset = ctx->offset;
 649
 650         if (ctx->bufcnt)
 651                 n++;
 652
 653         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 654         if (!ctx->sg)
 655                 return -ENOMEM;
 656
 657         sg_init_table(ctx->sg, n);
 658
 659         tmp = ctx->sg;
 660
 661         ctx->sg_len = 0;
 662
 663         if (ctx->bufcnt) {
 664                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 665                 tmp = sg_next(tmp);
 666                 ctx->sg_len++;
 667         }
 668
 669         while (sg && new_len) {
 670                 int len = sg->length - offset;
 671
 672                 if (offset) {
 673                         offset -= sg->length;
 674                         if (offset < 0)
 675                                 offset = 0;
 676                 }
 677
 678                 if (new_len < len)
 679                         len = new_len;
 680
 681                 if (len > 0) {
 682                         new_len -= len;
 683                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 684                         if (new_len <= 0)
 685                                 sg_mark_end(tmp);
 686                         tmp = sg_next(tmp);
 687                         ctx->sg_len++;
 688                 }
 689
 690                 sg = sg_next(sg);
 691         }
 692
 693         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 694
 695         ctx->bufcnt = 0;
 696
 697         return 0;
 698 }
 699
 700 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 701                               struct scatterlist *sg, int bs, int new_len)
 702 {
 703         int pages;
 704         void *buf;
 705         int len;
 706
 707         len = new_len + ctx->bufcnt;
 708
 709         pages = get_order(ctx->total);
 710
 711         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 712         if (!buf) {
 713                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 714                 return -ENOMEM;
 715         }
 716
 717         if (ctx->bufcnt)
 718                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 719
 720         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 721                                  ctx->total - ctx->bufcnt, 0);
 722         sg_init_table(ctx->sgl, 1);
 723         sg_set_buf(ctx->sgl, buf, len);
 724         ctx->sg = ctx->sgl;
 725         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 726         ctx->sg_len = 1;
 727         ctx->bufcnt = 0;
 728         ctx->offset = 0;
 729
 730         return 0;
 731 }
 732
 733 static int omap_sham_align_sgs(struct scatterlist *sg,
 734                                int nbytes, int bs, bool final,
 735                                struct omap_sham_reqctx *rctx)
 736 {
 737         int n = 0;
 738         bool aligned = true;
 739         bool list_ok = true;
 740         struct scatterlist *sg_tmp = sg;
 741         int new_len;
 742         int offset = rctx->offset;
 743
 744         if (!sg || !sg->length || !nbytes)
 745                 return 0;
 746
 747         new_len = nbytes;
 748
 749         if (offset)
 750                 list_ok = false;
 751
 752         if (final)
 753                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 754         else
 755                 new_len = (new_len - 1) / bs * bs;
 756
 757         if (nbytes != new_len)
 758                 list_ok = false;
 759
 760         while (nbytes > 0 && sg_tmp) {
 761                 n++;
 762
 763 #ifdef CONFIG_ZONE_DMA
 764                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 765                         aligned = false;
 766                         break;
 767                 }
 768 #endif
 769
 770                 if (offset < sg_tmp->length) {
 771                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 772                                 aligned = false;
 773                                 break;
 774                         }
 775
 776                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 777                                 aligned = false;
 778                                 break;
 779                         }
 780                 }
 781
 782                 if (offset) {
 783                         offset -= sg_tmp->length;
 784                         if (offset < 0) {
 785                                 nbytes += offset;
 786                                 offset = 0;
 787                         }
 788                 } else {
 789                         nbytes -= sg_tmp->length;
 790                 }
 791
 792                 sg_tmp = sg_next(sg_tmp);
 793
 794                 if (nbytes < 0) {
 795                         list_ok = false;
 796                         break;
 797                 }
 798         }
 799
 800         if (!aligned)
 801                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 802         else if (!list_ok)
 803                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 804
 805         rctx->sg_len = n;
 806         rctx->sg = sg;
 807
 808         return 0;
 809 }
 810
 811 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 812 {
 813         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 814         int bs;
 815         int ret;
 816         int nbytes;
 817         bool final = rctx->flags & BIT(FLAGS_FINUP);
 818         int xmit_len, hash_later;
 819
 820         bs = get_block_size(rctx);
 821
 822         if (update)
 823                 nbytes = req->nbytes;
 824         else
 825                 nbytes = 0;
 826
 827         rctx->total = nbytes + rctx->bufcnt;
 828
 829         if (!rctx->total)
 830                 return 0;
 831
 832         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 833                 int len = bs - rctx->bufcnt % bs;
 834
 835                 if (len > nbytes)
 836                         len = nbytes;
 837                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 838                                          0, len, 0);
 839                 rctx->bufcnt += len;
 840                 nbytes -= len;
 841                 rctx->offset = len;
 842         }
 843
 844         if (rctx->bufcnt)
 845                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 846
 847         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 848         if (ret)
 849                 return ret;
 850
 851         xmit_len = rctx->total;
 852
 853         if (!IS_ALIGNED(xmit_len, bs)) {
 854                 if (final)
 855                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 856                 else
 857                         xmit_len = xmit_len / bs * bs;
 858         } else if (!final) {
 859                 xmit_len -= bs;
 860         }
 861
 862         hash_later = rctx->total - xmit_len;
 863         if (hash_later < 0)
 864                 hash_later = 0;
 865
 866         if (rctx->bufcnt && nbytes) {
 867                 /* have data from previous operation and current */
 868                 sg_init_table(rctx->sgl, 2);
 869                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 870
 871                 sg_chain(rctx->sgl, 2, req->src);
 872
 873                 rctx->sg = rctx->sgl;
 874
 875                 rctx->sg_len++;
 876         } else if (rctx->bufcnt) {
 877                 /* have buffered data only */
 878                 sg_init_table(rctx->sgl, 1);
 879                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 880
 881                 rctx->sg = rctx->sgl;
 882
 883                 rctx->sg_len = 1;
 884         }
 885
 886         if (hash_later) {
 887                 int offset = 0;
 888
 889                 if (hash_later > req->nbytes) {
 890                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 891                                hash_later - req->nbytes);
 892                         offset = hash_later - req->nbytes;
 893                 }
 894
 895                 if (req->nbytes) {
 896                         scatterwalk_map_and_copy(rctx->buffer + offset,
 897                                                  req->src,
 898                                                  offset + req->nbytes -
 899                                                  hash_later, hash_later, 0);
 900                 }
 901
 902                 rctx->bufcnt = hash_later;
 903         } else {
 904                 rctx->bufcnt = 0;
 905         }
 906
 907         if (!final)
 908                 rctx->total = xmit_len;
 909
 910         return 0;
 911 }
 912
 913 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 914 {
 915         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 916
 917         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 918
 919         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 920
 921         return 0;
 922 }
 923
 924 static int omap_sham_init(struct ahash_request *req)
 925 {
 926         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 927         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 928         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 929         struct omap_sham_dev *dd = NULL, *tmp;
 930         int bs = 0;
 931
 932         spin_lock_bh(&sham.lock);
 933         if (!tctx->dd) {
 934                 list_for_each_entry(tmp, &sham.dev_list, list) {
 935                         dd = tmp;
 936                         break;
 937                 }
 938                 tctx->dd = dd;
 939         } else {
 940                 dd = tctx->dd;
 941         }
 942         spin_unlock_bh(&sham.lock);
 943
 944         ctx->dd = dd;
 945
 946         ctx->flags = 0;
 947
 948         dev_dbg(dd->dev, "init: digest size: %d\n",
 949                 crypto_ahash_digestsize(tfm));
 950
 951         switch (crypto_ahash_digestsize(tfm)) {
 952         case MD5_DIGEST_SIZE:
 953                 ctx->flags |= FLAGS_MODE_MD5;
 954                 bs = SHA1_BLOCK_SIZE;
 955                 break;
 956         case SHA1_DIGEST_SIZE:
 957                 ctx->flags |= FLAGS_MODE_SHA1;
 958                 bs = SHA1_BLOCK_SIZE;
 959                 break;
 960         case SHA224_DIGEST_SIZE:
 961                 ctx->flags |= FLAGS_MODE_SHA224;
 962                 bs = SHA224_BLOCK_SIZE;
 963                 break;
 964         case SHA256_DIGEST_SIZE:
 965                 ctx->flags |= FLAGS_MODE_SHA256;
 966                 bs = SHA256_BLOCK_SIZE;
 967                 break;
 968         case SHA384_DIGEST_SIZE:
 969                 ctx->flags |= FLAGS_MODE_SHA384;
 970                 bs = SHA384_BLOCK_SIZE;
 971                 break;
 972         case SHA512_DIGEST_SIZE:
 973                 ctx->flags |= FLAGS_MODE_SHA512;
 974                 bs = SHA512_BLOCK_SIZE;
 975                 break;
 976         }
 977
 978         ctx->bufcnt = 0;
 979         ctx->digcnt = 0;
 980         ctx->total = 0;
 981         ctx->offset = 0;
 982         ctx->buflen = BUFLEN;
 983
 984         if (tctx->flags & BIT(FLAGS_HMAC)) {
 985                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 986                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 987
 988                         memcpy(ctx->buffer, bctx->ipad, bs);
 989                         ctx->bufcnt = bs;
 990                 }
 991
 992                 ctx->flags |= BIT(FLAGS_HMAC);
 993         }
 994
 995         return 0;
 996
 997 }
 998
 999 static int omap_sham_update_req(struct omap_sham_dev *dd)
1000 {
1001         struct ahash_request *req = dd->req;
1002         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1003         int err;
1004         bool final = ctx->flags & BIT(FLAGS_FINUP);
1005
1006         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1007                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1008
1009         if (ctx->total < get_block_size(ctx) ||
1010             ctx->total < dd->fallback_sz)
1011                 ctx->flags |= BIT(FLAGS_CPU);
1012
1013         if (ctx->flags & BIT(FLAGS_CPU))
1014                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1015         else
1016                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1017
1018         /* wait for dma completion before can take more data */
1019         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1020
1021         return err;
1022 }
1023
1024 static int omap_sham_final_req(struct omap_sham_dev *dd)
1025 {
1026         struct ahash_request *req = dd->req;
1027         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1028         int err = 0, use_dma = 1;
1029
1030         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1031                 /*
1032                  * faster to handle last block with cpu or
1033                  * use cpu when dma is not present.
1034                  */
1035                 use_dma = 0;
1036
1037         if (use_dma)
1038                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1039         else
1040                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1041
1042         ctx->bufcnt = 0;
1043
1044         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1045
1046         return err;
1047 }
1048
1049 static int omap_sham_finish_hmac(struct ahash_request *req)
1050 {
1051         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1052         struct omap_sham_hmac_ctx *bctx = tctx->base;
1053         int bs = crypto_shash_blocksize(bctx->shash);
1054         int ds = crypto_shash_digestsize(bctx->shash);
1055         SHASH_DESC_ON_STACK(shash, bctx->shash);
1056
1057         shash->tfm = bctx->shash;
1058         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1059
1060         return crypto_shash_init(shash) ?:
1061                crypto_shash_update(shash, bctx->opad, bs) ?:
1062                crypto_shash_finup(shash, req->result, ds, req->result);
1063 }
1064
1065 static int omap_sham_finish(struct ahash_request *req)
1066 {
1067         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1068         struct omap_sham_dev *dd = ctx->dd;
1069         int err = 0;
1070
1071         if (ctx->digcnt) {
1072                 omap_sham_copy_ready_hash(req);
1073                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1074                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1075                         err = omap_sham_finish_hmac(req);
1076         }
1077
1078         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1079
1080         return err;
1081 }
1082
1083 static void omap_sham_finish_req(struct ahash_request *req, int err)
1084 {
1085         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1086         struct omap_sham_dev *dd = ctx->dd;
1087
1088         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1089                 free_pages((unsigned long)sg_virt(ctx->sg),
1090                            get_order(ctx->sg->length));
1091
1092         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1093                 kfree(ctx->sg);
1094
1095         ctx->sg = NULL;
1096
1097         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1098
1099         if (!err) {
1100                 dd->pdata->copy_hash(req, 1);
1101                 if (test_bit(FLAGS_FINAL, &dd->flags))
1102                         err = omap_sham_finish(req);
1103         } else {
1104                 ctx->flags |= BIT(FLAGS_ERROR);
1105         }
1106
1107         /* atomic operation is not needed here */
1108         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1109                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1110
1111         pm_runtime_mark_last_busy(dd->dev);
1112         pm_runtime_put_autosuspend(dd->dev);
1113
1114         if (req->base.complete)
1115                 req->base.complete(&req->base, err);
1116 }
1117
1118 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1119                                   struct ahash_request *req)
1120 {
1121         struct crypto_async_request *async_req, *backlog;
1122         struct omap_sham_reqctx *ctx;
1123         unsigned long flags;
1124         int err = 0, ret = 0;
1125
1126 retry:
1127         spin_lock_irqsave(&dd->lock, flags);
1128         if (req)
1129                 ret = ahash_enqueue_request(&dd->queue, req);
1130         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1131                 spin_unlock_irqrestore(&dd->lock, flags);
1132                 return ret;
1133         }
1134         backlog = crypto_get_backlog(&dd->queue);
1135         async_req = crypto_dequeue_request(&dd->queue);
1136         if (async_req)
1137                 set_bit(FLAGS_BUSY, &dd->flags);
1138         spin_unlock_irqrestore(&dd->lock, flags);
1139
1140         if (!async_req)
1141                 return ret;
1142
1143         if (backlog)
1144                 backlog->complete(backlog, -EINPROGRESS);
1145
1146         req = ahash_request_cast(async_req);
1147         dd->req = req;
1148         ctx = ahash_request_ctx(req);
1149
1150         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1151         if (err || !ctx->total)
1152                 goto err1;
1153
1154         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1155                                                 ctx->op, req->nbytes);
1156
1157         err = omap_sham_hw_init(dd);
1158         if (err)
1159                 goto err1;
1160
1161         if (ctx->digcnt)
1162                 /* request has changed - restore hash */
1163                 dd->pdata->copy_hash(req, 0);
1164
1165         if (ctx->op == OP_UPDATE) {
1166                 err = omap_sham_update_req(dd);
1167                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1168                         /* no final() after finup() */
1169                         err = omap_sham_final_req(dd);
1170         } else if (ctx->op == OP_FINAL) {
1171                 err = omap_sham_final_req(dd);
1172         }
1173 err1:
1174         dev_dbg(dd->dev, "exit, err: %d\n", err);
1175
1176         if (err != -EINPROGRESS) {
1177                 /* done_task will not finish it, so do it here */
1178                 omap_sham_finish_req(req, err);
1179                 req = NULL;
1180
1181                 /*
1182                  * Execute next request immediately if there is anything
1183                  * in queue.
1184                  */
1185                 goto retry;
1186         }
1187
1188         return ret;
1189 }
1190
1191 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1192 {
1193         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1194         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1195         struct omap_sham_dev *dd = tctx->dd;
1196
1197         ctx->op = op;
1198
1199         return omap_sham_handle_queue(dd, req);
1200 }
1201
1202 static int omap_sham_update(struct ahash_request *req)
1203 {
1204         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1205         struct omap_sham_dev *dd = ctx->dd;
1206
1207         if (!req->nbytes)
1208                 return 0;
1209
1210         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1211                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1212                                          0, req->nbytes, 0);
1213                 ctx->bufcnt += req->nbytes;
1214                 return 0;
1215         }
1216
1217         if (dd->polling_mode)
1218                 ctx->flags |= BIT(FLAGS_CPU);
1219
1220         return omap_sham_enqueue(req, OP_UPDATE);
1221 }
1222
1223 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1224                                   const u8 *data, unsigned int len, u8 *out)
1225 {
1226         SHASH_DESC_ON_STACK(shash, tfm);
1227
1228         shash->tfm = tfm;
1229         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1230
1231         return crypto_shash_digest(shash, data, len, out);
1232 }
1233
1234 static int omap_sham_final_shash(struct ahash_request *req)
1235 {
1236         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1237         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1238         int offset = 0;
1239
1240         /*
1241          * If we are running HMAC on limited hardware support, skip
1242          * the ipad in the beginning of the buffer if we are going for
1243          * software fallback algorithm.
1244          */
1245         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1246             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1247                 offset = get_block_size(ctx);
1248
1249         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1250                                       ctx->buffer + offset,
1251                                       ctx->bufcnt - offset, req->result);
1252 }
1253
1254 static int omap_sham_final(struct ahash_request *req)
1255 {
1256         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1257
1258         ctx->flags |= BIT(FLAGS_FINUP);
1259
1260         if (ctx->flags & BIT(FLAGS_ERROR))
1261                 return 0; /* uncompleted hash is not needed */
1262
1263         /*
1264          * OMAP HW accel works only with buffers >= 9.
1265          * HMAC is always >= 9 because ipad == block size.
1266          * If buffersize is less than fallback_sz, we use fallback
1267          * SW encoding, as using DMA + HW in this case doesn't provide
1268          * any benefit.
1269          */
1270         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1271                 return omap_sham_final_shash(req);
1272         else if (ctx->bufcnt)
1273                 return omap_sham_enqueue(req, OP_FINAL);
1274
1275         /* copy ready hash (+ finalize hmac) */
1276         return omap_sham_finish(req);
1277 }
1278
1279 static int omap_sham_finup(struct ahash_request *req)
1280 {
1281         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1282         int err1, err2;
1283
1284         ctx->flags |= BIT(FLAGS_FINUP);
1285
1286         err1 = omap_sham_update(req);
1287         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1288                 return err1;
1289         /*
1290          * final() has to be always called to cleanup resources
1291          * even if udpate() failed, except EINPROGRESS
1292          */
1293         err2 = omap_sham_final(req);
1294
1295         return err1 ?: err2;
1296 }
1297
1298 static int omap_sham_digest(struct ahash_request *req)
1299 {
1300         return omap_sham_init(req) ?: omap_sham_finup(req);
1301 }
1302
1303 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1304                       unsigned int keylen)
1305 {
1306         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1307         struct omap_sham_hmac_ctx *bctx = tctx->base;
1308         int bs = crypto_shash_blocksize(bctx->shash);
1309         int ds = crypto_shash_digestsize(bctx->shash);
1310         struct omap_sham_dev *dd = NULL, *tmp;
1311         int err, i;
1312
1313         spin_lock_bh(&sham.lock);
1314         if (!tctx->dd) {
1315                 list_for_each_entry(tmp, &sham.dev_list, list) {
1316                         dd = tmp;
1317                         break;
1318                 }
1319                 tctx->dd = dd;
1320         } else {
1321                 dd = tctx->dd;
1322         }
1323         spin_unlock_bh(&sham.lock);
1324
1325         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1326         if (err)
1327                 return err;
1328
1329         if (keylen > bs) {
1330                 err = omap_sham_shash_digest(bctx->shash,
1331                                 crypto_shash_get_flags(bctx->shash),
1332                                 key, keylen, bctx->ipad);
1333                 if (err)
1334                         return err;
1335                 keylen = ds;
1336         } else {
1337                 memcpy(bctx->ipad, key, keylen);
1338         }
1339
1340         memset(bctx->ipad + keylen, 0, bs - keylen);
1341
1342         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1343                 memcpy(bctx->opad, bctx->ipad, bs);
1344
1345                 for (i = 0; i < bs; i++) {
1346                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1347                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1348                 }
1349         }
1350
1351         return err;
1352 }
1353
1354 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1355 {
1356         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1357         const char *alg_name = crypto_tfm_alg_name(tfm);
1358
1359         /* Allocate a fallback and abort if it failed. */
1360         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1361                                             CRYPTO_ALG_NEED_FALLBACK);
1362         if (IS_ERR(tctx->fallback)) {
1363                 pr_err("omap-sham: fallback driver '%s' "
1364                                 "could not be loaded.\n", alg_name);
1365                 return PTR_ERR(tctx->fallback);
1366         }
1367
1368         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1369                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1370
1371         if (alg_base) {
1372                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1373                 tctx->flags |= BIT(FLAGS_HMAC);
1374                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1375                                                 CRYPTO_ALG_NEED_FALLBACK);
1376                 if (IS_ERR(bctx->shash)) {
1377                         pr_err("omap-sham: base driver '%s' "
1378                                         "could not be loaded.\n", alg_base);
1379                         crypto_free_shash(tctx->fallback);
1380                         return PTR_ERR(bctx->shash);
1381                 }
1382
1383         }
1384
1385         return 0;
1386 }
1387
1388 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1389 {
1390         return omap_sham_cra_init_alg(tfm, NULL);
1391 }
1392
1393 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1394 {
1395         return omap_sham_cra_init_alg(tfm, "sha1");
1396 }
1397
1398 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1399 {
1400         return omap_sham_cra_init_alg(tfm, "sha224");
1401 }
1402
1403 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1404 {
1405         return omap_sham_cra_init_alg(tfm, "sha256");
1406 }
1407
1408 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1409 {
1410         return omap_sham_cra_init_alg(tfm, "md5");
1411 }
1412
1413 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1414 {
1415         return omap_sham_cra_init_alg(tfm, "sha384");
1416 }
1417
1418 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1419 {
1420         return omap_sham_cra_init_alg(tfm, "sha512");
1421 }
1422
1423 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1424 {
1425         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1426
1427         crypto_free_shash(tctx->fallback);
1428         tctx->fallback = NULL;
1429
1430         if (tctx->flags & BIT(FLAGS_HMAC)) {
1431                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1432                 crypto_free_shash(bctx->shash);
1433         }
1434 }
1435
1436 static int omap_sham_export(struct ahash_request *req, void *out)
1437 {
1438         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1439
1440         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1441
1442         return 0;
1443 }
1444
1445 static int omap_sham_import(struct ahash_request *req, const void *in)
1446 {
1447         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1448         const struct omap_sham_reqctx *ctx_in = in;
1449
1450         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1451
1452         return 0;
1453 }
1454
1455 static struct ahash_alg algs_sha1_md5[] = {
1456 {
1457         .init           = omap_sham_init,
1458         .update         = omap_sham_update,
1459         .final          = omap_sham_final,
1460         .finup          = omap_sham_finup,
1461         .digest         = omap_sham_digest,
1462         .halg.digestsize        = SHA1_DIGEST_SIZE,
1463         .halg.base      = {
1464                 .cra_name               = "sha1",
1465                 .cra_driver_name        = "omap-sha1",
1466                 .cra_priority           = 400,
1467                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1468                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1469                                                 CRYPTO_ALG_ASYNC |
1470                                                 CRYPTO_ALG_NEED_FALLBACK,
1471                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1472                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1473                 .cra_alignmask          = OMAP_ALIGN_MASK,
1474                 .cra_module             = THIS_MODULE,
1475                 .cra_init               = omap_sham_cra_init,
1476                 .cra_exit               = omap_sham_cra_exit,
1477         }
1478 },
1479 {
1480         .init           = omap_sham_init,
1481         .update         = omap_sham_update,
1482         .final          = omap_sham_final,
1483         .finup          = omap_sham_finup,
1484         .digest         = omap_sham_digest,
1485         .halg.digestsize        = MD5_DIGEST_SIZE,
1486         .halg.base      = {
1487                 .cra_name               = "md5",
1488                 .cra_driver_name        = "omap-md5",
1489                 .cra_priority           = 400,
1490                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1491                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1492                                                 CRYPTO_ALG_ASYNC |
1493                                                 CRYPTO_ALG_NEED_FALLBACK,
1494                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1495                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1496                 .cra_alignmask          = OMAP_ALIGN_MASK,
1497                 .cra_module             = THIS_MODULE,
1498                 .cra_init               = omap_sham_cra_init,
1499                 .cra_exit               = omap_sham_cra_exit,
1500         }
1501 },
1502 {
1503         .init           = omap_sham_init,
1504         .update         = omap_sham_update,
1505         .final          = omap_sham_final,
1506         .finup          = omap_sham_finup,
1507         .digest         = omap_sham_digest,
1508         .setkey         = omap_sham_setkey,
1509         .halg.digestsize        = SHA1_DIGEST_SIZE,
1510         .halg.base      = {
1511                 .cra_name               = "hmac(sha1)",
1512                 .cra_driver_name        = "omap-hmac-sha1",
1513                 .cra_priority           = 400,
1514                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1515                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1516                                                 CRYPTO_ALG_ASYNC |
1517                                                 CRYPTO_ALG_NEED_FALLBACK,
1518                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1519                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1520                                         sizeof(struct omap_sham_hmac_ctx),
1521                 .cra_alignmask          = OMAP_ALIGN_MASK,
1522                 .cra_module             = THIS_MODULE,
1523                 .cra_init               = omap_sham_cra_sha1_init,
1524                 .cra_exit               = omap_sham_cra_exit,
1525         }
1526 },
1527 {
1528         .init           = omap_sham_init,
1529         .update         = omap_sham_update,
1530         .final          = omap_sham_final,
1531         .finup          = omap_sham_finup,
1532         .digest         = omap_sham_digest,
1533         .setkey         = omap_sham_setkey,
1534         .halg.digestsize        = MD5_DIGEST_SIZE,
1535         .halg.base      = {
1536                 .cra_name               = "hmac(md5)",
1537                 .cra_driver_name        = "omap-hmac-md5",
1538                 .cra_priority           = 400,
1539                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1540                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1541                                                 CRYPTO_ALG_ASYNC |
1542                                                 CRYPTO_ALG_NEED_FALLBACK,
1543                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1544                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1545                                         sizeof(struct omap_sham_hmac_ctx),
1546                 .cra_alignmask          = OMAP_ALIGN_MASK,
1547                 .cra_module             = THIS_MODULE,
1548                 .cra_init               = omap_sham_cra_md5_init,
1549                 .cra_exit               = omap_sham_cra_exit,
1550         }
1551 }
1552 };
1553
1554 /* OMAP4 has some algs in addition to what OMAP2 has */
1555 static struct ahash_alg algs_sha224_sha256[] = {
1556 {
1557         .init           = omap_sham_init,
1558         .update         = omap_sham_update,
1559         .final          = omap_sham_final,
1560         .finup          = omap_sham_finup,
1561         .digest         = omap_sham_digest,
1562         .halg.digestsize        = SHA224_DIGEST_SIZE,
1563         .halg.base      = {
1564                 .cra_name               = "sha224",
1565                 .cra_driver_name        = "omap-sha224",
1566                 .cra_priority           = 400,
1567                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1568                                                 CRYPTO_ALG_ASYNC |
1569                                                 CRYPTO_ALG_NEED_FALLBACK,
1570                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1571                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1572                 .cra_alignmask          = OMAP_ALIGN_MASK,
1573                 .cra_module             = THIS_MODULE,
1574                 .cra_init               = omap_sham_cra_init,
1575                 .cra_exit               = omap_sham_cra_exit,
1576         }
1577 },
1578 {
1579         .init           = omap_sham_init,
1580         .update         = omap_sham_update,
1581         .final          = omap_sham_final,
1582         .finup          = omap_sham_finup,
1583         .digest         = omap_sham_digest,
1584         .halg.digestsize        = SHA256_DIGEST_SIZE,
1585         .halg.base      = {
1586                 .cra_name               = "sha256",
1587                 .cra_driver_name        = "omap-sha256",
1588                 .cra_priority           = 400,
1589                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1590                                                 CRYPTO_ALG_ASYNC |
1591                                                 CRYPTO_ALG_NEED_FALLBACK,
1592                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1593                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1594                 .cra_alignmask          = OMAP_ALIGN_MASK,
1595                 .cra_module             = THIS_MODULE,
1596                 .cra_init               = omap_sham_cra_init,
1597                 .cra_exit               = omap_sham_cra_exit,
1598         }
1599 },
1600 {
1601         .init           = omap_sham_init,
1602         .update         = omap_sham_update,
1603         .final          = omap_sham_final,
1604         .finup          = omap_sham_finup,
1605         .digest         = omap_sham_digest,
1606         .setkey         = omap_sham_setkey,
1607         .halg.digestsize        = SHA224_DIGEST_SIZE,
1608         .halg.base      = {
1609                 .cra_name               = "hmac(sha224)",
1610                 .cra_driver_name        = "omap-hmac-sha224",
1611                 .cra_priority           = 400,
1612                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1613                                                 CRYPTO_ALG_ASYNC |
1614                                                 CRYPTO_ALG_NEED_FALLBACK,
1615                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1616                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1617                                         sizeof(struct omap_sham_hmac_ctx),
1618                 .cra_alignmask          = OMAP_ALIGN_MASK,
1619                 .cra_module             = THIS_MODULE,
1620                 .cra_init               = omap_sham_cra_sha224_init,
1621                 .cra_exit               = omap_sham_cra_exit,
1622         }
1623 },
1624 {
1625         .init           = omap_sham_init,
1626         .update         = omap_sham_update,
1627         .final          = omap_sham_final,
1628         .finup          = omap_sham_finup,
1629         .digest         = omap_sham_digest,
1630         .setkey         = omap_sham_setkey,
1631         .halg.digestsize        = SHA256_DIGEST_SIZE,
1632         .halg.base      = {
1633                 .cra_name               = "hmac(sha256)",
1634                 .cra_driver_name        = "omap-hmac-sha256",
1635                 .cra_priority           = 400,
1636                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1637                                                 CRYPTO_ALG_ASYNC |
1638                                                 CRYPTO_ALG_NEED_FALLBACK,
1639                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1640                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1641                                         sizeof(struct omap_sham_hmac_ctx),
1642                 .cra_alignmask          = OMAP_ALIGN_MASK,
1643                 .cra_module             = THIS_MODULE,
1644                 .cra_init               = omap_sham_cra_sha256_init,
1645                 .cra_exit               = omap_sham_cra_exit,
1646         }
1647 },
1648 };
1649
1650 static struct ahash_alg algs_sha384_sha512[] = {
1651 {
1652         .init           = omap_sham_init,
1653         .update         = omap_sham_update,
1654         .final          = omap_sham_final,
1655         .finup          = omap_sham_finup,
1656         .digest         = omap_sham_digest,
1657         .halg.digestsize        = SHA384_DIGEST_SIZE,
1658         .halg.base      = {
1659                 .cra_name               = "sha384",
1660                 .cra_driver_name        = "omap-sha384",
1661                 .cra_priority           = 400,
1662                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1663                                                 CRYPTO_ALG_ASYNC |
1664                                                 CRYPTO_ALG_NEED_FALLBACK,
1665                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1666                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1667                 .cra_alignmask          = OMAP_ALIGN_MASK,
1668                 .cra_module             = THIS_MODULE,
1669                 .cra_init               = omap_sham_cra_init,
1670                 .cra_exit               = omap_sham_cra_exit,
1671         }
1672 },
1673 {
1674         .init           = omap_sham_init,
1675         .update         = omap_sham_update,
1676         .final          = omap_sham_final,
1677         .finup          = omap_sham_finup,
1678         .digest         = omap_sham_digest,
1679         .halg.digestsize        = SHA512_DIGEST_SIZE,
1680         .halg.base      = {
1681                 .cra_name               = "sha512",
1682                 .cra_driver_name        = "omap-sha512",
1683                 .cra_priority           = 400,
1684                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1685                                                 CRYPTO_ALG_ASYNC |
1686                                                 CRYPTO_ALG_NEED_FALLBACK,
1687                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1688                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1689                 .cra_alignmask          = OMAP_ALIGN_MASK,
1690                 .cra_module             = THIS_MODULE,
1691                 .cra_init               = omap_sham_cra_init,
1692                 .cra_exit               = omap_sham_cra_exit,
1693         }
1694 },
1695 {
1696         .init           = omap_sham_init,
1697         .update         = omap_sham_update,
1698         .final          = omap_sham_final,
1699         .finup          = omap_sham_finup,
1700         .digest         = omap_sham_digest,
1701         .setkey         = omap_sham_setkey,
1702         .halg.digestsize        = SHA384_DIGEST_SIZE,
1703         .halg.base      = {
1704                 .cra_name               = "hmac(sha384)",
1705                 .cra_driver_name        = "omap-hmac-sha384",
1706                 .cra_priority           = 400,
1707                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1708                                                 CRYPTO_ALG_ASYNC |
1709                                                 CRYPTO_ALG_NEED_FALLBACK,
1710                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1711                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1712                                         sizeof(struct omap_sham_hmac_ctx),
1713                 .cra_alignmask          = OMAP_ALIGN_MASK,
1714                 .cra_module             = THIS_MODULE,
1715                 .cra_init               = omap_sham_cra_sha384_init,
1716                 .cra_exit               = omap_sham_cra_exit,
1717         }
1718 },
1719 {
1720         .init           = omap_sham_init,
1721         .update         = omap_sham_update,
1722         .final          = omap_sham_final,
1723         .finup          = omap_sham_finup,
1724         .digest         = omap_sham_digest,
1725         .setkey         = omap_sham_setkey,
1726         .halg.digestsize        = SHA512_DIGEST_SIZE,
1727         .halg.base      = {
1728                 .cra_name               = "hmac(sha512)",
1729                 .cra_driver_name        = "omap-hmac-sha512",
1730                 .cra_priority           = 400,
1731                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1732                                                 CRYPTO_ALG_ASYNC |
1733                                                 CRYPTO_ALG_NEED_FALLBACK,
1734                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1735                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1736                                         sizeof(struct omap_sham_hmac_ctx),
1737                 .cra_alignmask          = OMAP_ALIGN_MASK,
1738                 .cra_module             = THIS_MODULE,
1739                 .cra_init               = omap_sham_cra_sha512_init,
1740                 .cra_exit               = omap_sham_cra_exit,
1741         }
1742 },
1743 };
1744
1745 static void omap_sham_done_task(unsigned long data)
1746 {
1747         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1748         int err = 0;
1749
1750         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1751                 omap_sham_handle_queue(dd, NULL);
1752                 return;
1753         }
1754
1755         if (test_bit(FLAGS_CPU, &dd->flags)) {
1756                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1757                         goto finish;
1758         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1759                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1760                         omap_sham_update_dma_stop(dd);
1761                         if (dd->err) {
1762                                 err = dd->err;
1763                                 goto finish;
1764                         }
1765                 }
1766                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1767                         /* hash or semi-hash ready */
1768                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1769                                 goto finish;
1770                 }
1771         }
1772
1773         return;
1774
1775 finish:
1776         dev_dbg(dd->dev, "update done: err: %d\n", err);
1777         /* finish curent request */
1778         omap_sham_finish_req(dd->req, err);
1779
1780         /* If we are not busy, process next req */
1781         if (!test_bit(FLAGS_BUSY, &dd->flags))
1782                 omap_sham_handle_queue(dd, NULL);
1783 }
1784
1785 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1786 {
1787         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1788                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1789         } else {
1790                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1791                 tasklet_schedule(&dd->done_task);
1792         }
1793
1794         return IRQ_HANDLED;
1795 }
1796
1797 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1798 {
1799         struct omap_sham_dev *dd = dev_id;
1800
1801         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1802                 /* final -> allow device to go to power-saving mode */
1803                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1804
1805         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1806                                  SHA_REG_CTRL_OUTPUT_READY);
1807         omap_sham_read(dd, SHA_REG_CTRL);
1808
1809         return omap_sham_irq_common(dd);
1810 }
1811
1812 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1813 {
1814         struct omap_sham_dev *dd = dev_id;
1815
1816         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1817
1818         return omap_sham_irq_common(dd);
1819 }
1820
1821 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1822         {
1823                 .algs_list      = algs_sha1_md5,
1824                 .size           = ARRAY_SIZE(algs_sha1_md5),
1825         },
1826 };
1827
1828 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1829         .algs_info      = omap_sham_algs_info_omap2,
1830         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1831         .flags          = BIT(FLAGS_BE32_SHA1),
1832         .digest_size    = SHA1_DIGEST_SIZE,
1833         .copy_hash      = omap_sham_copy_hash_omap2,
1834         .write_ctrl     = omap_sham_write_ctrl_omap2,
1835         .trigger        = omap_sham_trigger_omap2,
1836         .poll_irq       = omap_sham_poll_irq_omap2,
1837         .intr_hdlr      = omap_sham_irq_omap2,
1838         .idigest_ofs    = 0x00,
1839         .din_ofs        = 0x1c,
1840         .digcnt_ofs     = 0x14,
1841         .rev_ofs        = 0x5c,
1842         .mask_ofs       = 0x60,
1843         .sysstatus_ofs  = 0x64,
1844         .major_mask     = 0xf0,
1845         .major_shift    = 4,
1846         .minor_mask     = 0x0f,
1847         .minor_shift    = 0,
1848 };
1849
1850 #ifdef CONFIG_OF
1851 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1852         {
1853                 .algs_list      = algs_sha1_md5,
1854                 .size           = ARRAY_SIZE(algs_sha1_md5),
1855         },
1856         {
1857                 .algs_list      = algs_sha224_sha256,
1858                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1859         },
1860 };
1861
1862 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1863         .algs_info      = omap_sham_algs_info_omap4,
1864         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1865         .flags          = BIT(FLAGS_AUTO_XOR),
1866         .digest_size    = SHA256_DIGEST_SIZE,
1867         .copy_hash      = omap_sham_copy_hash_omap4,
1868         .write_ctrl     = omap_sham_write_ctrl_omap4,
1869         .trigger        = omap_sham_trigger_omap4,
1870         .poll_irq       = omap_sham_poll_irq_omap4,
1871         .intr_hdlr      = omap_sham_irq_omap4,
1872         .idigest_ofs    = 0x020,
1873         .odigest_ofs    = 0x0,
1874         .din_ofs        = 0x080,
1875         .digcnt_ofs     = 0x040,
1876         .rev_ofs        = 0x100,
1877         .mask_ofs       = 0x110,
1878         .sysstatus_ofs  = 0x114,
1879         .mode_ofs       = 0x44,
1880         .length_ofs     = 0x48,
1881         .major_mask     = 0x0700,
1882         .major_shift    = 8,
1883         .minor_mask     = 0x003f,
1884         .minor_shift    = 0,
1885 };
1886
1887 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1888         {
1889                 .algs_list      = algs_sha1_md5,
1890                 .size           = ARRAY_SIZE(algs_sha1_md5),
1891         },
1892         {
1893                 .algs_list      = algs_sha224_sha256,
1894                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1895         },
1896         {
1897                 .algs_list      = algs_sha384_sha512,
1898                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1899         },
1900 };
1901
1902 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1903         .algs_info      = omap_sham_algs_info_omap5,
1904         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1905         .flags          = BIT(FLAGS_AUTO_XOR),
1906         .digest_size    = SHA512_DIGEST_SIZE,
1907         .copy_hash      = omap_sham_copy_hash_omap4,
1908         .write_ctrl     = omap_sham_write_ctrl_omap4,
1909         .trigger        = omap_sham_trigger_omap4,
1910         .poll_irq       = omap_sham_poll_irq_omap4,
1911         .intr_hdlr      = omap_sham_irq_omap4,
1912         .idigest_ofs    = 0x240,
1913         .odigest_ofs    = 0x200,
1914         .din_ofs        = 0x080,
1915         .digcnt_ofs     = 0x280,
1916         .rev_ofs        = 0x100,
1917         .mask_ofs       = 0x110,
1918         .sysstatus_ofs  = 0x114,
1919         .mode_ofs       = 0x284,
1920         .length_ofs     = 0x288,
1921         .major_mask     = 0x0700,
1922         .major_shift    = 8,
1923         .minor_mask     = 0x003f,
1924         .minor_shift    = 0,
1925 };
1926
1927 static const struct of_device_id omap_sham_of_match[] = {
1928         {
1929                 .compatible     = "ti,omap2-sham",
1930                 .data           = &omap_sham_pdata_omap2,
1931         },
1932         {
1933                 .compatible     = "ti,omap3-sham",
1934                 .data           = &omap_sham_pdata_omap2,
1935         },
1936         {
1937                 .compatible     = "ti,omap4-sham",
1938                 .data           = &omap_sham_pdata_omap4,
1939         },
1940         {
1941                 .compatible     = "ti,omap5-sham",
1942                 .data           = &omap_sham_pdata_omap5,
1943         },
1944         {},
1945 };
1946 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1947
1948 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1949                 struct device *dev, struct resource *res)
1950 {
1951         struct device_node *node = dev->of_node;
1952         int err = 0;
1953
1954         dd->pdata = of_device_get_match_data(dev);
1955         if (!dd->pdata) {
1956                 dev_err(dev, "no compatible OF match\n");
1957                 err = -EINVAL;
1958                 goto err;
1959         }
1960
1961         err = of_address_to_resource(node, 0, res);
1962         if (err < 0) {
1963                 dev_err(dev, "can't translate OF node address\n");
1964                 err = -EINVAL;
1965                 goto err;
1966         }
1967
1968         dd->irq = irq_of_parse_and_map(node, 0);
1969         if (!dd->irq) {
1970                 dev_err(dev, "can't translate OF irq value\n");
1971                 err = -EINVAL;
1972                 goto err;
1973         }
1974
1975 err:
1976         return err;
1977 }
1978 #else
1979 static const struct of_device_id omap_sham_of_match[] = {
1980         {},
1981 };
1982
1983 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1984                 struct device *dev, struct resource *res)
1985 {
1986         return -EINVAL;
1987 }
1988 #endif
1989
1990 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1991                 struct platform_device *pdev, struct resource *res)
1992 {
1993         struct device *dev = &pdev->dev;
1994         struct resource *r;
1995         int err = 0;
1996
1997         /* Get the base address */
1998         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1999         if (!r) {
2000                 dev_err(dev, "no MEM resource info\n");
2001                 err = -ENODEV;
2002                 goto err;
2003         }
2004         memcpy(res, r, sizeof(*res));
2005
2006         /* Get the IRQ */
2007         dd->irq = platform_get_irq(pdev, 0);
2008         if (dd->irq < 0) {
2009                 dev_err(dev, "no IRQ resource info\n");
2010                 err = dd->irq;
2011                 goto err;
2012         }
2013
2014         /* Only OMAP2/3 can be non-DT */
2015         dd->pdata = &omap_sham_pdata_omap2;
2016
2017 err:
2018         return err;
2019 }
2020
2021 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2022                              char *buf)
2023 {
2024         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2025
2026         return sprintf(buf, "%d\n", dd->fallback_sz);
2027 }
2028
2029 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2030                               const char *buf, size_t size)
2031 {
2032         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2033         ssize_t status;
2034         long value;
2035
2036         status = kstrtol(buf, 0, &value);
2037         if (status)
2038                 return status;
2039
2040         /* HW accelerator only works with buffers > 9 */
2041         if (value < 9) {
2042                 dev_err(dev, "minimum fallback size 9\n");
2043                 return -EINVAL;
2044         }
2045
2046         dd->fallback_sz = value;
2047
2048         return size;
2049 }
2050
2051 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2052                               char *buf)
2053 {
2054         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2055
2056         return sprintf(buf, "%d\n", dd->queue.max_qlen);
2057 }
2058
2059 static ssize_t queue_len_store(struct device *dev,
2060                                struct device_attribute *attr, const char *buf,
2061                                size_t size)
2062 {
2063         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2064         ssize_t status;
2065         long value;
2066         unsigned long flags;
2067
2068         status = kstrtol(buf, 0, &value);
2069         if (status)
2070                 return status;
2071
2072         if (value < 1)
2073                 return -EINVAL;
2074
2075         /*
2076          * Changing the queue size in fly is safe, if size becomes smaller
2077          * than current size, it will just not accept new entries until
2078          * it has shrank enough.
2079          */
2080         spin_lock_irqsave(&dd->lock, flags);
2081         dd->queue.max_qlen = value;
2082         spin_unlock_irqrestore(&dd->lock, flags);
2083
2084         return size;
2085 }
2086
2087 static DEVICE_ATTR_RW(queue_len);
2088 static DEVICE_ATTR_RW(fallback);
2089
2090 static struct attribute *omap_sham_attrs[] = {
2091         &dev_attr_queue_len.attr,
2092         &dev_attr_fallback.attr,
2093         NULL,
2094 };
2095
2096 static struct attribute_group omap_sham_attr_group = {
2097         .attrs = omap_sham_attrs,
2098 };
2099
2100 static int omap_sham_probe(struct platform_device *pdev)
2101 {
2102         struct omap_sham_dev *dd;
2103         struct device *dev = &pdev->dev;
2104         struct resource res;
2105         dma_cap_mask_t mask;
2106         int err, i, j;
2107         u32 rev;
2108
2109         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2110         if (dd == NULL) {
2111                 dev_err(dev, "unable to alloc data struct.\n");
2112                 err = -ENOMEM;
2113                 goto data_err;
2114         }
2115         dd->dev = dev;
2116         platform_set_drvdata(pdev, dd);
2117
2118         INIT_LIST_HEAD(&dd->list);
2119         spin_lock_init(&dd->lock);
2120         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2121         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2122
2123         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2124                                omap_sham_get_res_pdev(dd, pdev, &res);
2125         if (err)
2126                 goto data_err;
2127
2128         dd->io_base = devm_ioremap_resource(dev, &res);
2129         if (IS_ERR(dd->io_base)) {
2130                 err = PTR_ERR(dd->io_base);
2131                 goto data_err;
2132         }
2133         dd->phys_base = res.start;
2134
2135         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2136                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2137         if (err) {
2138                 dev_err(dev, "unable to request irq %d, err = %d\n",
2139                         dd->irq, err);
2140                 goto data_err;
2141         }
2142
2143         dma_cap_zero(mask);
2144         dma_cap_set(DMA_SLAVE, mask);
2145
2146         dd->dma_lch = dma_request_chan(dev, "rx");
2147         if (IS_ERR(dd->dma_lch)) {
2148                 err = PTR_ERR(dd->dma_lch);
2149                 if (err == -EPROBE_DEFER)
2150                         goto data_err;
2151
2152                 dd->polling_mode = 1;
2153                 dev_dbg(dev, "using polling mode instead of dma\n");
2154         }
2155
2156         dd->flags |= dd->pdata->flags;
2157
2158         pm_runtime_use_autosuspend(dev);
2159         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2160
2161         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2162
2163         pm_runtime_enable(dev);
2164         pm_runtime_irq_safe(dev);
2165
2166         err = pm_runtime_get_sync(dev);
2167         if (err < 0) {
2168                 dev_err(dev, "failed to get sync: %d\n", err);
2169                 goto err_pm;
2170         }
2171
2172         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2173         pm_runtime_put_sync(&pdev->dev);
2174
2175         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2176                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2177                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2178
2179         spin_lock(&sham.lock);
2180         list_add_tail(&dd->list, &sham.dev_list);
2181         spin_unlock(&sham.lock);
2182
2183         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2184                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2185                         struct ahash_alg *alg;
2186
2187                         alg = &dd->pdata->algs_info[i].algs_list[j];
2188                         alg->export = omap_sham_export;
2189                         alg->import = omap_sham_import;
2190                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2191                                               BUFLEN;
2192                         err = crypto_register_ahash(alg);
2193                         if (err)
2194                                 goto err_algs;
2195
2196                         dd->pdata->algs_info[i].registered++;
2197                 }
2198         }
2199
2200         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2201         if (err) {
2202                 dev_err(dev, "could not create sysfs device attrs\n");
2203                 goto err_algs;
2204         }
2205
2206         return 0;
2207
2208 err_algs:
2209         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2210                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2211                         crypto_unregister_ahash(
2212                                         &dd->pdata->algs_info[i].algs_list[j]);
2213 err_pm:
2214         pm_runtime_disable(dev);
2215         if (!dd->polling_mode)
2216                 dma_release_channel(dd->dma_lch);
2217 data_err:
2218         dev_err(dev, "initialization failed.\n");
2219
2220         return err;
2221 }
2222
2223 static int omap_sham_remove(struct platform_device *pdev)
2224 {
2225         struct omap_sham_dev *dd;
2226         int i, j;
2227
2228         dd = platform_get_drvdata(pdev);
2229         if (!dd)
2230                 return -ENODEV;
2231         spin_lock(&sham.lock);
2232         list_del(&dd->list);
2233         spin_unlock(&sham.lock);
2234         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2235                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2236                         crypto_unregister_ahash(
2237                                         &dd->pdata->algs_info[i].algs_list[j]);
2238         tasklet_kill(&dd->done_task);
2239         pm_runtime_disable(&pdev->dev);
2240
2241         if (!dd->polling_mode)
2242                 dma_release_channel(dd->dma_lch);
2243
2244         return 0;
2245 }
2246
2247 #ifdef CONFIG_PM_SLEEP
2248 static int omap_sham_suspend(struct device *dev)
2249 {
2250         pm_runtime_put_sync(dev);
2251         return 0;
2252 }
2253
2254 static int omap_sham_resume(struct device *dev)
2255 {
2256         int err = pm_runtime_get_sync(dev);
2257         if (err < 0) {
2258                 dev_err(dev, "failed to get sync: %d\n", err);
2259                 return err;
2260         }
2261         return 0;
2262 }
2263 #endif
2264
2265 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2266
2267 static struct platform_driver omap_sham_driver = {
2268         .probe  = omap_sham_probe,
2269         .remove = omap_sham_remove,
2270         .driver = {
2271                 .name   = "omap-sham",
2272                 .pm     = &omap_sham_pm_ops,
2273                 .of_match_table = omap_sham_of_match,
2274         },
2275 };
2276
2277 module_platform_driver(omap_sham_driver);
2278
2279 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2280 MODULE_LICENSE("GPL v2");
2281 MODULE_AUTHOR("Dmitry Kasatkin");
2282 MODULE_ALIAS("platform:omap-sham");