drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as published
  11  * by the Free Software Foundation.
  12  *
  13  * Some ideas are from old omap-sha1-md5.c driver.
  14  */
  15
  16 #define pr_fmt(fmt) "%s: " fmt, __func__
  17
  18 #include <linux/err.h>
  19 #include <linux/device.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/clk.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/crypto.h>
  33 #include <linux/cryptohash.h>
  34 #include <crypto/scatterwalk.h>
  35 #include <crypto/algapi.h>
  36 #include <crypto/sha.h>
  37 #include <crypto/hash.h>
  38 #include <crypto/internal/hash.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/dma.h>
  42 #include <mach/irqs.h>
  43
  44 #define SHA_REG_DIGEST(x)               (0x00 + ((x) * 0x04))
  45 #define SHA_REG_DIN(x)                  (0x1C + ((x) * 0x04))
  46
  47 #define SHA1_MD5_BLOCK_SIZE             SHA1_BLOCK_SIZE
  48 #define MD5_DIGEST_SIZE                 16
  49
  50 #define SHA_REG_DIGCNT                  0x14
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV                     0x5C
  61 #define SHA_REG_REV_MAJOR               0xF0
  62 #define SHA_REG_REV_MINOR               0x0F
  63
  64 #define SHA_REG_MASK                    0x60
  65 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  66 #define SHA_REG_MASK_IT_EN              (1 << 2)
  67 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  68 #define SHA_REG_AUTOIDLE                (1 << 0)
  69
  70 #define SHA_REG_SYSSTATUS               0x64
  71 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  72
  73 #define DEFAULT_TIMEOUT_INTERVAL        HZ
  74
  75 /* mostly device flags */
  76 #define FLAGS_BUSY              0
  77 #define FLAGS_FINAL             1
  78 #define FLAGS_DMA_ACTIVE        2
  79 #define FLAGS_OUTPUT_READY      3
  80 #define FLAGS_INIT              4
  81 #define FLAGS_CPU               5
  82 #define FLAGS_DMA_READY         6
  83 /* context flags */
  84 #define FLAGS_FINUP             16
  85 #define FLAGS_SG                17
  86 #define FLAGS_SHA1              18
  87 #define FLAGS_HMAC              19
  88 #define FLAGS_ERROR             20
  89
  90 #define OP_UPDATE       1
  91 #define OP_FINAL        2
  92
  93 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
  94 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
  95
  96 #define BUFLEN          PAGE_SIZE
  97
  98 struct omap_sham_dev;
  99
 100 struct omap_sham_reqctx {
 101         struct omap_sham_dev    *dd;
 102         unsigned long           flags;
 103         unsigned long           op;
 104
 105         u8                      digest[SHA1_DIGEST_SIZE] OMAP_ALIGNED;
 106         size_t                  digcnt;
 107         size_t                  bufcnt;
 108         size_t                  buflen;
 109         dma_addr_t              dma_addr;
 110
 111         /* walk state */
 112         struct scatterlist      *sg;
 113         unsigned int            offset; /* offset in current sg */
 114         unsigned int            total;  /* total request */
 115
 116         u8                      buffer[0] OMAP_ALIGNED;
 117 };
 118
 119 struct omap_sham_hmac_ctx {
 120         struct crypto_shash     *shash;
 121         u8                      ipad[SHA1_MD5_BLOCK_SIZE];
 122         u8                      opad[SHA1_MD5_BLOCK_SIZE];
 123 };
 124
 125 struct omap_sham_ctx {
 126         struct omap_sham_dev    *dd;
 127
 128         unsigned long           flags;
 129
 130         /* fallback stuff */
 131         struct crypto_shash     *fallback;
 132
 133         struct omap_sham_hmac_ctx base[0];
 134 };
 135
 136 #define OMAP_SHAM_QUEUE_LENGTH  1
 137
 138 struct omap_sham_dev {
 139         struct list_head        list;
 140         unsigned long           phys_base;
 141         struct device           *dev;
 142         void __iomem            *io_base;
 143         int                     irq;
 144         struct clk              *iclk;
 145         spinlock_t              lock;
 146         int                     err;
 147         int                     dma;
 148         int                     dma_lch;
 149         struct tasklet_struct   done_task;
 150
 151         unsigned long           flags;
 152         struct crypto_queue     queue;
 153         struct ahash_request    *req;
 154 };
 155
 156 struct omap_sham_drv {
 157         struct list_head        dev_list;
 158         spinlock_t              lock;
 159         unsigned long           flags;
 160 };
 161
 162 static struct omap_sham_drv sham = {
 163         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 164         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 165 };
 166
 167 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 168 {
 169         return __raw_readl(dd->io_base + offset);
 170 }
 171
 172 static inline void omap_sham_write(struct omap_sham_dev *dd,
 173                                         u32 offset, u32 value)
 174 {
 175         __raw_writel(value, dd->io_base + offset);
 176 }
 177
 178 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 179                                         u32 value, u32 mask)
 180 {
 181         u32 val;
 182
 183         val = omap_sham_read(dd, address);
 184         val &= ~mask;
 185         val |= value;
 186         omap_sham_write(dd, address, val);
 187 }
 188
 189 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 190 {
 191         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 192
 193         while (!(omap_sham_read(dd, offset) & bit)) {
 194                 if (time_is_before_jiffies(timeout))
 195                         return -ETIMEDOUT;
 196         }
 197
 198         return 0;
 199 }
 200
 201 static void omap_sham_copy_hash(struct ahash_request *req, int out)
 202 {
 203         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 204         u32 *hash = (u32 *)ctx->digest;
 205         int i;
 206
 207         /* MD5 is almost unused. So copy sha1 size to reduce code */
 208         for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++) {
 209                 if (out)
 210                         hash[i] = omap_sham_read(ctx->dd,
 211                                                 SHA_REG_DIGEST(i));
 212                 else
 213                         omap_sham_write(ctx->dd,
 214                                         SHA_REG_DIGEST(i), hash[i]);
 215         }
 216 }
 217
 218 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 219 {
 220         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 221         u32 *in = (u32 *)ctx->digest;
 222         u32 *hash = (u32 *)req->result;
 223         int i;
 224
 225         if (!hash)
 226                 return;
 227
 228         if (likely(ctx->flags & BIT(FLAGS_SHA1))) {
 229                 /* SHA1 results are in big endian */
 230                 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
 231                         hash[i] = be32_to_cpu(in[i]);
 232         } else {
 233                 /* MD5 results are in little endian */
 234                 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
 235                         hash[i] = le32_to_cpu(in[i]);
 236         }
 237 }
 238
 239 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 240 {
 241         clk_enable(dd->iclk);
 242
 243         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 244                 omap_sham_write_mask(dd, SHA_REG_MASK,
 245                         SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
 246
 247                 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
 248                                         SHA_REG_SYSSTATUS_RESETDONE))
 249                         return -ETIMEDOUT;
 250
 251                 set_bit(FLAGS_INIT, &dd->flags);
 252                 dd->err = 0;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static void omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
 259                                  int final, int dma)
 260 {
 261         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 262         u32 val = length << 5, mask;
 263
 264         if (likely(ctx->digcnt))
 265                 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
 266
 267         omap_sham_write_mask(dd, SHA_REG_MASK,
 268                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 269                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 270         /*
 271          * Setting ALGO_CONST only for the first iteration
 272          * and CLOSE_HASH only for the last one.
 273          */
 274         if (ctx->flags & BIT(FLAGS_SHA1))
 275                 val |= SHA_REG_CTRL_ALGO;
 276         if (!ctx->digcnt)
 277                 val |= SHA_REG_CTRL_ALGO_CONST;
 278         if (final)
 279                 val |= SHA_REG_CTRL_CLOSE_HASH;
 280
 281         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 282                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 283
 284         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 285 }
 286
 287 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 288                               size_t length, int final)
 289 {
 290         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 291         int count, len32;
 292         const u32 *buffer = (const u32 *)buf;
 293
 294         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 295                                                 ctx->digcnt, length, final);
 296
 297         omap_sham_write_ctrl(dd, length, final, 0);
 298
 299         /* should be non-zero before next lines to disable clocks later */
 300         ctx->digcnt += length;
 301
 302         if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
 303                 return -ETIMEDOUT;
 304
 305         if (final)
 306                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 307
 308         set_bit(FLAGS_CPU, &dd->flags);
 309
 310         len32 = DIV_ROUND_UP(length, sizeof(u32));
 311
 312         for (count = 0; count < len32; count++)
 313                 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
 314
 315         return -EINPROGRESS;
 316 }
 317
 318 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 319                               size_t length, int final)
 320 {
 321         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 322         int len32;
 323
 324         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 325                                                 ctx->digcnt, length, final);
 326
 327         len32 = DIV_ROUND_UP(length, sizeof(u32));
 328
 329         omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
 330                         1, OMAP_DMA_SYNC_PACKET, dd->dma,
 331                                 OMAP_DMA_DST_SYNC_PREFETCH);
 332
 333         omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
 334                                 dma_addr, 0, 0);
 335
 336         omap_sham_write_ctrl(dd, length, final, 1);
 337
 338         ctx->digcnt += length;
 339
 340         if (final)
 341                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 342
 343         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 344
 345         omap_start_dma(dd->dma_lch);
 346
 347         return -EINPROGRESS;
 348 }
 349
 350 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 351                                 const u8 *data, size_t length)
 352 {
 353         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 354
 355         count = min(count, ctx->total);
 356         if (count <= 0)
 357                 return 0;
 358         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 359         ctx->bufcnt += count;
 360
 361         return count;
 362 }
 363
 364 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 365 {
 366         size_t count;
 367
 368         while (ctx->sg) {
 369                 count = omap_sham_append_buffer(ctx,
 370                                 sg_virt(ctx->sg) + ctx->offset,
 371                                 ctx->sg->length - ctx->offset);
 372                 if (!count)
 373                         break;
 374                 ctx->offset += count;
 375                 ctx->total -= count;
 376                 if (ctx->offset == ctx->sg->length) {
 377                         ctx->sg = sg_next(ctx->sg);
 378                         if (ctx->sg)
 379                                 ctx->offset = 0;
 380                         else
 381                                 ctx->total = 0;
 382                 }
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 389                                         struct omap_sham_reqctx *ctx,
 390                                         size_t length, int final)
 391 {
 392         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 393                                        DMA_TO_DEVICE);
 394         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 395                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 396                 return -EINVAL;
 397         }
 398
 399         ctx->flags &= ~BIT(FLAGS_SG);
 400
 401         /* next call does not fail... so no unmap in the case of error */
 402         return omap_sham_xmit_dma(dd, ctx->dma_addr, length, final);
 403 }
 404
 405 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 406 {
 407         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 408         unsigned int final;
 409         size_t count;
 410
 411         omap_sham_append_sg(ctx);
 412
 413         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 414
 415         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 416                                          ctx->bufcnt, ctx->digcnt, final);
 417
 418         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 419                 count = ctx->bufcnt;
 420                 ctx->bufcnt = 0;
 421                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* Start address alignment */
 428 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 429 /* SHA1 block size alignment */
 430 #define SG_SA(sg)       (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE))
 431
 432 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 433 {
 434         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 435         unsigned int length, final, tail;
 436         struct scatterlist *sg;
 437
 438         if (!ctx->total)
 439                 return 0;
 440
 441         if (ctx->bufcnt || ctx->offset)
 442                 return omap_sham_update_dma_slow(dd);
 443
 444         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 445                         ctx->digcnt, ctx->bufcnt, ctx->total);
 446
 447         sg = ctx->sg;
 448
 449         if (!SG_AA(sg))
 450                 return omap_sham_update_dma_slow(dd);
 451
 452         if (!sg_is_last(sg) && !SG_SA(sg))
 453                 /* size is not SHA1_BLOCK_SIZE aligned */
 454                 return omap_sham_update_dma_slow(dd);
 455
 456         length = min(ctx->total, sg->length);
 457
 458         if (sg_is_last(sg)) {
 459                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 460                         /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */
 461                         tail = length & (SHA1_MD5_BLOCK_SIZE - 1);
 462                         /* without finup() we need one block to close hash */
 463                         if (!tail)
 464                                 tail = SHA1_MD5_BLOCK_SIZE;
 465                         length -= tail;
 466                 }
 467         }
 468
 469         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 470                 dev_err(dd->dev, "dma_map_sg  error\n");
 471                 return -EINVAL;
 472         }
 473
 474         ctx->flags |= BIT(FLAGS_SG);
 475
 476         ctx->total -= length;
 477         ctx->offset = length; /* offset where to start slow */
 478
 479         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 480
 481         /* next call does not fail... so no unmap in the case of error */
 482         return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final);
 483 }
 484
 485 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 486 {
 487         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 488         int bufcnt;
 489
 490         omap_sham_append_sg(ctx);
 491         bufcnt = ctx->bufcnt;
 492         ctx->bufcnt = 0;
 493
 494         return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
 495 }
 496
 497 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 498 {
 499         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 500
 501         omap_stop_dma(dd->dma_lch);
 502         if (ctx->flags & BIT(FLAGS_SG)) {
 503                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 504                 if (ctx->sg->length == ctx->offset) {
 505                         ctx->sg = sg_next(ctx->sg);
 506                         if (ctx->sg)
 507                                 ctx->offset = 0;
 508                 }
 509         } else {
 510                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 511                                  DMA_TO_DEVICE);
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int omap_sham_init(struct ahash_request *req)
 518 {
 519         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 520         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 521         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 522         struct omap_sham_dev *dd = NULL, *tmp;
 523
 524         spin_lock_bh(&sham.lock);
 525         if (!tctx->dd) {
 526                 list_for_each_entry(tmp, &sham.dev_list, list) {
 527                         dd = tmp;
 528                         break;
 529                 }
 530                 tctx->dd = dd;
 531         } else {
 532                 dd = tctx->dd;
 533         }
 534         spin_unlock_bh(&sham.lock);
 535
 536         ctx->dd = dd;
 537
 538         ctx->flags = 0;
 539
 540         dev_dbg(dd->dev, "init: digest size: %d\n",
 541                 crypto_ahash_digestsize(tfm));
 542
 543         if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
 544                 ctx->flags |= BIT(FLAGS_SHA1);
 545
 546         ctx->bufcnt = 0;
 547         ctx->digcnt = 0;
 548         ctx->buflen = BUFLEN;
 549
 550         if (tctx->flags & BIT(FLAGS_HMAC)) {
 551                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 552
 553                 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
 554                 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
 555                 ctx->flags |= BIT(FLAGS_HMAC);
 556         }
 557
 558         return 0;
 559
 560 }
 561
 562 static int omap_sham_update_req(struct omap_sham_dev *dd)
 563 {
 564         struct ahash_request *req = dd->req;
 565         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 566         int err;
 567
 568         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 569                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 570
 571         if (ctx->flags & BIT(FLAGS_CPU))
 572                 err = omap_sham_update_cpu(dd);
 573         else
 574                 err = omap_sham_update_dma_start(dd);
 575
 576         /* wait for dma completion before can take more data */
 577         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 578
 579         return err;
 580 }
 581
 582 static int omap_sham_final_req(struct omap_sham_dev *dd)
 583 {
 584         struct ahash_request *req = dd->req;
 585         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 586         int err = 0, use_dma = 1;
 587
 588         if (ctx->bufcnt <= 64)
 589                 /* faster to handle last block with cpu */
 590                 use_dma = 0;
 591
 592         if (use_dma)
 593                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 594         else
 595                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 596
 597         ctx->bufcnt = 0;
 598
 599         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 600
 601         return err;
 602 }
 603
 604 static int omap_sham_finish_hmac(struct ahash_request *req)
 605 {
 606         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 607         struct omap_sham_hmac_ctx *bctx = tctx->base;
 608         int bs = crypto_shash_blocksize(bctx->shash);
 609         int ds = crypto_shash_digestsize(bctx->shash);
 610         struct {
 611                 struct shash_desc shash;
 612                 char ctx[crypto_shash_descsize(bctx->shash)];
 613         } desc;
 614
 615         desc.shash.tfm = bctx->shash;
 616         desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 617
 618         return crypto_shash_init(&desc.shash) ?:
 619                crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
 620                crypto_shash_finup(&desc.shash, req->result, ds, req->result);
 621 }
 622
 623 static int omap_sham_finish(struct ahash_request *req)
 624 {
 625         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 626         struct omap_sham_dev *dd = ctx->dd;
 627         int err = 0;
 628
 629         if (ctx->digcnt) {
 630                 omap_sham_copy_ready_hash(req);
 631                 if (ctx->flags & BIT(FLAGS_HMAC))
 632                         err = omap_sham_finish_hmac(req);
 633         }
 634
 635         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 636
 637         return err;
 638 }
 639
 640 static void omap_sham_finish_req(struct ahash_request *req, int err)
 641 {
 642         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 643         struct omap_sham_dev *dd = ctx->dd;
 644
 645         if (!err) {
 646                 omap_sham_copy_hash(req, 1);
 647                 if (test_bit(FLAGS_FINAL, &dd->flags))
 648                         err = omap_sham_finish(req);
 649         } else {
 650                 ctx->flags |= BIT(FLAGS_ERROR);
 651         }
 652
 653         clk_disable(dd->iclk);
 654         dd->flags &= ~BIT(FLAGS_BUSY);
 655
 656         if (req->base.complete)
 657                 req->base.complete(&req->base, err);
 658
 659         /* handle new request */
 660         tasklet_schedule(&dd->done_task);
 661 }
 662
 663 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
 664                                   struct ahash_request *req)
 665 {
 666         struct crypto_async_request *async_req, *backlog;
 667         struct omap_sham_reqctx *ctx;
 668         unsigned long flags;
 669         int err = 0, ret = 0;
 670
 671         spin_lock_irqsave(&dd->lock, flags);
 672         if (req)
 673                 ret = ahash_enqueue_request(&dd->queue, req);
 674         if (test_bit(FLAGS_BUSY, &dd->flags)) {
 675                 spin_unlock_irqrestore(&dd->lock, flags);
 676                 return ret;
 677         }
 678         backlog = crypto_get_backlog(&dd->queue);
 679         async_req = crypto_dequeue_request(&dd->queue);
 680         if (async_req)
 681                 set_bit(FLAGS_BUSY, &dd->flags);
 682         spin_unlock_irqrestore(&dd->lock, flags);
 683
 684         if (!async_req)
 685                 return ret;
 686
 687         if (backlog)
 688                 backlog->complete(backlog, -EINPROGRESS);
 689
 690         req = ahash_request_cast(async_req);
 691         dd->req = req;
 692         ctx = ahash_request_ctx(req);
 693
 694         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
 695                                                 ctx->op, req->nbytes);
 696
 697         err = omap_sham_hw_init(dd);
 698         if (err)
 699                 goto err1;
 700
 701         omap_set_dma_dest_params(dd->dma_lch, 0,
 702                         OMAP_DMA_AMODE_CONSTANT,
 703                         dd->phys_base + SHA_REG_DIN(0), 0, 16);
 704
 705         omap_set_dma_dest_burst_mode(dd->dma_lch,
 706                         OMAP_DMA_DATA_BURST_16);
 707
 708         omap_set_dma_src_burst_mode(dd->dma_lch,
 709                         OMAP_DMA_DATA_BURST_4);
 710
 711         if (ctx->digcnt)
 712                 /* request has changed - restore hash */
 713                 omap_sham_copy_hash(req, 0);
 714
 715         if (ctx->op == OP_UPDATE) {
 716                 err = omap_sham_update_req(dd);
 717                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
 718                         /* no final() after finup() */
 719                         err = omap_sham_final_req(dd);
 720         } else if (ctx->op == OP_FINAL) {
 721                 err = omap_sham_final_req(dd);
 722         }
 723 err1:
 724         if (err != -EINPROGRESS)
 725                 /* done_task will not finish it, so do it here */
 726                 omap_sham_finish_req(req, err);
 727
 728         dev_dbg(dd->dev, "exit, err: %d\n", err);
 729
 730         return ret;
 731 }
 732
 733 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
 734 {
 735         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 736         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 737         struct omap_sham_dev *dd = tctx->dd;
 738
 739         ctx->op = op;
 740
 741         return omap_sham_handle_queue(dd, req);
 742 }
 743
 744 static int omap_sham_update(struct ahash_request *req)
 745 {
 746         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 747
 748         if (!req->nbytes)
 749                 return 0;
 750
 751         ctx->total = req->nbytes;
 752         ctx->sg = req->src;
 753         ctx->offset = 0;
 754
 755         if (ctx->flags & BIT(FLAGS_FINUP)) {
 756                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
 757                         /*
 758                         * OMAP HW accel works only with buffers >= 9
 759                         * will switch to bypass in final()
 760                         * final has the same request and data
 761                         */
 762                         omap_sham_append_sg(ctx);
 763                         return 0;
 764                 } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) {
 765                         /*
 766                         * faster to use CPU for short transfers
 767                         */
 768                         ctx->flags |= BIT(FLAGS_CPU);
 769                 }
 770         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
 771                 omap_sham_append_sg(ctx);
 772                 return 0;
 773         }
 774
 775         return omap_sham_enqueue(req, OP_UPDATE);
 776 }
 777
 778 static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
 779                                   const u8 *data, unsigned int len, u8 *out)
 780 {
 781         struct {
 782                 struct shash_desc shash;
 783                 char ctx[crypto_shash_descsize(shash)];
 784         } desc;
 785
 786         desc.shash.tfm = shash;
 787         desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 788
 789         return crypto_shash_digest(&desc.shash, data, len, out);
 790 }
 791
 792 static int omap_sham_final_shash(struct ahash_request *req)
 793 {
 794         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 795         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 796
 797         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
 798                                       ctx->buffer, ctx->bufcnt, req->result);
 799 }
 800
 801 static int omap_sham_final(struct ahash_request *req)
 802 {
 803         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 804
 805         ctx->flags |= BIT(FLAGS_FINUP);
 806
 807         if (ctx->flags & BIT(FLAGS_ERROR))
 808                 return 0; /* uncompleted hash is not needed */
 809
 810         /* OMAP HW accel works only with buffers >= 9 */
 811         /* HMAC is always >= 9 because ipad == block size */
 812         if ((ctx->digcnt + ctx->bufcnt) < 9)
 813                 return omap_sham_final_shash(req);
 814         else if (ctx->bufcnt)
 815                 return omap_sham_enqueue(req, OP_FINAL);
 816
 817         /* copy ready hash (+ finalize hmac) */
 818         return omap_sham_finish(req);
 819 }
 820
 821 static int omap_sham_finup(struct ahash_request *req)
 822 {
 823         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 824         int err1, err2;
 825
 826         ctx->flags |= BIT(FLAGS_FINUP);
 827
 828         err1 = omap_sham_update(req);
 829         if (err1 == -EINPROGRESS || err1 == -EBUSY)
 830                 return err1;
 831         /*
 832          * final() has to be always called to cleanup resources
 833          * even if udpate() failed, except EINPROGRESS
 834          */
 835         err2 = omap_sham_final(req);
 836
 837         return err1 ?: err2;
 838 }
 839
 840 static int omap_sham_digest(struct ahash_request *req)
 841 {
 842         return omap_sham_init(req) ?: omap_sham_finup(req);
 843 }
 844
 845 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
 846                       unsigned int keylen)
 847 {
 848         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 849         struct omap_sham_hmac_ctx *bctx = tctx->base;
 850         int bs = crypto_shash_blocksize(bctx->shash);
 851         int ds = crypto_shash_digestsize(bctx->shash);
 852         int err, i;
 853         err = crypto_shash_setkey(tctx->fallback, key, keylen);
 854         if (err)
 855                 return err;
 856
 857         if (keylen > bs) {
 858                 err = omap_sham_shash_digest(bctx->shash,
 859                                 crypto_shash_get_flags(bctx->shash),
 860                                 key, keylen, bctx->ipad);
 861                 if (err)
 862                         return err;
 863                 keylen = ds;
 864         } else {
 865                 memcpy(bctx->ipad, key, keylen);
 866         }
 867
 868         memset(bctx->ipad + keylen, 0, bs - keylen);
 869         memcpy(bctx->opad, bctx->ipad, bs);
 870
 871         for (i = 0; i < bs; i++) {
 872                 bctx->ipad[i] ^= 0x36;
 873                 bctx->opad[i] ^= 0x5c;
 874         }
 875
 876         return err;
 877 }
 878
 879 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
 880 {
 881         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 882         const char *alg_name = crypto_tfm_alg_name(tfm);
 883
 884         /* Allocate a fallback and abort if it failed. */
 885         tctx->fallback = crypto_alloc_shash(alg_name, 0,
 886                                             CRYPTO_ALG_NEED_FALLBACK);
 887         if (IS_ERR(tctx->fallback)) {
 888                 pr_err("omap-sham: fallback driver '%s' "
 889                                 "could not be loaded.\n", alg_name);
 890                 return PTR_ERR(tctx->fallback);
 891         }
 892
 893         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 894                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
 895
 896         if (alg_base) {
 897                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 898                 tctx->flags |= BIT(FLAGS_HMAC);
 899                 bctx->shash = crypto_alloc_shash(alg_base, 0,
 900                                                 CRYPTO_ALG_NEED_FALLBACK);
 901                 if (IS_ERR(bctx->shash)) {
 902                         pr_err("omap-sham: base driver '%s' "
 903                                         "could not be loaded.\n", alg_base);
 904                         crypto_free_shash(tctx->fallback);
 905                         return PTR_ERR(bctx->shash);
 906                 }
 907
 908         }
 909
 910         return 0;
 911 }
 912
 913 static int omap_sham_cra_init(struct crypto_tfm *tfm)
 914 {
 915         return omap_sham_cra_init_alg(tfm, NULL);
 916 }
 917
 918 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
 919 {
 920         return omap_sham_cra_init_alg(tfm, "sha1");
 921 }
 922
 923 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
 924 {
 925         return omap_sham_cra_init_alg(tfm, "md5");
 926 }
 927
 928 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
 929 {
 930         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
 931
 932         crypto_free_shash(tctx->fallback);
 933         tctx->fallback = NULL;
 934
 935         if (tctx->flags & BIT(FLAGS_HMAC)) {
 936                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 937                 crypto_free_shash(bctx->shash);
 938         }
 939 }
 940
 941 static struct ahash_alg algs[] = {
 942 {
 943         .init           = omap_sham_init,
 944         .update         = omap_sham_update,
 945         .final          = omap_sham_final,
 946         .finup          = omap_sham_finup,
 947         .digest         = omap_sham_digest,
 948         .halg.digestsize        = SHA1_DIGEST_SIZE,
 949         .halg.base      = {
 950                 .cra_name               = "sha1",
 951                 .cra_driver_name        = "omap-sha1",
 952                 .cra_priority           = 100,
 953                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 954                                                 CRYPTO_ALG_ASYNC |
 955                                                 CRYPTO_ALG_NEED_FALLBACK,
 956                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 957                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 958                 .cra_alignmask          = 0,
 959                 .cra_module             = THIS_MODULE,
 960                 .cra_init               = omap_sham_cra_init,
 961                 .cra_exit               = omap_sham_cra_exit,
 962         }
 963 },
 964 {
 965         .init           = omap_sham_init,
 966         .update         = omap_sham_update,
 967         .final          = omap_sham_final,
 968         .finup          = omap_sham_finup,
 969         .digest         = omap_sham_digest,
 970         .halg.digestsize        = MD5_DIGEST_SIZE,
 971         .halg.base      = {
 972                 .cra_name               = "md5",
 973                 .cra_driver_name        = "omap-md5",
 974                 .cra_priority           = 100,
 975                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 976                                                 CRYPTO_ALG_ASYNC |
 977                                                 CRYPTO_ALG_NEED_FALLBACK,
 978                 .cra_blocksize          = SHA1_BLOCK_SIZE,
 979                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
 980                 .cra_alignmask          = OMAP_ALIGN_MASK,
 981                 .cra_module             = THIS_MODULE,
 982                 .cra_init               = omap_sham_cra_init,
 983                 .cra_exit               = omap_sham_cra_exit,
 984         }
 985 },
 986 {
 987         .init           = omap_sham_init,
 988         .update         = omap_sham_update,
 989         .final          = omap_sham_final,
 990         .finup          = omap_sham_finup,
 991         .digest         = omap_sham_digest,
 992         .setkey         = omap_sham_setkey,
 993         .halg.digestsize        = SHA1_DIGEST_SIZE,
 994         .halg.base      = {
 995                 .cra_name               = "hmac(sha1)",
 996                 .cra_driver_name        = "omap-hmac-sha1",
 997                 .cra_priority           = 100,
 998                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
 999                                                 CRYPTO_ALG_ASYNC |
1000                                                 CRYPTO_ALG_NEED_FALLBACK,
1001                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1002                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1003                                         sizeof(struct omap_sham_hmac_ctx),
1004                 .cra_alignmask          = OMAP_ALIGN_MASK,
1005                 .cra_module             = THIS_MODULE,
1006                 .cra_init               = omap_sham_cra_sha1_init,
1007                 .cra_exit               = omap_sham_cra_exit,
1008         }
1009 },
1010 {
1011         .init           = omap_sham_init,
1012         .update         = omap_sham_update,
1013         .final          = omap_sham_final,
1014         .finup          = omap_sham_finup,
1015         .digest         = omap_sham_digest,
1016         .setkey         = omap_sham_setkey,
1017         .halg.digestsize        = MD5_DIGEST_SIZE,
1018         .halg.base      = {
1019                 .cra_name               = "hmac(md5)",
1020                 .cra_driver_name        = "omap-hmac-md5",
1021                 .cra_priority           = 100,
1022                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1023                                                 CRYPTO_ALG_ASYNC |
1024                                                 CRYPTO_ALG_NEED_FALLBACK,
1025                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1026                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1027                                         sizeof(struct omap_sham_hmac_ctx),
1028                 .cra_alignmask          = OMAP_ALIGN_MASK,
1029                 .cra_module             = THIS_MODULE,
1030                 .cra_init               = omap_sham_cra_md5_init,
1031                 .cra_exit               = omap_sham_cra_exit,
1032         }
1033 }
1034 };
1035
1036 static void omap_sham_done_task(unsigned long data)
1037 {
1038         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1039         int err = 0;
1040
1041         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1042                 omap_sham_handle_queue(dd, NULL);
1043                 return;
1044         }
1045
1046         if (test_bit(FLAGS_CPU, &dd->flags)) {
1047                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1048                         goto finish;
1049         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1050                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1051                         omap_sham_update_dma_stop(dd);
1052                         if (dd->err) {
1053                                 err = dd->err;
1054                                 goto finish;
1055                         }
1056                 }
1057                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1058                         /* hash or semi-hash ready */
1059                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1060                         err = omap_sham_update_dma_start(dd);
1061                         if (err != -EINPROGRESS)
1062                                 goto finish;
1063                 }
1064         }
1065
1066         return;
1067
1068 finish:
1069         dev_dbg(dd->dev, "update done: err: %d\n", err);
1070         /* finish curent request */
1071         omap_sham_finish_req(dd->req, err);
1072 }
1073
1074 static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1075 {
1076         struct omap_sham_dev *dd = dev_id;
1077
1078         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1079                 /* final -> allow device to go to power-saving mode */
1080                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1081
1082         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1083                                  SHA_REG_CTRL_OUTPUT_READY);
1084         omap_sham_read(dd, SHA_REG_CTRL);
1085
1086         set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1087         dd->err = 0;
1088         tasklet_schedule(&dd->done_task);
1089
1090         return IRQ_HANDLED;
1091 }
1092
1093 static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1094 {
1095         struct omap_sham_dev *dd = data;
1096
1097         if (ch_status != OMAP_DMA_BLOCK_IRQ) {
1098                 pr_err("omap-sham DMA error status: 0x%hx\n", ch_status);
1099                 dd->err = -EIO;
1100                 clear_bit(FLAGS_INIT, &dd->flags);/* request to re-initialize */
1101         }
1102
1103         set_bit(FLAGS_DMA_READY, &dd->flags);
1104         tasklet_schedule(&dd->done_task);
1105 }
1106
1107 static int omap_sham_dma_init(struct omap_sham_dev *dd)
1108 {
1109         int err;
1110
1111         dd->dma_lch = -1;
1112
1113         err = omap_request_dma(dd->dma, dev_name(dd->dev),
1114                         omap_sham_dma_callback, dd, &dd->dma_lch);
1115         if (err) {
1116                 dev_err(dd->dev, "Unable to request DMA channel\n");
1117                 return err;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1124 {
1125         if (dd->dma_lch >= 0) {
1126                 omap_free_dma(dd->dma_lch);
1127                 dd->dma_lch = -1;
1128         }
1129 }
1130
1131 static int __devinit omap_sham_probe(struct platform_device *pdev)
1132 {
1133         struct omap_sham_dev *dd;
1134         struct device *dev = &pdev->dev;
1135         struct resource *res;
1136         int err, i, j;
1137
1138         dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1139         if (dd == NULL) {
1140                 dev_err(dev, "unable to alloc data struct.\n");
1141                 err = -ENOMEM;
1142                 goto data_err;
1143         }
1144         dd->dev = dev;
1145         platform_set_drvdata(pdev, dd);
1146
1147         INIT_LIST_HEAD(&dd->list);
1148         spin_lock_init(&dd->lock);
1149         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1150         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1151
1152         dd->irq = -1;
1153
1154         /* Get the base address */
1155         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1156         if (!res) {
1157                 dev_err(dev, "no MEM resource info\n");
1158                 err = -ENODEV;
1159                 goto res_err;
1160         }
1161         dd->phys_base = res->start;
1162
1163         /* Get the DMA */
1164         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1165         if (!res) {
1166                 dev_err(dev, "no DMA resource info\n");
1167                 err = -ENODEV;
1168                 goto res_err;
1169         }
1170         dd->dma = res->start;
1171
1172         /* Get the IRQ */
1173         dd->irq = platform_get_irq(pdev,  0);
1174         if (dd->irq < 0) {
1175                 dev_err(dev, "no IRQ resource info\n");
1176                 err = dd->irq;
1177                 goto res_err;
1178         }
1179
1180         err = request_irq(dd->irq, omap_sham_irq,
1181                         IRQF_TRIGGER_LOW, dev_name(dev), dd);
1182         if (err) {
1183                 dev_err(dev, "unable to request irq.\n");
1184                 goto res_err;
1185         }
1186
1187         err = omap_sham_dma_init(dd);
1188         if (err)
1189                 goto dma_err;
1190
1191         /* Initializing the clock */
1192         dd->iclk = clk_get(dev, "ick");
1193         if (IS_ERR(dd->iclk)) {
1194                 dev_err(dev, "clock intialization failed.\n");
1195                 err = PTR_ERR(dd->iclk);
1196                 goto clk_err;
1197         }
1198
1199         dd->io_base = ioremap(dd->phys_base, SZ_4K);
1200         if (!dd->io_base) {
1201                 dev_err(dev, "can't ioremap\n");
1202                 err = -ENOMEM;
1203                 goto io_err;
1204         }
1205
1206         clk_enable(dd->iclk);
1207         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1208                 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1209                 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1210         clk_disable(dd->iclk);
1211
1212         spin_lock(&sham.lock);
1213         list_add_tail(&dd->list, &sham.dev_list);
1214         spin_unlock(&sham.lock);
1215
1216         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1217                 err = crypto_register_ahash(&algs[i]);
1218                 if (err)
1219                         goto err_algs;
1220         }
1221
1222         return 0;
1223
1224 err_algs:
1225         for (j = 0; j < i; j++)
1226                 crypto_unregister_ahash(&algs[j]);
1227         iounmap(dd->io_base);
1228 io_err:
1229         clk_put(dd->iclk);
1230 clk_err:
1231         omap_sham_dma_cleanup(dd);
1232 dma_err:
1233         if (dd->irq >= 0)
1234                 free_irq(dd->irq, dd);
1235 res_err:
1236         kfree(dd);
1237         dd = NULL;
1238 data_err:
1239         dev_err(dev, "initialization failed.\n");
1240
1241         return err;
1242 }
1243
1244 static int __devexit omap_sham_remove(struct platform_device *pdev)
1245 {
1246         static struct omap_sham_dev *dd;
1247         int i;
1248
1249         dd = platform_get_drvdata(pdev);
1250         if (!dd)
1251                 return -ENODEV;
1252         spin_lock(&sham.lock);
1253         list_del(&dd->list);
1254         spin_unlock(&sham.lock);
1255         for (i = 0; i < ARRAY_SIZE(algs); i++)
1256                 crypto_unregister_ahash(&algs[i]);
1257         tasklet_kill(&dd->done_task);
1258         iounmap(dd->io_base);
1259         clk_put(dd->iclk);
1260         omap_sham_dma_cleanup(dd);
1261         if (dd->irq >= 0)
1262                 free_irq(dd->irq, dd);
1263         kfree(dd);
1264         dd = NULL;
1265
1266         return 0;
1267 }
1268
1269 static struct platform_driver omap_sham_driver = {
1270         .probe  = omap_sham_probe,
1271         .remove = omap_sham_remove,
1272         .driver = {
1273                 .name   = "omap-sham",
1274                 .owner  = THIS_MODULE,
1275         },
1276 };
1277
1278 static int __init omap_sham_mod_init(void)
1279 {
1280         pr_info("loading %s driver\n", "omap-sham");
1281
1282         if (!cpu_class_is_omap2() ||
1283                 (omap_type() != OMAP2_DEVICE_TYPE_SEC &&
1284                         omap_type() != OMAP2_DEVICE_TYPE_EMU)) {
1285                 pr_err("Unsupported cpu\n");
1286                 return -ENODEV;
1287         }
1288
1289         return platform_driver_register(&omap_sham_driver);
1290 }
1291
1292 static void __exit omap_sham_mod_exit(void)
1293 {
1294         platform_driver_unregister(&omap_sham_driver);
1295 }
1296
1297 module_init(omap_sham_mod_init);
1298 module_exit(omap_sham_mod_exit);
1299
1300 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1301 MODULE_LICENSE("GPL v2");
1302 MODULE_AUTHOR("Dmitry Kasatkin");