drivers/crypto/omap-des.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Support for OMAP DES and Triple DES HW acceleration.
   4  *
   5  * Copyright (c) 2013 Texas Instruments Incorporated
   6  * Author: Joel Fernandes <joelf@ti.com>
   7  */
   8
   9 #define pr_fmt(fmt) "%s: " fmt, __func__
  10
  11 #ifdef DEBUG
  12 #define prn(num) printk(#num "=%d\n", num)
  13 #define prx(num) printk(#num "=%x\n", num)
  14 #else
  15 #define prn(num) do { } while (0)
  16 #define prx(num)  do { } while (0)
  17 #endif
  18
  19 #include <crypto/engine.h>
  20 #include <crypto/internal/des.h>
  21 #include <crypto/internal/skcipher.h>
  22 #include <crypto/scatterwalk.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/err.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/of.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/scatterlist.h>
  35 #include <linux/string.h>
  36
  37 #include "omap-crypto.h"
  38
  39 #define DST_MAXBURST                    2
  40
  41 #define DES_BLOCK_WORDS         (DES_BLOCK_SIZE >> 2)
  42
  43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
  44
  45 #define DES_REG_KEY(dd, x)              ((dd)->pdata->key_ofs - \
  46                                                 ((x ^ 0x01) * 0x04))
  47
  48 #define DES_REG_IV(dd, x)               ((dd)->pdata->iv_ofs + ((x) * 0x04))
  49
  50 #define DES_REG_CTRL(dd)                ((dd)->pdata->ctrl_ofs)
  51 #define DES_REG_CTRL_CBC                BIT(4)
  52 #define DES_REG_CTRL_TDES               BIT(3)
  53 #define DES_REG_CTRL_DIRECTION          BIT(2)
  54 #define DES_REG_CTRL_INPUT_READY        BIT(1)
  55 #define DES_REG_CTRL_OUTPUT_READY       BIT(0)
  56
  57 #define DES_REG_DATA_N(dd, x)           ((dd)->pdata->data_ofs + ((x) * 0x04))
  58
  59 #define DES_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  60
  61 #define DES_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  62
  63 #define DES_REG_LENGTH_N(x)             (0x24 + ((x) * 0x04))
  64
  65 #define DES_REG_IRQ_STATUS(dd)         ((dd)->pdata->irq_status_ofs)
  66 #define DES_REG_IRQ_ENABLE(dd)         ((dd)->pdata->irq_enable_ofs)
  67 #define DES_REG_IRQ_DATA_IN            BIT(1)
  68 #define DES_REG_IRQ_DATA_OUT           BIT(2)
  69
  70 #define FLAGS_MODE_MASK         0x000f
  71 #define FLAGS_ENCRYPT           BIT(0)
  72 #define FLAGS_CBC               BIT(1)
  73 #define FLAGS_INIT              BIT(4)
  74 #define FLAGS_BUSY              BIT(6)
  75
  76 #define DEFAULT_AUTOSUSPEND_DELAY       1000
  77
  78 #define FLAGS_IN_DATA_ST_SHIFT  8
  79 #define FLAGS_OUT_DATA_ST_SHIFT 10
  80
  81 struct omap_des_ctx {
  82         struct omap_des_dev *dd;
  83
  84         int             keylen;
  85         __le32          key[(3 * DES_KEY_SIZE) / sizeof(u32)];
  86         unsigned long   flags;
  87 };
  88
  89 struct omap_des_reqctx {
  90         unsigned long mode;
  91 };
  92
  93 #define OMAP_DES_QUEUE_LENGTH   1
  94 #define OMAP_DES_CACHE_SIZE     0
  95
  96 struct omap_des_algs_info {
  97         struct skcipher_engine_alg      *algs_list;
  98         unsigned int                    size;
  99         unsigned int                    registered;
 100 };
 101
 102 struct omap_des_pdata {
 103         struct omap_des_algs_info       *algs_info;
 104         unsigned int    algs_info_size;
 105
 106         void            (*trigger)(struct omap_des_dev *dd, int length);
 107
 108         u32             key_ofs;
 109         u32             iv_ofs;
 110         u32             ctrl_ofs;
 111         u32             data_ofs;
 112         u32             rev_ofs;
 113         u32             mask_ofs;
 114         u32             irq_enable_ofs;
 115         u32             irq_status_ofs;
 116
 117         u32             dma_enable_in;
 118         u32             dma_enable_out;
 119         u32             dma_start;
 120
 121         u32             major_mask;
 122         u32             major_shift;
 123         u32             minor_mask;
 124         u32             minor_shift;
 125 };
 126
 127 struct omap_des_dev {
 128         struct list_head        list;
 129         unsigned long           phys_base;
 130         void __iomem            *io_base;
 131         struct omap_des_ctx     *ctx;
 132         struct device           *dev;
 133         unsigned long           flags;
 134         int                     err;
 135
 136         struct tasklet_struct   done_task;
 137
 138         struct skcipher_request *req;
 139         struct crypto_engine            *engine;
 140         /*
 141          * total is used by PIO mode for book keeping so introduce
 142          * variable total_save as need it to calc page_order
 143          */
 144         size_t                          total;
 145         size_t                          total_save;
 146
 147         struct scatterlist              *in_sg;
 148         struct scatterlist              *out_sg;
 149
 150         /* Buffers for copying for unaligned cases */
 151         struct scatterlist              in_sgl;
 152         struct scatterlist              out_sgl;
 153         struct scatterlist              *orig_out;
 154
 155         struct scatter_walk             in_walk;
 156         struct scatter_walk             out_walk;
 157         struct dma_chan         *dma_lch_in;
 158         struct dma_chan         *dma_lch_out;
 159         int                     in_sg_len;
 160         int                     out_sg_len;
 161         int                     pio_only;
 162         const struct omap_des_pdata     *pdata;
 163 };
 164
 165 /* keep registered devices data here */
 166 static LIST_HEAD(dev_list);
 167 static DEFINE_SPINLOCK(list_lock);
 168
 169 #ifdef DEBUG
 170 #define omap_des_read(dd, offset)                               \
 171         ({                                                              \
 172          int _read_ret;                                          \
 173          _read_ret = __raw_readl(dd->io_base + offset);          \
 174          pr_err("omap_des_read(" #offset "=%#x)= %#x\n",       \
 175                  offset, _read_ret);                            \
 176          _read_ret;                                              \
 177          })
 178 #else
 179 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
 180 {
 181         return __raw_readl(dd->io_base + offset);
 182 }
 183 #endif
 184
 185 #ifdef DEBUG
 186 #define omap_des_write(dd, offset, value)                               \
 187         do {                                                            \
 188                 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
 189                                 offset, value);                                \
 190                 __raw_writel(value, dd->io_base + offset);              \
 191         } while (0)
 192 #else
 193 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
 194                 u32 value)
 195 {
 196         __raw_writel(value, dd->io_base + offset);
 197 }
 198 #endif
 199
 200 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
 201                                         u32 value, u32 mask)
 202 {
 203         u32 val;
 204
 205         val = omap_des_read(dd, offset);
 206         val &= ~mask;
 207         val |= value;
 208         omap_des_write(dd, offset, val);
 209 }
 210
 211 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
 212                                         u32 *value, int count)
 213 {
 214         for (; count--; value++, offset += 4)
 215                 omap_des_write(dd, offset, *value);
 216 }
 217
 218 static int omap_des_hw_init(struct omap_des_dev *dd)
 219 {
 220         int err;
 221
 222         /*
 223          * clocks are enabled when request starts and disabled when finished.
 224          * It may be long delays between requests.
 225          * Device might go to off mode to save power.
 226          */
 227         err = pm_runtime_resume_and_get(dd->dev);
 228         if (err < 0) {
 229                 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
 230                 return err;
 231         }
 232
 233         if (!(dd->flags & FLAGS_INIT)) {
 234                 dd->flags |= FLAGS_INIT;
 235                 dd->err = 0;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int omap_des_write_ctrl(struct omap_des_dev *dd)
 242 {
 243         unsigned int key32;
 244         int i, err;
 245         u32 val = 0, mask = 0;
 246
 247         err = omap_des_hw_init(dd);
 248         if (err)
 249                 return err;
 250
 251         key32 = dd->ctx->keylen / sizeof(u32);
 252
 253         /* it seems a key should always be set even if it has not changed */
 254         for (i = 0; i < key32; i++) {
 255                 omap_des_write(dd, DES_REG_KEY(dd, i),
 256                                __le32_to_cpu(dd->ctx->key[i]));
 257         }
 258
 259         if ((dd->flags & FLAGS_CBC) && dd->req->iv)
 260                 omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
 261
 262         if (dd->flags & FLAGS_CBC)
 263                 val |= DES_REG_CTRL_CBC;
 264         if (dd->flags & FLAGS_ENCRYPT)
 265                 val |= DES_REG_CTRL_DIRECTION;
 266         if (key32 == 6)
 267                 val |= DES_REG_CTRL_TDES;
 268
 269         mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
 270
 271         omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
 272
 273         return 0;
 274 }
 275
 276 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
 277 {
 278         u32 mask, val;
 279
 280         omap_des_write(dd, DES_REG_LENGTH_N(0), length);
 281
 282         val = dd->pdata->dma_start;
 283
 284         if (dd->dma_lch_out != NULL)
 285                 val |= dd->pdata->dma_enable_out;
 286         if (dd->dma_lch_in != NULL)
 287                 val |= dd->pdata->dma_enable_in;
 288
 289         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 290                dd->pdata->dma_start;
 291
 292         omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
 293 }
 294
 295 static void omap_des_dma_stop(struct omap_des_dev *dd)
 296 {
 297         u32 mask;
 298
 299         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 300                dd->pdata->dma_start;
 301
 302         omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
 303 }
 304
 305 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
 306 {
 307         struct omap_des_dev *dd = NULL, *tmp;
 308
 309         spin_lock_bh(&list_lock);
 310         if (!ctx->dd) {
 311                 list_for_each_entry(tmp, &dev_list, list) {
 312                         /* FIXME: take fist available des core */
 313                         dd = tmp;
 314                         break;
 315                 }
 316                 ctx->dd = dd;
 317         } else {
 318                 /* already found before */
 319                 dd = ctx->dd;
 320         }
 321         spin_unlock_bh(&list_lock);
 322
 323         return dd;
 324 }
 325
 326 static void omap_des_dma_out_callback(void *data)
 327 {
 328         struct omap_des_dev *dd = data;
 329
 330         /* dma_lch_out - completed */
 331         tasklet_schedule(&dd->done_task);
 332 }
 333
 334 static int omap_des_dma_init(struct omap_des_dev *dd)
 335 {
 336         int err;
 337
 338         dd->dma_lch_out = NULL;
 339         dd->dma_lch_in = NULL;
 340
 341         dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 342         if (IS_ERR(dd->dma_lch_in)) {
 343                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 344                 return PTR_ERR(dd->dma_lch_in);
 345         }
 346
 347         dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 348         if (IS_ERR(dd->dma_lch_out)) {
 349                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 350                 err = PTR_ERR(dd->dma_lch_out);
 351                 goto err_dma_out;
 352         }
 353
 354         return 0;
 355
 356 err_dma_out:
 357         dma_release_channel(dd->dma_lch_in);
 358
 359         return err;
 360 }
 361
 362 static void omap_des_dma_cleanup(struct omap_des_dev *dd)
 363 {
 364         if (dd->pio_only)
 365                 return;
 366
 367         dma_release_channel(dd->dma_lch_out);
 368         dma_release_channel(dd->dma_lch_in);
 369 }
 370
 371 static int omap_des_crypt_dma(struct crypto_tfm *tfm,
 372                 struct scatterlist *in_sg, struct scatterlist *out_sg,
 373                 int in_sg_len, int out_sg_len)
 374 {
 375         struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
 376         struct omap_des_dev *dd = ctx->dd;
 377         struct dma_async_tx_descriptor *tx_in, *tx_out;
 378         struct dma_slave_config cfg;
 379         int ret;
 380
 381         if (dd->pio_only) {
 382                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 383                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 384
 385                 /* Enable DATAIN interrupt and let it take
 386                    care of the rest */
 387                 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
 388                 return 0;
 389         }
 390
 391         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 392
 393         memset(&cfg, 0, sizeof(cfg));
 394
 395         cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
 396         cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
 397         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 398         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 399         cfg.src_maxburst = DST_MAXBURST;
 400         cfg.dst_maxburst = DST_MAXBURST;
 401
 402         /* IN */
 403         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 404         if (ret) {
 405                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 406                         ret);
 407                 return ret;
 408         }
 409
 410         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 411                                         DMA_MEM_TO_DEV,
 412                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 413         if (!tx_in) {
 414                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 415                 return -EINVAL;
 416         }
 417
 418         /* No callback necessary */
 419         tx_in->callback_param = dd;
 420
 421         /* OUT */
 422         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 423         if (ret) {
 424                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 425                         ret);
 426                 return ret;
 427         }
 428
 429         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 430                                         DMA_DEV_TO_MEM,
 431                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 432         if (!tx_out) {
 433                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 434                 return -EINVAL;
 435         }
 436
 437         tx_out->callback = omap_des_dma_out_callback;
 438         tx_out->callback_param = dd;
 439
 440         dmaengine_submit(tx_in);
 441         dmaengine_submit(tx_out);
 442
 443         dma_async_issue_pending(dd->dma_lch_in);
 444         dma_async_issue_pending(dd->dma_lch_out);
 445
 446         /* start DMA */
 447         dd->pdata->trigger(dd, dd->total);
 448
 449         return 0;
 450 }
 451
 452 static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
 453 {
 454         struct crypto_tfm *tfm = crypto_skcipher_tfm(
 455                                         crypto_skcipher_reqtfm(dd->req));
 456         int err;
 457
 458         pr_debug("total: %zd\n", dd->total);
 459
 460         if (!dd->pio_only) {
 461                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 462                                  DMA_TO_DEVICE);
 463                 if (!err) {
 464                         dev_err(dd->dev, "dma_map_sg() error\n");
 465                         return -EINVAL;
 466                 }
 467
 468                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 469                                  DMA_FROM_DEVICE);
 470                 if (!err) {
 471                         dev_err(dd->dev, "dma_map_sg() error\n");
 472                         return -EINVAL;
 473                 }
 474         }
 475
 476         err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
 477                                  dd->out_sg_len);
 478         if (err && !dd->pio_only) {
 479                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 480                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 481                              DMA_FROM_DEVICE);
 482         }
 483
 484         return err;
 485 }
 486
 487 static void omap_des_finish_req(struct omap_des_dev *dd, int err)
 488 {
 489         struct skcipher_request *req = dd->req;
 490
 491         pr_debug("err: %d\n", err);
 492
 493         crypto_finalize_skcipher_request(dd->engine, req, err);
 494
 495         pm_runtime_mark_last_busy(dd->dev);
 496         pm_runtime_put_autosuspend(dd->dev);
 497 }
 498
 499 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
 500 {
 501         pr_debug("total: %zd\n", dd->total);
 502
 503         omap_des_dma_stop(dd);
 504
 505         dmaengine_terminate_all(dd->dma_lch_in);
 506         dmaengine_terminate_all(dd->dma_lch_out);
 507
 508         return 0;
 509 }
 510
 511 static int omap_des_handle_queue(struct omap_des_dev *dd,
 512                                  struct skcipher_request *req)
 513 {
 514         if (req)
 515                 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
 516
 517         return 0;
 518 }
 519
 520 static int omap_des_prepare_req(struct skcipher_request *req,
 521                                 struct omap_des_dev *dd)
 522 {
 523         struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 524                         crypto_skcipher_reqtfm(req));
 525         struct omap_des_reqctx *rctx;
 526         int ret;
 527         u16 flags;
 528
 529         /* assign new request to device */
 530         dd->req = req;
 531         dd->total = req->cryptlen;
 532         dd->total_save = req->cryptlen;
 533         dd->in_sg = req->src;
 534         dd->out_sg = req->dst;
 535         dd->orig_out = req->dst;
 536
 537         flags = OMAP_CRYPTO_COPY_DATA;
 538         if (req->src == req->dst)
 539                 flags |= OMAP_CRYPTO_FORCE_COPY;
 540
 541         ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
 542                                    &dd->in_sgl, flags,
 543                                    FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
 544         if (ret)
 545                 return ret;
 546
 547         ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
 548                                    &dd->out_sgl, 0,
 549                                    FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
 550         if (ret)
 551                 return ret;
 552
 553         dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 554         if (dd->in_sg_len < 0)
 555                 return dd->in_sg_len;
 556
 557         dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 558         if (dd->out_sg_len < 0)
 559                 return dd->out_sg_len;
 560
 561         rctx = skcipher_request_ctx(req);
 562         ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
 563         rctx->mode &= FLAGS_MODE_MASK;
 564         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 565
 566         dd->ctx = ctx;
 567         ctx->dd = dd;
 568
 569         return omap_des_write_ctrl(dd);
 570 }
 571
 572 static int omap_des_crypt_req(struct crypto_engine *engine,
 573                               void *areq)
 574 {
 575         struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
 576         struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 577                         crypto_skcipher_reqtfm(req));
 578         struct omap_des_dev *dd = omap_des_find_dev(ctx);
 579
 580         if (!dd)
 581                 return -ENODEV;
 582
 583         return omap_des_prepare_req(req, dd) ?:
 584                omap_des_crypt_dma_start(dd);
 585 }
 586
 587 static void omap_des_done_task(unsigned long data)
 588 {
 589         struct omap_des_dev *dd = (struct omap_des_dev *)data;
 590         int i;
 591
 592         pr_debug("enter done_task\n");
 593
 594         if (!dd->pio_only) {
 595                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 596                                        DMA_FROM_DEVICE);
 597                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 598                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 599                              DMA_FROM_DEVICE);
 600                 omap_des_crypt_dma_stop(dd);
 601         }
 602
 603         omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
 604                             FLAGS_IN_DATA_ST_SHIFT, dd->flags);
 605
 606         omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
 607                             FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
 608
 609         if ((dd->flags & FLAGS_CBC) && dd->req->iv)
 610                 for (i = 0; i < 2; i++)
 611                         ((u32 *)dd->req->iv)[i] =
 612                                 omap_des_read(dd, DES_REG_IV(dd, i));
 613
 614         omap_des_finish_req(dd, 0);
 615
 616         pr_debug("exit\n");
 617 }
 618
 619 static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
 620 {
 621         struct omap_des_ctx *ctx = crypto_skcipher_ctx(
 622                         crypto_skcipher_reqtfm(req));
 623         struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
 624         struct omap_des_dev *dd;
 625
 626         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
 627                  !!(mode & FLAGS_ENCRYPT),
 628                  !!(mode & FLAGS_CBC));
 629
 630         if (!req->cryptlen)
 631                 return 0;
 632
 633         if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
 634                 return -EINVAL;
 635
 636         dd = omap_des_find_dev(ctx);
 637         if (!dd)
 638                 return -ENODEV;
 639
 640         rctx->mode = mode;
 641
 642         return omap_des_handle_queue(dd, req);
 643 }
 644
 645 /* ********************** ALG API ************************************ */
 646
 647 static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
 648                            unsigned int keylen)
 649 {
 650         struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
 651         int err;
 652
 653         pr_debug("enter, keylen: %d\n", keylen);
 654
 655         err = verify_skcipher_des_key(cipher, key);
 656         if (err)
 657                 return err;
 658
 659         memcpy(ctx->key, key, keylen);
 660         ctx->keylen = keylen;
 661
 662         return 0;
 663 }
 664
 665 static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
 666                             unsigned int keylen)
 667 {
 668         struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
 669         int err;
 670
 671         pr_debug("enter, keylen: %d\n", keylen);
 672
 673         err = verify_skcipher_des3_key(cipher, key);
 674         if (err)
 675                 return err;
 676
 677         memcpy(ctx->key, key, keylen);
 678         ctx->keylen = keylen;
 679
 680         return 0;
 681 }
 682
 683 static int omap_des_ecb_encrypt(struct skcipher_request *req)
 684 {
 685         return omap_des_crypt(req, FLAGS_ENCRYPT);
 686 }
 687
 688 static int omap_des_ecb_decrypt(struct skcipher_request *req)
 689 {
 690         return omap_des_crypt(req, 0);
 691 }
 692
 693 static int omap_des_cbc_encrypt(struct skcipher_request *req)
 694 {
 695         return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 696 }
 697
 698 static int omap_des_cbc_decrypt(struct skcipher_request *req)
 699 {
 700         return omap_des_crypt(req, FLAGS_CBC);
 701 }
 702
 703 static int omap_des_init_tfm(struct crypto_skcipher *tfm)
 704 {
 705         pr_debug("enter\n");
 706
 707         crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
 708
 709         return 0;
 710 }
 711
 712 /* ********************** ALGS ************************************ */
 713
 714 static struct skcipher_engine_alg algs_ecb_cbc[] = {
 715 {
 716         .base = {
 717                 .base.cra_name          = "ecb(des)",
 718                 .base.cra_driver_name   = "ecb-des-omap",
 719                 .base.cra_priority      = 300,
 720                 .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 721                                           CRYPTO_ALG_ASYNC,
 722                 .base.cra_blocksize     = DES_BLOCK_SIZE,
 723                 .base.cra_ctxsize       = sizeof(struct omap_des_ctx),
 724                 .base.cra_module        = THIS_MODULE,
 725
 726                 .min_keysize            = DES_KEY_SIZE,
 727                 .max_keysize            = DES_KEY_SIZE,
 728                 .setkey                 = omap_des_setkey,
 729                 .encrypt                = omap_des_ecb_encrypt,
 730                 .decrypt                = omap_des_ecb_decrypt,
 731                 .init                   = omap_des_init_tfm,
 732         },
 733         .op.do_one_request = omap_des_crypt_req,
 734 },
 735 {
 736         .base = {
 737                 .base.cra_name          = "cbc(des)",
 738                 .base.cra_driver_name   = "cbc-des-omap",
 739                 .base.cra_priority      = 300,
 740                 .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 741                                           CRYPTO_ALG_ASYNC,
 742                 .base.cra_blocksize     = DES_BLOCK_SIZE,
 743                 .base.cra_ctxsize       = sizeof(struct omap_des_ctx),
 744                 .base.cra_module        = THIS_MODULE,
 745
 746                 .min_keysize            = DES_KEY_SIZE,
 747                 .max_keysize            = DES_KEY_SIZE,
 748                 .ivsize                 = DES_BLOCK_SIZE,
 749                 .setkey                 = omap_des_setkey,
 750                 .encrypt                = omap_des_cbc_encrypt,
 751                 .decrypt                = omap_des_cbc_decrypt,
 752                 .init                   = omap_des_init_tfm,
 753         },
 754         .op.do_one_request = omap_des_crypt_req,
 755 },
 756 {
 757         .base = {
 758                 .base.cra_name          = "ecb(des3_ede)",
 759                 .base.cra_driver_name   = "ecb-des3-omap",
 760                 .base.cra_priority      = 300,
 761                 .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 762                                           CRYPTO_ALG_ASYNC,
 763                 .base.cra_blocksize     = DES3_EDE_BLOCK_SIZE,
 764                 .base.cra_ctxsize       = sizeof(struct omap_des_ctx),
 765                 .base.cra_module        = THIS_MODULE,
 766
 767                 .min_keysize            = DES3_EDE_KEY_SIZE,
 768                 .max_keysize            = DES3_EDE_KEY_SIZE,
 769                 .setkey                 = omap_des3_setkey,
 770                 .encrypt                = omap_des_ecb_encrypt,
 771                 .decrypt                = omap_des_ecb_decrypt,
 772                 .init                   = omap_des_init_tfm,
 773         },
 774         .op.do_one_request = omap_des_crypt_req,
 775 },
 776 {
 777         .base = {
 778                 .base.cra_name          = "cbc(des3_ede)",
 779                 .base.cra_driver_name   = "cbc-des3-omap",
 780                 .base.cra_priority      = 300,
 781                 .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 782                                           CRYPTO_ALG_ASYNC,
 783                 .base.cra_blocksize     = DES3_EDE_BLOCK_SIZE,
 784                 .base.cra_ctxsize       = sizeof(struct omap_des_ctx),
 785                 .base.cra_module        = THIS_MODULE,
 786
 787                 .min_keysize            = DES3_EDE_KEY_SIZE,
 788                 .max_keysize            = DES3_EDE_KEY_SIZE,
 789                 .ivsize                 = DES3_EDE_BLOCK_SIZE,
 790                 .setkey                 = omap_des3_setkey,
 791                 .encrypt                = omap_des_cbc_encrypt,
 792                 .decrypt                = omap_des_cbc_decrypt,
 793                 .init                   = omap_des_init_tfm,
 794         },
 795         .op.do_one_request = omap_des_crypt_req,
 796 }
 797 };
 798
 799 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
 800         {
 801                 .algs_list      = algs_ecb_cbc,
 802                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 803         },
 804 };
 805
 806 #ifdef CONFIG_OF
 807 static const struct omap_des_pdata omap_des_pdata_omap4 = {
 808         .algs_info      = omap_des_algs_info_ecb_cbc,
 809         .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
 810         .trigger        = omap_des_dma_trigger_omap4,
 811         .key_ofs        = 0x14,
 812         .iv_ofs         = 0x18,
 813         .ctrl_ofs       = 0x20,
 814         .data_ofs       = 0x28,
 815         .rev_ofs        = 0x30,
 816         .mask_ofs       = 0x34,
 817         .irq_status_ofs = 0x3c,
 818         .irq_enable_ofs = 0x40,
 819         .dma_enable_in  = BIT(5),
 820         .dma_enable_out = BIT(6),
 821         .major_mask     = 0x0700,
 822         .major_shift    = 8,
 823         .minor_mask     = 0x003f,
 824         .minor_shift    = 0,
 825 };
 826
 827 static irqreturn_t omap_des_irq(int irq, void *dev_id)
 828 {
 829         struct omap_des_dev *dd = dev_id;
 830         u32 status, i;
 831         u32 *src, *dst;
 832
 833         status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
 834         if (status & DES_REG_IRQ_DATA_IN) {
 835                 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
 836
 837                 BUG_ON(!dd->in_sg);
 838
 839                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 840
 841                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 842
 843                 for (i = 0; i < DES_BLOCK_WORDS; i++) {
 844                         omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
 845
 846                         scatterwalk_advance(&dd->in_walk, 4);
 847                         if (dd->in_sg->length == _calc_walked(in)) {
 848                                 dd->in_sg = sg_next(dd->in_sg);
 849                                 if (dd->in_sg) {
 850                                         scatterwalk_start(&dd->in_walk,
 851                                                           dd->in_sg);
 852                                         src = sg_virt(dd->in_sg) +
 853                                               _calc_walked(in);
 854                                 }
 855                         } else {
 856                                 src++;
 857                         }
 858                 }
 859
 860                 /* Clear IRQ status */
 861                 status &= ~DES_REG_IRQ_DATA_IN;
 862                 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
 863
 864                 /* Enable DATA_OUT interrupt */
 865                 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
 866
 867         } else if (status & DES_REG_IRQ_DATA_OUT) {
 868                 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
 869
 870                 BUG_ON(!dd->out_sg);
 871
 872                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
 873
 874                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
 875
 876                 for (i = 0; i < DES_BLOCK_WORDS; i++) {
 877                         *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
 878                         scatterwalk_advance(&dd->out_walk, 4);
 879                         if (dd->out_sg->length == _calc_walked(out)) {
 880                                 dd->out_sg = sg_next(dd->out_sg);
 881                                 if (dd->out_sg) {
 882                                         scatterwalk_start(&dd->out_walk,
 883                                                           dd->out_sg);
 884                                         dst = sg_virt(dd->out_sg) +
 885                                               _calc_walked(out);
 886                                 }
 887                         } else {
 888                                 dst++;
 889                         }
 890                 }
 891
 892                 BUG_ON(dd->total < DES_BLOCK_SIZE);
 893
 894                 dd->total -= DES_BLOCK_SIZE;
 895
 896                 /* Clear IRQ status */
 897                 status &= ~DES_REG_IRQ_DATA_OUT;
 898                 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
 899
 900                 if (!dd->total)
 901                         /* All bytes read! */
 902                         tasklet_schedule(&dd->done_task);
 903                 else
 904                         /* Enable DATA_IN interrupt for next block */
 905                         omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
 906         }
 907
 908         return IRQ_HANDLED;
 909 }
 910
 911 static const struct of_device_id omap_des_of_match[] = {
 912         {
 913                 .compatible     = "ti,omap4-des",
 914                 .data           = &omap_des_pdata_omap4,
 915         },
 916         {},
 917 };
 918 MODULE_DEVICE_TABLE(of, omap_des_of_match);
 919
 920 static int omap_des_get_of(struct omap_des_dev *dd,
 921                 struct platform_device *pdev)
 922 {
 923
 924         dd->pdata = of_device_get_match_data(&pdev->dev);
 925         if (!dd->pdata) {
 926                 dev_err(&pdev->dev, "no compatible OF match\n");
 927                 return -EINVAL;
 928         }
 929
 930         return 0;
 931 }
 932 #else
 933 static int omap_des_get_of(struct omap_des_dev *dd,
 934                 struct device *dev)
 935 {
 936         return -EINVAL;
 937 }
 938 #endif
 939
 940 static int omap_des_get_pdev(struct omap_des_dev *dd,
 941                 struct platform_device *pdev)
 942 {
 943         /* non-DT devices get pdata from pdev */
 944         dd->pdata = pdev->dev.platform_data;
 945
 946         return 0;
 947 }
 948
 949 static int omap_des_probe(struct platform_device *pdev)
 950 {
 951         struct device *dev = &pdev->dev;
 952         struct omap_des_dev *dd;
 953         struct skcipher_engine_alg *algp;
 954         struct resource *res;
 955         int err = -ENOMEM, i, j, irq = -1;
 956         u32 reg;
 957
 958         dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
 959         if (dd == NULL) {
 960                 dev_err(dev, "unable to alloc data struct.\n");
 961                 goto err_data;
 962         }
 963         dd->dev = dev;
 964         platform_set_drvdata(pdev, dd);
 965
 966         err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
 967                                omap_des_get_pdev(dd, pdev);
 968         if (err)
 969                 goto err_res;
 970
 971         dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 972         if (IS_ERR(dd->io_base)) {
 973                 err = PTR_ERR(dd->io_base);
 974                 goto err_res;
 975         }
 976         dd->phys_base = res->start;
 977
 978         pm_runtime_use_autosuspend(dev);
 979         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
 980
 981         pm_runtime_enable(dev);
 982         err = pm_runtime_resume_and_get(dev);
 983         if (err < 0) {
 984                 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
 985                 goto err_get;
 986         }
 987
 988         omap_des_dma_stop(dd);
 989
 990         reg = omap_des_read(dd, DES_REG_REV(dd));
 991
 992         pm_runtime_put_sync(dev);
 993
 994         dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
 995                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
 996                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
 997
 998         tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
 999
1000         err = omap_des_dma_init(dd);
1001         if (err == -EPROBE_DEFER) {
1002                 goto err_irq;
1003         } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1004                 dd->pio_only = 1;
1005
1006                 irq = platform_get_irq(pdev, 0);
1007                 if (irq < 0) {
1008                         err = irq;
1009                         goto err_irq;
1010                 }
1011
1012                 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1013                                 dev_name(dev), dd);
1014                 if (err) {
1015                         dev_err(dev, "Unable to grab omap-des IRQ\n");
1016                         goto err_irq;
1017                 }
1018         }
1019
1020
1021         INIT_LIST_HEAD(&dd->list);
1022         spin_lock_bh(&list_lock);
1023         list_add_tail(&dd->list, &dev_list);
1024         spin_unlock_bh(&list_lock);
1025
1026         /* Initialize des crypto engine */
1027         dd->engine = crypto_engine_alloc_init(dev, 1);
1028         if (!dd->engine) {
1029                 err = -ENOMEM;
1030                 goto err_engine;
1031         }
1032
1033         err = crypto_engine_start(dd->engine);
1034         if (err)
1035                 goto err_engine;
1036
1037         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1038                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1039                         algp = &dd->pdata->algs_info[i].algs_list[j];
1040
1041                         pr_debug("reg alg: %s\n", algp->base.base.cra_name);
1042
1043                         err = crypto_engine_register_skcipher(algp);
1044                         if (err)
1045                                 goto err_algs;
1046
1047                         dd->pdata->algs_info[i].registered++;
1048                 }
1049         }
1050
1051         return 0;
1052
1053 err_algs:
1054         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1055                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1056                         crypto_engine_unregister_skcipher(
1057                                         &dd->pdata->algs_info[i].algs_list[j]);
1058
1059 err_engine:
1060         if (dd->engine)
1061                 crypto_engine_exit(dd->engine);
1062
1063         omap_des_dma_cleanup(dd);
1064 err_irq:
1065         tasklet_kill(&dd->done_task);
1066 err_get:
1067         pm_runtime_disable(dev);
1068 err_res:
1069         dd = NULL;
1070 err_data:
1071         dev_err(dev, "initialization failed.\n");
1072         return err;
1073 }
1074
1075 static int omap_des_remove(struct platform_device *pdev)
1076 {
1077         struct omap_des_dev *dd = platform_get_drvdata(pdev);
1078         int i, j;
1079
1080         spin_lock_bh(&list_lock);
1081         list_del(&dd->list);
1082         spin_unlock_bh(&list_lock);
1083
1084         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1085                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1086                         crypto_engine_unregister_skcipher(
1087                                         &dd->pdata->algs_info[i].algs_list[j]);
1088
1089         tasklet_kill(&dd->done_task);
1090         omap_des_dma_cleanup(dd);
1091         pm_runtime_disable(dd->dev);
1092
1093         return 0;
1094 }
1095
1096 #ifdef CONFIG_PM_SLEEP
1097 static int omap_des_suspend(struct device *dev)
1098 {
1099         pm_runtime_put_sync(dev);
1100         return 0;
1101 }
1102
1103 static int omap_des_resume(struct device *dev)
1104 {
1105         int err;
1106
1107         err = pm_runtime_resume_and_get(dev);
1108         if (err < 0) {
1109                 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1110                 return err;
1111         }
1112         return 0;
1113 }
1114 #endif
1115
1116 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1117
1118 static struct platform_driver omap_des_driver = {
1119         .probe  = omap_des_probe,
1120         .remove = omap_des_remove,
1121         .driver = {
1122                 .name   = "omap-des",
1123                 .pm     = &omap_des_pm_ops,
1124                 .of_match_table = of_match_ptr(omap_des_of_match),
1125         },
1126 };
1127
1128 module_platform_driver(omap_des_driver);
1129
1130 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1131 MODULE_LICENSE("GPL v2");
1132 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");