drivers/crypto/intel/qat/qat_common/icp_qat_fw_init_admin.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_
   4 #define _ICP_QAT_FW_INIT_ADMIN_H_
   5
   6 #include "icp_qat_fw.h"
   7
   8 enum icp_qat_fw_init_admin_cmd_id {
   9         ICP_QAT_FW_INIT_AE = 0,
  10         ICP_QAT_FW_TRNG_ENABLE = 1,
  11         ICP_QAT_FW_TRNG_DISABLE = 2,
  12         ICP_QAT_FW_CONSTANTS_CFG = 3,
  13         ICP_QAT_FW_STATUS_GET = 4,
  14         ICP_QAT_FW_COUNTERS_GET = 5,
  15         ICP_QAT_FW_LOOPBACK = 6,
  16         ICP_QAT_FW_HEARTBEAT_SYNC = 7,
  17         ICP_QAT_FW_HEARTBEAT_GET = 8,
  18         ICP_QAT_FW_COMP_CAPABILITY_GET = 9,
  19         ICP_QAT_FW_DC_CHAIN_INIT = 11,
  20         ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13,
  21         ICP_QAT_FW_TIMER_GET = 19,
  22         ICP_QAT_FW_PM_STATE_CONFIG = 128,
  23 };
  24
  25 enum icp_qat_fw_init_admin_resp_status {
  26         ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
  27         ICP_QAT_FW_INIT_RESP_STATUS_FAIL
  28 };
  29
  30 struct icp_qat_fw_init_admin_req {
  31         __u16 init_cfg_sz;
  32         __u8 resrvd1;
  33         __u8 cmd_id;
  34         __u32 resrvd2;
  35         __u64 opaque_data;
  36         __u64 init_cfg_ptr;
  37
  38         union {
  39                 struct {
  40                         __u16 ibuf_size_in_kb;
  41                         __u16 resrvd3;
  42                 };
  43                 struct {
  44                         __u32 int_timer_ticks;
  45                 };
  46                 struct {
  47                         __u32 heartbeat_ticks;
  48                 };
  49                 __u32 idle_filter;
  50         };
  51
  52         __u32 resrvd4;
  53 } __packed;
  54
  55 struct icp_qat_fw_init_admin_resp {
  56         __u8 flags;
  57         __u8 resrvd1;
  58         __u8 status;
  59         __u8 cmd_id;
  60         union {
  61                 __u32 resrvd2;
  62                 struct {
  63                         __u16 version_minor_num;
  64                         __u16 version_major_num;
  65                 };
  66                 __u32 extended_features;
  67         };
  68         __u64 opaque_data;
  69         union {
  70                 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4];
  71                 struct {
  72                         __u32 version_patch_num;
  73                         __u8 context_id;
  74                         __u8 ae_id;
  75                         __u16 resrvd4;
  76                         __u64 resrvd5;
  77                 };
  78                 struct {
  79                         __u64 req_rec_count;
  80                         __u64 resp_sent_count;
  81                 };
  82                 struct {
  83                         __u16 compression_algos;
  84                         __u16 checksum_algos;
  85                         __u32 deflate_capabilities;
  86                         __u32 resrvd6;
  87                         __u32 lzs_capabilities;
  88                 };
  89                 struct {
  90                         __u32 cipher_algos;
  91                         __u32 hash_algos;
  92                         __u16 keygen_algos;
  93                         __u16 other;
  94                         __u16 public_key_algos;
  95                         __u16 prime_algos;
  96                 };
  97                 struct {
  98                         __u64 timestamp;
  99                         __u64 resrvd7;
 100                 };
 101                 struct {
 102                         __u32 successful_count;
 103                         __u32 unsuccessful_count;
 104                         __u64 resrvd8;
 105                 };
 106         };
 107 } __packed;
 108
 109 #define ICP_QAT_FW_SYNC ICP_QAT_FW_HEARTBEAT_SYNC
 110
 111 #endif