drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

   1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
   2 /* Copyright(c) 2020 - 2021 Intel Corporation */
   3 #include <linux/iopoll.h>
   4 #include <adf_accel_devices.h>
   5 #include <adf_cfg.h>
   6 #include <adf_clock.h>
   7 #include <adf_common_drv.h>
   8 #include <adf_gen4_dc.h>
   9 #include <adf_gen4_hw_data.h>
  10 #include <adf_gen4_pfvf.h>
  11 #include <adf_gen4_pm.h>
  12 #include <adf_gen4_timer.h>
  13 #include "adf_4xxx_hw_data.h"
  14 #include "adf_cfg_services.h"
  15 #include "icp_qat_hw.h"
  16
  17 enum adf_fw_objs {
  18         ADF_FW_SYM_OBJ,
  19         ADF_FW_ASYM_OBJ,
  20         ADF_FW_DC_OBJ,
  21         ADF_FW_ADMIN_OBJ,
  22 };
  23
  24 static const char * const adf_4xxx_fw_objs[] = {
  25         [ADF_FW_SYM_OBJ] =  ADF_4XXX_SYM_OBJ,
  26         [ADF_FW_ASYM_OBJ] =  ADF_4XXX_ASYM_OBJ,
  27         [ADF_FW_DC_OBJ] =  ADF_4XXX_DC_OBJ,
  28         [ADF_FW_ADMIN_OBJ] = ADF_4XXX_ADMIN_OBJ,
  29 };
  30
  31 static const char * const adf_402xx_fw_objs[] = {
  32         [ADF_FW_SYM_OBJ] =  ADF_402XX_SYM_OBJ,
  33         [ADF_FW_ASYM_OBJ] =  ADF_402XX_ASYM_OBJ,
  34         [ADF_FW_DC_OBJ] =  ADF_402XX_DC_OBJ,
  35         [ADF_FW_ADMIN_OBJ] = ADF_402XX_ADMIN_OBJ,
  36 };
  37
  38 struct adf_fw_config {
  39         u32 ae_mask;
  40         enum adf_fw_objs obj;
  41 };
  42
  43 static const struct adf_fw_config adf_fw_cy_config[] = {
  44         {0xF0, ADF_FW_SYM_OBJ},
  45         {0xF, ADF_FW_ASYM_OBJ},
  46         {0x100, ADF_FW_ADMIN_OBJ},
  47 };
  48
  49 static const struct adf_fw_config adf_fw_dc_config[] = {
  50         {0xF0, ADF_FW_DC_OBJ},
  51         {0xF, ADF_FW_DC_OBJ},
  52         {0x100, ADF_FW_ADMIN_OBJ},
  53 };
  54
  55 static const struct adf_fw_config adf_fw_sym_config[] = {
  56         {0xF0, ADF_FW_SYM_OBJ},
  57         {0xF, ADF_FW_SYM_OBJ},
  58         {0x100, ADF_FW_ADMIN_OBJ},
  59 };
  60
  61 static const struct adf_fw_config adf_fw_asym_config[] = {
  62         {0xF0, ADF_FW_ASYM_OBJ},
  63         {0xF, ADF_FW_ASYM_OBJ},
  64         {0x100, ADF_FW_ADMIN_OBJ},
  65 };
  66
  67 static const struct adf_fw_config adf_fw_asym_dc_config[] = {
  68         {0xF0, ADF_FW_ASYM_OBJ},
  69         {0xF, ADF_FW_DC_OBJ},
  70         {0x100, ADF_FW_ADMIN_OBJ},
  71 };
  72
  73 static const struct adf_fw_config adf_fw_sym_dc_config[] = {
  74         {0xF0, ADF_FW_SYM_OBJ},
  75         {0xF, ADF_FW_DC_OBJ},
  76         {0x100, ADF_FW_ADMIN_OBJ},
  77 };
  78
  79 static const struct adf_fw_config adf_fw_dcc_config[] = {
  80         {0xF0, ADF_FW_DC_OBJ},
  81         {0xF, ADF_FW_SYM_OBJ},
  82         {0x100, ADF_FW_ADMIN_OBJ},
  83 };
  84
  85 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_dc_config));
  86 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_config));
  87 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_config));
  88 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_asym_dc_config));
  89 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_sym_dc_config));
  90 static_assert(ARRAY_SIZE(adf_fw_cy_config) == ARRAY_SIZE(adf_fw_dcc_config));
  91
  92 /* Worker thread to service arbiter mappings */
  93 static const u32 default_thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
  94         0x5555555, 0x5555555, 0x5555555, 0x5555555,
  95         0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
  96         0x0
  97 };
  98
  99 static const u32 thrd_to_arb_map_dc[ADF_4XXX_MAX_ACCELENGINES] = {
 100         0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
 101         0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,
 102         0x0
 103 };
 104
 105 static const u32 thrd_to_arb_map_dcc[ADF_4XXX_MAX_ACCELENGINES] = {
 106         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 107         0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,
 108         0x0
 109 };
 110
 111 static struct adf_hw_device_class adf_4xxx_class = {
 112         .name = ADF_4XXX_DEVICE_NAME,
 113         .type = DEV_4XXX,
 114         .instances = 0,
 115 };
 116
 117 static int get_service_enabled(struct adf_accel_dev *accel_dev)
 118 {
 119         char services[ADF_CFG_MAX_VAL_LEN_IN_BYTES] = {0};
 120         int ret;
 121
 122         ret = adf_cfg_get_param_value(accel_dev, ADF_GENERAL_SEC,
 123                                       ADF_SERVICES_ENABLED, services);
 124         if (ret) {
 125                 dev_err(&GET_DEV(accel_dev),
 126                         ADF_SERVICES_ENABLED " param not found\n");
 127                 return ret;
 128         }
 129
 130         ret = match_string(adf_cfg_services, ARRAY_SIZE(adf_cfg_services),
 131                            services);
 132         if (ret < 0)
 133                 dev_err(&GET_DEV(accel_dev),
 134                         "Invalid value of " ADF_SERVICES_ENABLED " param: %s\n",
 135                         services);
 136
 137         return ret;
 138 }
 139
 140 static u32 get_accel_mask(struct adf_hw_device_data *self)
 141 {
 142         return ADF_4XXX_ACCELERATORS_MASK;
 143 }
 144
 145 static u32 get_ae_mask(struct adf_hw_device_data *self)
 146 {
 147         u32 me_disable = self->fuses;
 148
 149         return ~me_disable & ADF_4XXX_ACCELENGINES_MASK;
 150 }
 151
 152 static u32 get_num_accels(struct adf_hw_device_data *self)
 153 {
 154         return ADF_4XXX_MAX_ACCELERATORS;
 155 }
 156
 157 static u32 get_num_aes(struct adf_hw_device_data *self)
 158 {
 159         if (!self || !self->ae_mask)
 160                 return 0;
 161
 162         return hweight32(self->ae_mask);
 163 }
 164
 165 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
 166 {
 167         return ADF_4XXX_PMISC_BAR;
 168 }
 169
 170 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
 171 {
 172         return ADF_4XXX_ETR_BAR;
 173 }
 174
 175 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
 176 {
 177         return ADF_4XXX_SRAM_BAR;
 178 }
 179
 180 /*
 181  * The vector routing table is used to select the MSI-X entry to use for each
 182  * interrupt source.
 183  * The first ADF_4XXX_ETR_MAX_BANKS entries correspond to ring interrupts.
 184  * The final entry corresponds to VF2PF or error interrupts.
 185  * This vector table could be used to configure one MSI-X entry to be shared
 186  * between multiple interrupt sources.
 187  *
 188  * The default routing is set to have a one to one correspondence between the
 189  * interrupt source and the MSI-X entry used.
 190  */
 191 static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)
 192 {
 193         void __iomem *csr;
 194         int i;
 195
 196         csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
 197         for (i = 0; i <= ADF_4XXX_ETR_MAX_BANKS; i++)
 198                 ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);
 199 }
 200
 201 static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
 202 {
 203         struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
 204         u32 capabilities_sym, capabilities_asym, capabilities_dc;
 205         u32 capabilities_dcc;
 206         u32 fusectl1;
 207
 208         /* Read accelerator capabilities mask */
 209         pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
 210
 211         capabilities_sym = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
 212                           ICP_ACCEL_CAPABILITIES_CIPHER |
 213                           ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
 214                           ICP_ACCEL_CAPABILITIES_SHA3 |
 215                           ICP_ACCEL_CAPABILITIES_SHA3_EXT |
 216                           ICP_ACCEL_CAPABILITIES_HKDF |
 217                           ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
 218                           ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
 219                           ICP_ACCEL_CAPABILITIES_SM3 |
 220                           ICP_ACCEL_CAPABILITIES_SM4 |
 221                           ICP_ACCEL_CAPABILITIES_AES_V2;
 222
 223         /* A set bit in fusectl1 means the feature is OFF in this SKU */
 224         if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {
 225                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
 226                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_HKDF;
 227                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
 228         }
 229
 230         if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
 231                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
 232                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
 233                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
 234                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
 235         }
 236
 237         if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
 238                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
 239                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3;
 240                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
 241                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
 242         }
 243
 244         if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) {
 245                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM3;
 246                 capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM4;
 247         }
 248
 249         capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
 250                           ICP_ACCEL_CAPABILITIES_CIPHER |
 251                           ICP_ACCEL_CAPABILITIES_SM2 |
 252                           ICP_ACCEL_CAPABILITIES_ECEDMONT;
 253
 254         if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
 255                 capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
 256                 capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
 257                 capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
 258         }
 259
 260         capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
 261                           ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
 262                           ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
 263                           ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
 264
 265         if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
 266                 capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
 267                 capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
 268                 capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
 269                 capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
 270         }
 271
 272         switch (get_service_enabled(accel_dev)) {
 273         case SVC_CY:
 274         case SVC_CY2:
 275                 return capabilities_sym | capabilities_asym;
 276         case SVC_DC:
 277                 return capabilities_dc;
 278         case SVC_DCC:
 279                 /*
 280                  * Sym capabilities are available for chaining operations,
 281                  * but sym crypto instances cannot be supported
 282                  */
 283                 capabilities_dcc = capabilities_dc | capabilities_sym;
 284                 capabilities_dcc &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
 285                 return capabilities_dcc;
 286         case SVC_SYM:
 287                 return capabilities_sym;
 288         case SVC_ASYM:
 289                 return capabilities_asym;
 290         case SVC_ASYM_DC:
 291         case SVC_DC_ASYM:
 292                 return capabilities_asym | capabilities_dc;
 293         case SVC_SYM_DC:
 294         case SVC_DC_SYM:
 295                 return capabilities_sym | capabilities_dc;
 296         default:
 297                 return 0;
 298         }
 299 }
 300
 301 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
 302 {
 303         return DEV_SKU_1;
 304 }
 305
 306 static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
 307 {
 308         switch (get_service_enabled(accel_dev)) {
 309         case SVC_DC:
 310                 return thrd_to_arb_map_dc;
 311         case SVC_DCC:
 312                 return thrd_to_arb_map_dcc;
 313         default:
 314                 return default_thrd_to_arb_map;
 315         }
 316 }
 317
 318 static void get_arb_info(struct arb_info *arb_info)
 319 {
 320         arb_info->arb_cfg = ADF_4XXX_ARB_CONFIG;
 321         arb_info->arb_offset = ADF_4XXX_ARB_OFFSET;
 322         arb_info->wt2sam_offset = ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET;
 323 }
 324
 325 static void get_admin_info(struct admin_info *admin_csrs_info)
 326 {
 327         admin_csrs_info->mailbox_offset = ADF_4XXX_MAILBOX_BASE_OFFSET;
 328         admin_csrs_info->admin_msg_ur = ADF_4XXX_ADMINMSGUR_OFFSET;
 329         admin_csrs_info->admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;
 330 }
 331
 332 static u32 get_heartbeat_clock(struct adf_hw_device_data *self)
 333 {
 334         /*
 335          * 4XXX uses KPT counter for HB
 336          */
 337         return ADF_4XXX_KPT_COUNTER_FREQ;
 338 }
 339
 340 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
 341 {
 342         struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];
 343         void __iomem *csr = misc_bar->virt_addr;
 344
 345         /* Enable all in errsou3 except VFLR notification on host */
 346         ADF_CSR_WR(csr, ADF_GEN4_ERRMSK3, ADF_GEN4_VFLNOTIFY);
 347 }
 348
 349 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
 350 {
 351         void __iomem *addr;
 352
 353         addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
 354
 355         /* Enable bundle interrupts */
 356         ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0);
 357         ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0);
 358
 359         /* Enable misc interrupts */
 360         ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0);
 361 }
 362
 363 static int adf_init_device(struct adf_accel_dev *accel_dev)
 364 {
 365         void __iomem *addr;
 366         u32 status;
 367         u32 csr;
 368         int ret;
 369
 370         addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
 371
 372         /* Temporarily mask PM interrupt */
 373         csr = ADF_CSR_RD(addr, ADF_GEN4_ERRMSK2);
 374         csr |= ADF_GEN4_PM_SOU;
 375         ADF_CSR_WR(addr, ADF_GEN4_ERRMSK2, csr);
 376
 377         /* Set DRV_ACTIVE bit to power up the device */
 378         ADF_CSR_WR(addr, ADF_GEN4_PM_INTERRUPT, ADF_GEN4_PM_DRV_ACTIVE);
 379
 380         /* Poll status register to make sure the device is powered up */
 381         ret = read_poll_timeout(ADF_CSR_RD, status,
 382                                 status & ADF_GEN4_PM_INIT_STATE,
 383                                 ADF_GEN4_PM_POLL_DELAY_US,
 384                                 ADF_GEN4_PM_POLL_TIMEOUT_US, true, addr,
 385                                 ADF_GEN4_PM_STATUS);
 386         if (ret)
 387                 dev_err(&GET_DEV(accel_dev), "Failed to power up the device\n");
 388
 389         return ret;
 390 }
 391
 392 static u32 uof_get_num_objs(void)
 393 {
 394         return ARRAY_SIZE(adf_fw_cy_config);
 395 }
 396
 397 static const char *uof_get_name(struct adf_accel_dev *accel_dev, u32 obj_num,
 398                                 const char * const fw_objs[], int num_objs)
 399 {
 400         int id;
 401
 402         switch (get_service_enabled(accel_dev)) {
 403         case SVC_CY:
 404         case SVC_CY2:
 405                 id = adf_fw_cy_config[obj_num].obj;
 406                 break;
 407         case SVC_DC:
 408                 id = adf_fw_dc_config[obj_num].obj;
 409                 break;
 410         case SVC_DCC:
 411                 id = adf_fw_dcc_config[obj_num].obj;
 412                 break;
 413         case SVC_SYM:
 414                 id = adf_fw_sym_config[obj_num].obj;
 415                 break;
 416         case SVC_ASYM:
 417                 id =  adf_fw_asym_config[obj_num].obj;
 418                 break;
 419         case SVC_ASYM_DC:
 420         case SVC_DC_ASYM:
 421                 id = adf_fw_asym_dc_config[obj_num].obj;
 422                 break;
 423         case SVC_SYM_DC:
 424         case SVC_DC_SYM:
 425                 id = adf_fw_sym_dc_config[obj_num].obj;
 426                 break;
 427         default:
 428                 id = -EINVAL;
 429                 break;
 430         }
 431
 432         if (id < 0 || id > num_objs)
 433                 return NULL;
 434
 435         return fw_objs[id];
 436 }
 437
 438 static const char *uof_get_name_4xxx(struct adf_accel_dev *accel_dev, u32 obj_num)
 439 {
 440         int num_fw_objs = ARRAY_SIZE(adf_4xxx_fw_objs);
 441
 442         return uof_get_name(accel_dev, obj_num, adf_4xxx_fw_objs, num_fw_objs);
 443 }
 444
 445 static const char *uof_get_name_402xx(struct adf_accel_dev *accel_dev, u32 obj_num)
 446 {
 447         int num_fw_objs = ARRAY_SIZE(adf_402xx_fw_objs);
 448
 449         return uof_get_name(accel_dev, obj_num, adf_402xx_fw_objs, num_fw_objs);
 450 }
 451
 452 static u32 uof_get_ae_mask(struct adf_accel_dev *accel_dev, u32 obj_num)
 453 {
 454         switch (get_service_enabled(accel_dev)) {
 455         case SVC_CY:
 456                 return adf_fw_cy_config[obj_num].ae_mask;
 457         case SVC_DC:
 458                 return adf_fw_dc_config[obj_num].ae_mask;
 459         case SVC_DCC:
 460                 return adf_fw_dcc_config[obj_num].ae_mask;
 461         case SVC_CY2:
 462                 return adf_fw_cy_config[obj_num].ae_mask;
 463         case SVC_SYM:
 464                 return adf_fw_sym_config[obj_num].ae_mask;
 465         case SVC_ASYM:
 466                 return adf_fw_asym_config[obj_num].ae_mask;
 467         case SVC_ASYM_DC:
 468         case SVC_DC_ASYM:
 469                 return adf_fw_asym_dc_config[obj_num].ae_mask;
 470         case SVC_SYM_DC:
 471         case SVC_DC_SYM:
 472                 return adf_fw_sym_dc_config[obj_num].ae_mask;
 473         default:
 474                 return 0;
 475         }
 476 }
 477
 478 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
 479 {
 480         hw_data->dev_class = &adf_4xxx_class;
 481         hw_data->instance_id = adf_4xxx_class.instances++;
 482         hw_data->num_banks = ADF_4XXX_ETR_MAX_BANKS;
 483         hw_data->num_banks_per_vf = ADF_4XXX_NUM_BANKS_PER_VF;
 484         hw_data->num_rings_per_bank = ADF_4XXX_NUM_RINGS_PER_BANK;
 485         hw_data->num_accel = ADF_4XXX_MAX_ACCELERATORS;
 486         hw_data->num_engines = ADF_4XXX_MAX_ACCELENGINES;
 487         hw_data->num_logical_accel = 1;
 488         hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
 489         hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
 490         hw_data->ring_to_svc_map = ADF_GEN4_DEFAULT_RING_TO_SRV_MAP;
 491         hw_data->alloc_irq = adf_isr_resource_alloc;
 492         hw_data->free_irq = adf_isr_resource_free;
 493         hw_data->enable_error_correction = adf_enable_error_correction;
 494         hw_data->get_accel_mask = get_accel_mask;
 495         hw_data->get_ae_mask = get_ae_mask;
 496         hw_data->get_num_accels = get_num_accels;
 497         hw_data->get_num_aes = get_num_aes;
 498         hw_data->get_sram_bar_id = get_sram_bar_id;
 499         hw_data->get_etr_bar_id = get_etr_bar_id;
 500         hw_data->get_misc_bar_id = get_misc_bar_id;
 501         hw_data->get_arb_info = get_arb_info;
 502         hw_data->get_admin_info = get_admin_info;
 503         hw_data->get_accel_cap = get_accel_cap;
 504         hw_data->get_sku = get_sku;
 505         hw_data->init_admin_comms = adf_init_admin_comms;
 506         hw_data->exit_admin_comms = adf_exit_admin_comms;
 507         hw_data->send_admin_init = adf_send_admin_init;
 508         hw_data->init_arb = adf_init_arb;
 509         hw_data->exit_arb = adf_exit_arb;
 510         hw_data->get_arb_mapping = adf_get_arbiter_mapping;
 511         hw_data->enable_ints = adf_enable_ints;
 512         hw_data->init_device = adf_init_device;
 513         hw_data->reset_device = adf_reset_flr;
 514         hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;
 515         switch (dev_id) {
 516         case ADF_402XX_PCI_DEVICE_ID:
 517                 hw_data->fw_name = ADF_402XX_FW;
 518                 hw_data->fw_mmp_name = ADF_402XX_MMP;
 519                 hw_data->uof_get_name = uof_get_name_402xx;
 520                 break;
 521
 522         default:
 523                 hw_data->fw_name = ADF_4XXX_FW;
 524                 hw_data->fw_mmp_name = ADF_4XXX_MMP;
 525                 hw_data->uof_get_name = uof_get_name_4xxx;
 526         }
 527         hw_data->uof_get_num_objs = uof_get_num_objs;
 528         hw_data->uof_get_ae_mask = uof_get_ae_mask;
 529         hw_data->set_msix_rttable = set_msix_default_rttable;
 530         hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
 531         hw_data->disable_iov = adf_disable_sriov;
 532         hw_data->ring_pair_reset = adf_gen4_ring_pair_reset;
 533         hw_data->enable_pm = adf_gen4_enable_pm;
 534         hw_data->handle_pm_interrupt = adf_gen4_handle_pm_interrupt;
 535         hw_data->dev_config = adf_gen4_dev_config;
 536         hw_data->start_timer = adf_gen4_timer_start;
 537         hw_data->stop_timer = adf_gen4_timer_stop;
 538         hw_data->get_hb_clock = get_heartbeat_clock;
 539         hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
 540
 541         adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
 542         adf_gen4_init_pf_pfvf_ops(&hw_data->pfvf_ops);
 543         adf_gen4_init_dc_ops(&hw_data->dc_ops);
 544 }
 545
 546 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)
 547 {
 548         hw_data->dev_class->instances--;
 549 }