1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2014 Freescale Semiconductor, Inc.
5 * Based on CAAM driver in drivers/crypto/caam in Linux
15 #include "desc_constr.h"
17 #include <asm/cache.h>
18 #ifdef CONFIG_FSL_CORENET
19 #include <asm/cache.h>
20 #include <asm/fsl_pamu.h>
23 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
24 #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
26 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
28 #if defined(CONFIG_ARCH_C29X)
29 CONFIG_SYS_FSL_SEC_IDX_OFFSET,
30 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
34 #define SEC_ADDR(idx) \
35 ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
37 #define SEC_JR0_ADDR(idx) \
39 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
41 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
43 static inline void start_jr0(uint8_t sec_idx)
45 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
46 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
47 u32 scfgr = sec_in32(&sec->scfgr);
49 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
50 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
51 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
53 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
54 (scfgr & SEC_SCFGR_VIRT_EN))
55 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
57 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
58 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
59 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
63 static inline void jr_reset_liodn(uint8_t sec_idx)
65 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
66 sec_out32(&sec->jrliodnr[0].ls, 0);
69 static inline void jr_disable_irq(uint8_t sec_idx)
71 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
72 uint32_t jrcfg = sec_in32(®s->jrcfg1);
74 jrcfg = jrcfg | JR_INTMASK;
76 sec_out32(®s->jrcfg1, jrcfg);
79 static void jr_initregs(uint8_t sec_idx)
81 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
82 struct jobring *jr = &jr0[sec_idx];
83 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
84 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
86 #ifdef CONFIG_PHYS_64BIT
87 sec_out32(®s->irba_h, ip_base >> 32);
89 sec_out32(®s->irba_h, 0x0);
91 sec_out32(®s->irba_l, (uint32_t)ip_base);
92 #ifdef CONFIG_PHYS_64BIT
93 sec_out32(®s->orba_h, op_base >> 32);
95 sec_out32(®s->orba_h, 0x0);
97 sec_out32(®s->orba_l, (uint32_t)op_base);
98 sec_out32(®s->ors, JR_SIZE);
99 sec_out32(®s->irs, JR_SIZE);
102 jr_disable_irq(sec_idx);
105 static int jr_init(uint8_t sec_idx)
107 struct jobring *jr = &jr0[sec_idx];
109 memset(jr, 0, sizeof(struct jobring));
111 jr->jq_id = DEFAULT_JR_ID;
112 jr->irq = DEFAULT_IRQ;
114 #ifdef CONFIG_FSL_CORENET
115 jr->liodn = DEFAULT_JR_LIODN;
118 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
119 JR_SIZE * sizeof(dma_addr_t));
123 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
126 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
127 if (!jr->output_ring)
130 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
131 memset(jr->output_ring, 0, jr->op_size);
135 jr_initregs(sec_idx);
140 static int jr_sw_cleanup(uint8_t sec_idx)
142 struct jobring *jr = &jr0[sec_idx];
148 memset(jr->info, 0, sizeof(jr->info));
149 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
150 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
155 static int jr_hw_reset(uint8_t sec_idx)
157 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
158 uint32_t timeout = 100000;
159 uint32_t jrint, jrcr;
161 sec_out32(®s->jrcr, JRCR_RESET);
163 jrint = sec_in32(®s->jrint);
164 } while (((jrint & JRINT_ERR_HALT_MASK) ==
165 JRINT_ERR_HALT_INPROGRESS) && --timeout);
167 jrint = sec_in32(®s->jrint);
168 if (((jrint & JRINT_ERR_HALT_MASK) !=
169 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
173 sec_out32(®s->jrcr, JRCR_RESET);
175 jrcr = sec_in32(®s->jrcr);
176 } while ((jrcr & JRCR_RESET) && --timeout);
184 /* -1 --- error, can't enqueue -- no space available */
185 static int jr_enqueue(uint32_t *desc_addr,
186 void (*callback)(uint32_t status, void *arg),
187 void *arg, uint8_t sec_idx)
189 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
190 struct jobring *jr = &jr0[sec_idx];
193 int length = desc_len(desc_addr);
195 #ifdef CONFIG_PHYS_64BIT
196 uint32_t *addr_hi, *addr_lo;
199 /* The descriptor must be submitted to SEC block as per endianness
201 * So, if the endianness of Core and SEC block is different, each word
202 * of the descriptor will be byte-swapped.
204 for (i = 0; i < length; i++) {
205 desc_word = desc_addr[i];
206 sec_out32((uint32_t *)&desc_addr[i], desc_word);
209 phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
211 jr->info[head].desc_phys_addr = desc_phys_addr;
212 jr->info[head].callback = (void *)callback;
213 jr->info[head].arg = arg;
214 jr->info[head].op_done = 0;
216 unsigned long start = (unsigned long)&jr->info[head] &
217 ~(ARCH_DMA_MINALIGN - 1);
218 unsigned long end = ALIGN((unsigned long)&jr->info[head] +
219 sizeof(struct jr_info), ARCH_DMA_MINALIGN);
220 flush_dcache_range(start, end);
222 #ifdef CONFIG_PHYS_64BIT
223 /* Write the 64 bit Descriptor address on Input Ring.
224 * The 32 bit hign and low part of the address will
225 * depend on endianness of SEC block.
227 #ifdef CONFIG_SYS_FSL_SEC_LE
228 addr_lo = (uint32_t *)(&jr->input_ring[head]);
229 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
230 #elif defined(CONFIG_SYS_FSL_SEC_BE)
231 addr_hi = (uint32_t *)(&jr->input_ring[head]);
232 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
233 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
235 sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
236 sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
239 /* Write the 32 bit Descriptor address on Input Ring. */
240 sec_out32(&jr->input_ring[head], desc_phys_addr);
241 #endif /* ifdef CONFIG_PHYS_64BIT */
243 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
244 end = ALIGN((unsigned long)&jr->input_ring[head] +
245 sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
246 flush_dcache_range(start, end);
248 jr->head = (head + 1) & (jr->size - 1);
250 /* Invalidate output ring */
251 start = (unsigned long)jr->output_ring &
252 ~(ARCH_DMA_MINALIGN - 1);
253 end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
255 invalidate_dcache_range(start, end);
257 sec_out32(®s->irja, 1);
262 static int jr_dequeue(int sec_idx)
264 struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
265 struct jobring *jr = &jr0[sec_idx];
269 void (*callback)(uint32_t status, void *arg);
271 #ifdef CONFIG_PHYS_64BIT
272 uint32_t *addr_hi, *addr_lo;
277 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail,
283 #ifdef CONFIG_PHYS_64BIT
284 /* Read the 64 bit Descriptor address from Output Ring.
285 * The 32 bit hign and low part of the address will
286 * depend on endianness of SEC block.
288 #ifdef CONFIG_SYS_FSL_SEC_LE
289 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
290 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
291 #elif defined(CONFIG_SYS_FSL_SEC_BE)
292 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
293 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
294 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
296 op_desc = ((u64)sec_in32(addr_hi) << 32) |
297 ((u64)sec_in32(addr_lo));
300 /* Read the 32 bit Descriptor address from Output Ring. */
301 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
302 op_desc = sec_in32(addr);
303 #endif /* ifdef CONFIG_PHYS_64BIT */
305 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
307 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
308 idx = (tail + i) & (jr->size - 1);
309 if (op_desc == jr->info[idx].desc_phys_addr) {
315 /* Error condition if match not found */
319 jr->info[idx].op_done = 1;
320 callback = (void *)jr->info[idx].callback;
321 arg = jr->info[idx].arg;
323 /* When the job on tail idx gets done, increment
324 * tail till the point where job completed out of oredr has
325 * been taken into account
329 tail = (tail + 1) & (jr->size - 1);
330 } while (jr->info[tail].op_done);
333 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
335 sec_out32(®s->orjr, 1);
336 jr->info[idx].op_done = 0;
338 callback(status, arg);
344 static void desc_done(uint32_t status, void *arg)
346 struct result *x = arg;
348 #ifndef CONFIG_SPL_BUILD
349 caam_jr_strstatus(status);
354 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
356 unsigned long long timeval = get_ticks();
357 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
361 memset(&op, 0, sizeof(op));
363 ret = jr_enqueue(desc, desc_done, &op, sec_idx);
365 debug("Error in SEC enq\n");
370 timeval = get_ticks();
371 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
372 while (op.done != 1) {
373 ret = jr_dequeue(sec_idx);
375 debug("Error in SEC deq\n");
380 if ((get_ticks() - timeval) > timeout) {
381 debug("SEC Dequeue timed out\n");
388 debug("Error %x\n", op.status);
395 int run_descriptor_jr(uint32_t *desc)
397 return run_descriptor_jr_idx(desc, 0);
400 static inline int jr_reset_sec(uint8_t sec_idx)
402 if (jr_hw_reset(sec_idx) < 0)
405 /* Clean up the jobring structure maintained by software */
406 jr_sw_cleanup(sec_idx);
413 return jr_reset_sec(0);
416 static inline int sec_reset_idx(uint8_t sec_idx)
418 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
419 uint32_t mcfgr = sec_in32(&sec->mcfgr);
420 uint32_t timeout = 100000;
422 mcfgr |= MCFGR_SWRST;
423 sec_out32(&sec->mcfgr, mcfgr);
425 mcfgr |= MCFGR_DMA_RST;
426 sec_out32(&sec->mcfgr, mcfgr);
428 mcfgr = sec_in32(&sec->mcfgr);
429 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
436 mcfgr = sec_in32(&sec->mcfgr);
437 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
446 return sec_reset_idx(0);
448 #ifndef CONFIG_SPL_BUILD
449 static int instantiate_rng(uint8_t sec_idx)
453 int ret = 0, sh_idx, size;
454 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
455 struct rng4tst __iomem *rng =
456 (struct rng4tst __iomem *)&sec->rng;
458 desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
460 printf("cannot allocate RNG init descriptor memory\n");
464 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
466 * If the corresponding bit is set, this state handle
467 * was initialized by somebody else, so it's left alone.
469 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
470 if (rdsta_val & (1 << sh_idx))
473 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx);
474 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
475 flush_dcache_range((unsigned long)desc,
476 (unsigned long)desc + size);
478 ret = run_descriptor_jr_idx(desc, sec_idx);
481 printf("RNG: Instantiation failed with error 0x%x\n",
484 rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
485 if (!(rdsta_val & (1 << sh_idx))) {
490 memset(desc, 0, sizeof(uint32_t) * 6);
498 static u8 get_rng_vid(uint8_t sec_idx)
500 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
501 u32 cha_vid = sec_in32(&sec->chavid_ls);
503 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
507 * By default, the TRNG runs for 200 clocks per sample;
508 * 1200 clocks per sample generates better entropy.
510 static void kick_trng(int ent_delay, uint8_t sec_idx)
512 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
513 struct rng4tst __iomem *rng =
514 (struct rng4tst __iomem *)&sec->rng;
517 /* put RNG4 into program mode */
518 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
519 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
520 * length (in system clocks) of each Entropy sample taken
522 val = sec_in32(&rng->rtsdctl);
523 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
524 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
525 sec_out32(&rng->rtsdctl, val);
526 /* min. freq. count, equal to 1/4 of the entropy sample length */
527 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
528 /* disable maximum frequency count */
529 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
531 * select raw sampling in both entropy shifter
532 * and statistical checker
534 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
535 /* put RNG4 into run mode */
536 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
539 static int rng_init(uint8_t sec_idx)
541 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
542 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
543 struct rng4tst __iomem *rng =
544 (struct rng4tst __iomem *)&sec->rng;
548 inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK;
551 * If either of the SH's were instantiated by somebody else
552 * then it is assumed that the entropy
553 * parameters are properly set and thus the function
554 * setting these (kick_trng(...)) is skipped.
555 * Also, if a handle was instantiated, do not change
556 * the TRNG parameters.
559 kick_trng(ent_delay, sec_idx);
563 * if instantiate_rng(...) fails, the loop will rerun
564 * and the kick_trng(...) function will modfiy the
565 * upper and lower limits of the entropy sampling
566 * interval, leading to a sucessful initialization of
569 ret = instantiate_rng(sec_idx);
570 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
572 printf("RNG: Failed to instantiate RNG\n");
576 /* Enable RDB bit so that RNG works faster */
577 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
582 int sec_init_idx(uint8_t sec_idx)
584 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
585 uint32_t mcr = sec_in32(&sec->mcfgr);
588 #ifdef CONFIG_FSL_CORENET
594 if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
595 printf("SEC initialization failed\n");
600 * Modifying CAAM Read/Write Attributes
602 * For AXI Write - Cacheable, Write Back, Write allocate
603 * For AXI Read - Cacheable, Read allocate
604 * Only For LS2080a, to solve CAAM coherency issues
606 #ifdef CONFIG_ARCH_LS2080A
607 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
608 mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
610 mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
613 #ifdef CONFIG_PHYS_64BIT
614 mcr |= (1 << MCFGR_PS_SHIFT);
616 sec_out32(&sec->mcfgr, mcr);
618 #ifdef CONFIG_FSL_CORENET
619 #ifdef CONFIG_SPL_BUILD
621 * For SPL Build, Set the Liodns in SEC JR0 for
622 * creating PAMU entries corresponding to these.
623 * For normal build, these are set in set_liodns().
625 liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
626 liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
628 liodnr = sec_in32(&sec->jrliodnr[0].ls) &
629 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
631 (liodn_ns << JRNSLIODN_SHIFT) |
632 (liodn_s << JRSLIODN_SHIFT);
633 sec_out32(&sec->jrliodnr[0].ls, liodnr);
635 liodnr = sec_in32(&sec->jrliodnr[0].ls);
636 liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
637 liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
641 ret = jr_init(sec_idx);
643 printf("SEC initialization failed\n");
647 #ifdef CONFIG_FSL_CORENET
648 ret = sec_config_pamu_table(liodn_ns, liodn_s);
654 #ifndef CONFIG_SPL_BUILD
655 if (get_rng_vid(sec_idx) >= 4) {
656 if (rng_init(sec_idx) < 0) {
657 printf("SEC%u: RNG instantiation failed\n", sec_idx);
660 printf("SEC%u: RNG instantiated\n", sec_idx);
668 return sec_init_idx(0);