drivers/crypto/fsl/jr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  *
   5  * Based on CAAM driver in drivers/crypto/caam in Linux
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <linux/kernel.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include "fsl_sec.h"
  14 #include "jr.h"
  15 #include "jobdesc.h"
  16 #include "desc_constr.h"
  17 #include <time.h>
  18 #include <asm/cache.h>
  19 #ifdef CONFIG_FSL_CORENET
  20 #include <asm/cache.h>
  21 #include <asm/fsl_pamu.h>
  22 #endif
  23 #include <dm/lists.h>
  24
  25 #define CIRC_CNT(head, tail, size)      (((head) - (tail)) & (size - 1))
  26 #define CIRC_SPACE(head, tail, size)    CIRC_CNT((tail), (head) + 1, (size))
  27
  28 uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
  29         0,
  30 #if defined(CONFIG_ARCH_C29X)
  31         CONFIG_SYS_FSL_SEC_IDX_OFFSET,
  32         2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
  33 #endif
  34 };
  35
  36 #define SEC_ADDR(idx)   \
  37         ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
  38
  39 #define SEC_JR0_ADDR(idx)       \
  40         (SEC_ADDR(idx) +        \
  41          (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
  42
  43 struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
  44
  45 static inline void start_jr0(uint8_t sec_idx)
  46 {
  47         ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  48         u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
  49         u32 scfgr = sec_in32(&sec->scfgr);
  50
  51         if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
  52                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
  53                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
  54                  */
  55                 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
  56                     (scfgr & SEC_SCFGR_VIRT_EN))
  57                         sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  58         } else {
  59                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
  60                 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
  61                         sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  62         }
  63 }
  64
  65 static inline void jr_reset_liodn(uint8_t sec_idx)
  66 {
  67         ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  68         sec_out32(&sec->jrliodnr[0].ls, 0);
  69 }
  70
  71 static inline void jr_disable_irq(uint8_t sec_idx)
  72 {
  73         struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  74         uint32_t jrcfg = sec_in32(&regs->jrcfg1);
  75
  76         jrcfg = jrcfg | JR_INTMASK;
  77
  78         sec_out32(&regs->jrcfg1, jrcfg);
  79 }
  80
  81 static void jr_initregs(uint8_t sec_idx)
  82 {
  83         struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  84         struct jobring *jr = &jr0[sec_idx];
  85         phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
  86         phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
  87
  88 #ifdef CONFIG_PHYS_64BIT
  89         sec_out32(&regs->irba_h, ip_base >> 32);
  90 #else
  91         sec_out32(&regs->irba_h, 0x0);
  92 #endif
  93         sec_out32(&regs->irba_l, (uint32_t)ip_base);
  94 #ifdef CONFIG_PHYS_64BIT
  95         sec_out32(&regs->orba_h, op_base >> 32);
  96 #else
  97         sec_out32(&regs->orba_h, 0x0);
  98 #endif
  99         sec_out32(&regs->orba_l, (uint32_t)op_base);
 100         sec_out32(&regs->ors, JR_SIZE);
 101         sec_out32(&regs->irs, JR_SIZE);
 102
 103         if (!jr->irq)
 104                 jr_disable_irq(sec_idx);
 105 }
 106
 107 static int jr_init(uint8_t sec_idx)
 108 {
 109         struct jobring *jr = &jr0[sec_idx];
 110
 111         memset(jr, 0, sizeof(struct jobring));
 112
 113         jr->jq_id = DEFAULT_JR_ID;
 114         jr->irq = DEFAULT_IRQ;
 115
 116 #ifdef CONFIG_FSL_CORENET
 117         jr->liodn = DEFAULT_JR_LIODN;
 118 #endif
 119         jr->size = JR_SIZE;
 120         jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
 121                                 JR_SIZE * sizeof(dma_addr_t));
 122         if (!jr->input_ring)
 123                 return -1;
 124
 125         jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
 126                               ARCH_DMA_MINALIGN);
 127         jr->output_ring =
 128             (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
 129         if (!jr->output_ring)
 130                 return -1;
 131
 132         memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
 133         memset(jr->output_ring, 0, jr->op_size);
 134
 135         start_jr0(sec_idx);
 136
 137         jr_initregs(sec_idx);
 138
 139         return 0;
 140 }
 141
 142 static int jr_sw_cleanup(uint8_t sec_idx)
 143 {
 144         struct jobring *jr = &jr0[sec_idx];
 145
 146         jr->head = 0;
 147         jr->tail = 0;
 148         jr->read_idx = 0;
 149         jr->write_idx = 0;
 150         memset(jr->info, 0, sizeof(jr->info));
 151         memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
 152         memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
 153
 154         return 0;
 155 }
 156
 157 static int jr_hw_reset(uint8_t sec_idx)
 158 {
 159         struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 160         uint32_t timeout = 100000;
 161         uint32_t jrint, jrcr;
 162
 163         sec_out32(&regs->jrcr, JRCR_RESET);
 164         do {
 165                 jrint = sec_in32(&regs->jrint);
 166         } while (((jrint & JRINT_ERR_HALT_MASK) ==
 167                   JRINT_ERR_HALT_INPROGRESS) && --timeout);
 168
 169         jrint = sec_in32(&regs->jrint);
 170         if (((jrint & JRINT_ERR_HALT_MASK) !=
 171              JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
 172                 return -1;
 173
 174         timeout = 100000;
 175         sec_out32(&regs->jrcr, JRCR_RESET);
 176         do {
 177                 jrcr = sec_in32(&regs->jrcr);
 178         } while ((jrcr & JRCR_RESET) && --timeout);
 179
 180         if (timeout == 0)
 181                 return -1;
 182
 183         return 0;
 184 }
 185
 186 /* -1 --- error, can't enqueue -- no space available */
 187 static int jr_enqueue(uint32_t *desc_addr,
 188                void (*callback)(uint32_t status, void *arg),
 189                void *arg, uint8_t sec_idx)
 190 {
 191         struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 192         struct jobring *jr = &jr0[sec_idx];
 193         int head = jr->head;
 194         uint32_t desc_word;
 195         int length = desc_len(desc_addr);
 196         int i;
 197 #ifdef CONFIG_PHYS_64BIT
 198         uint32_t *addr_hi, *addr_lo;
 199 #endif
 200
 201         /* The descriptor must be submitted to SEC block as per endianness
 202          * of the SEC Block.
 203          * So, if the endianness of Core and SEC block is different, each word
 204          * of the descriptor will be byte-swapped.
 205          */
 206         for (i = 0; i < length; i++) {
 207                 desc_word = desc_addr[i];
 208                 sec_out32((uint32_t *)&desc_addr[i], desc_word);
 209         }
 210
 211         phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
 212
 213         jr->info[head].desc_phys_addr = desc_phys_addr;
 214         jr->info[head].callback = (void *)callback;
 215         jr->info[head].arg = arg;
 216         jr->info[head].op_done = 0;
 217
 218         unsigned long start = (unsigned long)&jr->info[head] &
 219                                         ~(ARCH_DMA_MINALIGN - 1);
 220         unsigned long end = ALIGN((unsigned long)&jr->info[head] +
 221                                   sizeof(struct jr_info), ARCH_DMA_MINALIGN);
 222         flush_dcache_range(start, end);
 223
 224 #ifdef CONFIG_PHYS_64BIT
 225         /* Write the 64 bit Descriptor address on Input Ring.
 226          * The 32 bit hign and low part of the address will
 227          * depend on endianness of SEC block.
 228          */
 229 #ifdef CONFIG_SYS_FSL_SEC_LE
 230         addr_lo = (uint32_t *)(&jr->input_ring[head]);
 231         addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
 232 #elif defined(CONFIG_SYS_FSL_SEC_BE)
 233         addr_hi = (uint32_t *)(&jr->input_ring[head]);
 234         addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
 235 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 236
 237         sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
 238         sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
 239
 240 #else
 241         /* Write the 32 bit Descriptor address on Input Ring. */
 242         sec_out32(&jr->input_ring[head], desc_phys_addr);
 243 #endif /* ifdef CONFIG_PHYS_64BIT */
 244
 245         start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
 246         end = ALIGN((unsigned long)&jr->input_ring[head] +
 247                      sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
 248         flush_dcache_range(start, end);
 249
 250         jr->head = (head + 1) & (jr->size - 1);
 251
 252         /* Invalidate output ring */
 253         start = (unsigned long)jr->output_ring &
 254                                         ~(ARCH_DMA_MINALIGN - 1);
 255         end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
 256                     ARCH_DMA_MINALIGN);
 257         invalidate_dcache_range(start, end);
 258
 259         sec_out32(&regs->irja, 1);
 260
 261         return 0;
 262 }
 263
 264 static int jr_dequeue(int sec_idx)
 265 {
 266         struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 267         struct jobring *jr = &jr0[sec_idx];
 268         int head = jr->head;
 269         int tail = jr->tail;
 270         int idx, i, found;
 271         void (*callback)(uint32_t status, void *arg);
 272         void *arg = NULL;
 273 #ifdef CONFIG_PHYS_64BIT
 274         uint32_t *addr_hi, *addr_lo;
 275 #else
 276         uint32_t *addr;
 277 #endif
 278
 279         while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
 280                                                  jr->size)) {
 281
 282                 found = 0;
 283
 284                 phys_addr_t op_desc;
 285         #ifdef CONFIG_PHYS_64BIT
 286                 /* Read the 64 bit Descriptor address from Output Ring.
 287                  * The 32 bit hign and low part of the address will
 288                  * depend on endianness of SEC block.
 289                  */
 290         #ifdef CONFIG_SYS_FSL_SEC_LE
 291                 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
 292                 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 293         #elif defined(CONFIG_SYS_FSL_SEC_BE)
 294                 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
 295                 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 296         #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 297
 298                 op_desc = ((u64)sec_in32(addr_hi) << 32) |
 299                           ((u64)sec_in32(addr_lo));
 300
 301         #else
 302                 /* Read the 32 bit Descriptor address from Output Ring. */
 303                 addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
 304                 op_desc = sec_in32(addr);
 305         #endif /* ifdef CONFIG_PHYS_64BIT */
 306
 307                 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
 308
 309                 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
 310                         idx = (tail + i) & (jr->size - 1);
 311                         if (op_desc == jr->info[idx].desc_phys_addr) {
 312                                 found = 1;
 313                                 break;
 314                         }
 315                 }
 316
 317                 /* Error condition if match not found */
 318                 if (!found)
 319                         return -1;
 320
 321                 jr->info[idx].op_done = 1;
 322                 callback = (void *)jr->info[idx].callback;
 323                 arg = jr->info[idx].arg;
 324
 325                 /* When the job on tail idx gets done, increment
 326                  * tail till the point where job completed out of oredr has
 327                  * been taken into account
 328                  */
 329                 if (idx == tail)
 330                         do {
 331                                 tail = (tail + 1) & (jr->size - 1);
 332                         } while (jr->info[tail].op_done);
 333
 334                 jr->tail = tail;
 335                 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
 336
 337                 sec_out32(&regs->orjr, 1);
 338                 jr->info[idx].op_done = 0;
 339
 340                 callback(status, arg);
 341         }
 342
 343         return 0;
 344 }
 345
 346 static void desc_done(uint32_t status, void *arg)
 347 {
 348         struct result *x = arg;
 349         x->status = status;
 350 #ifndef CONFIG_SPL_BUILD
 351         caam_jr_strstatus(status);
 352 #endif
 353         x->done = 1;
 354 }
 355
 356 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 357 {
 358         unsigned long long timeval = get_ticks();
 359         unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
 360         struct result op;
 361         int ret = 0;
 362
 363         memset(&op, 0, sizeof(op));
 364
 365         ret = jr_enqueue(desc, desc_done, &op, sec_idx);
 366         if (ret) {
 367                 debug("Error in SEC enq\n");
 368                 ret = JQ_ENQ_ERR;
 369                 goto out;
 370         }
 371
 372         timeval = get_ticks();
 373         timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
 374         while (op.done != 1) {
 375                 ret = jr_dequeue(sec_idx);
 376                 if (ret) {
 377                         debug("Error in SEC deq\n");
 378                         ret = JQ_DEQ_ERR;
 379                         goto out;
 380                 }
 381
 382                 if ((get_ticks() - timeval) > timeout) {
 383                         debug("SEC Dequeue timed out\n");
 384                         ret = JQ_DEQ_TO_ERR;
 385                         goto out;
 386                 }
 387         }
 388
 389         if (op.status) {
 390                 debug("Error %x\n", op.status);
 391                 ret = op.status;
 392         }
 393 out:
 394         return ret;
 395 }
 396
 397 int run_descriptor_jr(uint32_t *desc)
 398 {
 399         return run_descriptor_jr_idx(desc, 0);
 400 }
 401
 402 static inline int jr_reset_sec(uint8_t sec_idx)
 403 {
 404         if (jr_hw_reset(sec_idx) < 0)
 405                 return -1;
 406
 407         /* Clean up the jobring structure maintained by software */
 408         jr_sw_cleanup(sec_idx);
 409
 410         return 0;
 411 }
 412
 413 int jr_reset(void)
 414 {
 415         return jr_reset_sec(0);
 416 }
 417
 418 static inline int sec_reset_idx(uint8_t sec_idx)
 419 {
 420         ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 421         uint32_t mcfgr = sec_in32(&sec->mcfgr);
 422         uint32_t timeout = 100000;
 423
 424         mcfgr |= MCFGR_SWRST;
 425         sec_out32(&sec->mcfgr, mcfgr);
 426
 427         mcfgr |= MCFGR_DMA_RST;
 428         sec_out32(&sec->mcfgr, mcfgr);
 429         do {
 430                 mcfgr = sec_in32(&sec->mcfgr);
 431         } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
 432
 433         if (timeout == 0)
 434                 return -1;
 435
 436         timeout = 100000;
 437         do {
 438                 mcfgr = sec_in32(&sec->mcfgr);
 439         } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
 440
 441         if (timeout == 0)
 442                 return -1;
 443
 444         return 0;
 445 }
 446 int sec_reset(void)
 447 {
 448         return sec_reset_idx(0);
 449 }
 450 #ifndef CONFIG_SPL_BUILD
 451 static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 452 {
 453         u32 *desc;
 454         int sh_idx, ret = 0;
 455         int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
 456
 457         desc = memalign(ARCH_DMA_MINALIGN, desc_size);
 458         if (!desc) {
 459                 debug("cannot allocate RNG init descriptor memory\n");
 460                 return -ENOMEM;
 461         }
 462
 463         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 464                 /*
 465                  * If the corresponding bit is set, then it means the state
 466                  * handle was initialized by us, and thus it needs to be
 467                  * deinitialized as well
 468                  */
 469
 470                 if (state_handle_mask & RDSTA_IF(sh_idx)) {
 471                         /*
 472                          * Create the descriptor for deinstantating this state
 473                          * handle.
 474                          */
 475                         inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
 476                         flush_dcache_range((unsigned long)desc,
 477                                            (unsigned long)desc + desc_size);
 478
 479                         ret = run_descriptor_jr_idx(desc, sec_idx);
 480                         if (ret) {
 481                                 printf("SEC%u:  RNG4 SH%d deinstantiation failed with error 0x%x\n",
 482                                        sec_idx, sh_idx, ret);
 483                                 ret = -EIO;
 484                                 break;
 485                         }
 486
 487                         printf("SEC%u:  Deinstantiated RNG4 SH%d\n",
 488                                sec_idx, sh_idx);
 489                 }
 490         }
 491
 492         free(desc);
 493         return ret;
 494 }
 495
 496 static int instantiate_rng(u8 sec_idx, int gen_sk)
 497 {
 498         u32 *desc;
 499         u32 rdsta_val;
 500         int ret = 0, sh_idx, size;
 501         ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 502         struct rng4tst __iomem *rng =
 503                         (struct rng4tst __iomem *)&sec->rng;
 504
 505         desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
 506         if (!desc) {
 507                 printf("cannot allocate RNG init descriptor memory\n");
 508                 return -1;
 509         }
 510
 511         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 512                 /*
 513                  * If the corresponding bit is set, this state handle
 514                  * was initialized by somebody else, so it's left alone.
 515                  */
 516                 rdsta_val = sec_in32(&rng->rdsta);
 517                 if (rdsta_val & (RDSTA_IF(sh_idx))) {
 518                         if (rdsta_val & RDSTA_PR(sh_idx))
 519                                 continue;
 520
 521                         printf("SEC%u:  RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
 522                                sec_idx, sh_idx);
 523
 524                         ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
 525                         if (ret)
 526                                 break;
 527                 }
 528
 529                 inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
 530                 size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
 531                 flush_dcache_range((unsigned long)desc,
 532                                    (unsigned long)desc + size);
 533
 534                 ret = run_descriptor_jr_idx(desc, sec_idx);
 535
 536                 if (ret)
 537                         printf("SEC%u:  RNG4 SH%d instantiation failed with error 0x%x\n",
 538                                sec_idx, sh_idx, ret);
 539
 540                 rdsta_val = sec_in32(&rng->rdsta);
 541                 if (!(rdsta_val & RDSTA_IF(sh_idx))) {
 542                         free(desc);
 543                         return -1;
 544                 }
 545
 546                 memset(desc, 0, sizeof(uint32_t) * 6);
 547         }
 548
 549         free(desc);
 550
 551         return ret;
 552 }
 553
 554 static u8 get_rng_vid(uint8_t sec_idx)
 555 {
 556         ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 557         u8 vid;
 558
 559         if (caam_get_era() < 10) {
 560                 vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
 561                        >> SEC_CHAVID_LS_RNG_SHIFT;
 562         } else {
 563                 vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
 564                        >> CHA_VER_VID_SHIFT;
 565         }
 566
 567         return vid;
 568 }
 569
 570 /*
 571  * By default, the TRNG runs for 200 clocks per sample;
 572  * 1200 clocks per sample generates better entropy.
 573  */
 574 static void kick_trng(int ent_delay, uint8_t sec_idx)
 575 {
 576         ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 577         struct rng4tst __iomem *rng =
 578                         (struct rng4tst __iomem *)&sec->rng;
 579         u32 val;
 580
 581         /* put RNG4 into program mode */
 582         sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
 583         /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
 584          * length (in system clocks) of each Entropy sample taken
 585          * */
 586         val = sec_in32(&rng->rtsdctl);
 587         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 588               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 589         sec_out32(&rng->rtsdctl, val);
 590         /* min. freq. count, equal to 1/4 of the entropy sample length */
 591         sec_out32(&rng->rtfreqmin, ent_delay >> 2);
 592         /* disable maximum frequency count */
 593         sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
 594         /*
 595          * select raw sampling in both entropy shifter
 596          * and statistical checker
 597          */
 598         sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
 599         /* put RNG4 into run mode */
 600         sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 601 }
 602
 603 static int rng_init(uint8_t sec_idx)
 604 {
 605         int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 606         ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 607         struct rng4tst __iomem *rng =
 608                         (struct rng4tst __iomem *)&sec->rng;
 609         u32 inst_handles;
 610
 611         gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
 612         do {
 613                 inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
 614
 615                 /*
 616                  * If either of the SH's were instantiated by somebody else
 617                  * then it is assumed that the entropy
 618                  * parameters are properly set and thus the function
 619                  * setting these (kick_trng(...)) is skipped.
 620                  * Also, if a handle was instantiated, do not change
 621                  * the TRNG parameters.
 622                  */
 623                 if (!inst_handles) {
 624                         kick_trng(ent_delay, sec_idx);
 625                         ent_delay += 400;
 626                 }
 627                 /*
 628                  * if instantiate_rng(...) fails, the loop will rerun
 629                  * and the kick_trng(...) function will modfiy the
 630                  * upper and lower limits of the entropy sampling
 631                  * interval, leading to a sucessful initialization of
 632                  * the RNG.
 633                  */
 634                 ret = instantiate_rng(sec_idx, gen_sk);
 635         } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 636         if (ret) {
 637                 printf("SEC%u:  Failed to instantiate RNG\n", sec_idx);
 638                 return ret;
 639         }
 640
 641          /* Enable RDB bit so that RNG works faster */
 642         sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
 643
 644         return ret;
 645 }
 646 #endif
 647 int sec_init_idx(uint8_t sec_idx)
 648 {
 649         ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 650         uint32_t mcr = sec_in32(&sec->mcfgr);
 651         int ret = 0;
 652
 653 #ifdef CONFIG_FSL_CORENET
 654         uint32_t liodnr;
 655         uint32_t liodn_ns;
 656         uint32_t liodn_s;
 657 #endif
 658
 659         if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
 660                 printf("SEC%u:  initialization failed\n", sec_idx);
 661                 return -1;
 662         }
 663
 664         /*
 665          * Modifying CAAM Read/Write Attributes
 666          * For LS2080A
 667          * For AXI Write - Cacheable, Write Back, Write allocate
 668          * For AXI Read - Cacheable, Read allocate
 669          * Only For LS2080a, to solve CAAM coherency issues
 670          */
 671 #ifdef CONFIG_ARCH_LS2080A
 672         mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
 673         mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
 674 #else
 675         mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
 676 #endif
 677
 678 #ifdef CONFIG_PHYS_64BIT
 679         mcr |= (1 << MCFGR_PS_SHIFT);
 680 #endif
 681         sec_out32(&sec->mcfgr, mcr);
 682
 683 #ifdef CONFIG_FSL_CORENET
 684 #ifdef CONFIG_SPL_BUILD
 685         /*
 686          * For SPL Build, Set the Liodns in SEC JR0 for
 687          * creating PAMU entries corresponding to these.
 688          * For normal build, these are set in set_liodns().
 689          */
 690         liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
 691         liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
 692
 693         liodnr = sec_in32(&sec->jrliodnr[0].ls) &
 694                  ~(JRNSLIODN_MASK | JRSLIODN_MASK);
 695         liodnr = liodnr |
 696                  (liodn_ns << JRNSLIODN_SHIFT) |
 697                  (liodn_s << JRSLIODN_SHIFT);
 698         sec_out32(&sec->jrliodnr[0].ls, liodnr);
 699 #else
 700         liodnr = sec_in32(&sec->jrliodnr[0].ls);
 701         liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
 702         liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 703 #endif
 704 #endif
 705
 706         ret = jr_init(sec_idx);
 707         if (ret < 0) {
 708                 printf("SEC%u:  initialization failed\n", sec_idx);
 709                 return -1;
 710         }
 711
 712 #ifdef CONFIG_FSL_CORENET
 713         ret = sec_config_pamu_table(liodn_ns, liodn_s);
 714         if (ret < 0)
 715                 return -1;
 716
 717         pamu_enable();
 718 #endif
 719 #ifndef CONFIG_SPL_BUILD
 720         if (get_rng_vid(sec_idx) >= 4) {
 721                 if (rng_init(sec_idx) < 0) {
 722                         printf("SEC%u:  RNG instantiation failed\n", sec_idx);
 723                         return -1;
 724                 }
 725
 726                 if (IS_ENABLED(CONFIG_DM_RNG)) {
 727                         ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
 728                                                  NULL);
 729                         if (ret)
 730                                 printf("Couldn't bind rng driver (%d)\n", ret);
 731                 }
 732
 733                 printf("SEC%u:  RNG instantiated\n", sec_idx);
 734         }
 735 #endif
 736         return ret;
 737 }
 738
 739 int sec_init(void)
 740 {
 741         return sec_init_idx(0);
 742 }