1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
9 #include <linux/device.h>
10 #include <linux/of_address.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/sys_soc.h>
14 #include <linux/fsl/mc.h>
21 #include "desc_constr.h"
25 EXPORT_SYMBOL(caam_dpaa2);
32 * Descriptor to instantiate RNG State Handle 0 in normal mode and
33 * load the JDKEK, TDKEK and TDSK registers
35 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
37 u32 *jump_cmd, op_flags;
39 init_job_desc(desc, 0);
41 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
42 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
45 /* INIT RNG in non-test mode */
46 append_operation(desc, op_flags);
48 if (!handle && do_sk) {
50 * For SH0, Secure Keys must be generated as well
54 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
55 set_jump_tgt_here(desc, jump_cmd);
58 * load 1 to clear written reg:
59 * resets the done interrupt and returns the RNG to idle.
61 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
63 /* Initialize State Handle */
64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
68 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
71 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
72 static void build_deinstantiation_desc(u32 *desc, int handle)
74 init_job_desc(desc, 0);
76 /* Uninstantiate State Handle 0 */
77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
78 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
80 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
83 static const struct of_device_id imx8m_machine_match[] = {
84 { .compatible = "fsl,imx8mm", },
85 { .compatible = "fsl,imx8mn", },
86 { .compatible = "fsl,imx8mp", },
87 { .compatible = "fsl,imx8mq", },
88 { .compatible = "fsl,imx8ulp", },
93 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
94 * the software (no JR/QI used).
95 * @ctrldev - pointer to device
96 * @status - descriptor status, after being run
98 * Return: - 0 if no error occurred
99 * - -ENODEV if the DECO couldn't be acquired
100 * - -EAGAIN if an error occurred while executing the descriptor
102 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
105 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
106 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
107 struct caam_deco __iomem *deco = ctrlpriv->deco;
108 unsigned int timeout = 100000;
109 u32 deco_dbg_reg, deco_state, flags;
113 if (ctrlpriv->virt_en == 1 ||
115 * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
116 * and the following steps should be performed regardless
118 of_match_node(imx8m_machine_match, of_root)) {
119 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
121 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
128 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
130 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
135 dev_err(ctrldev, "failed to acquire DECO 0\n");
136 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
140 for (i = 0; i < desc_len(desc); i++)
141 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
143 flags = DECO_JQCR_WHL;
145 * If the descriptor length is longer than 4 words, then the
146 * FOUR bit in JRCTRL register must be set.
148 if (desc_len(desc) >= 4)
149 flags |= DECO_JQCR_FOUR;
151 /* Instruct the DECO to execute it */
152 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
156 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
158 if (ctrlpriv->era < 10)
159 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
160 DESC_DBG_DECO_STAT_SHIFT;
162 deco_state = (rd_reg32(&deco->dbg_exec) &
163 DESC_DER_DECO_STAT_MASK) >>
164 DESC_DER_DECO_STAT_SHIFT;
167 * If an error occurred in the descriptor, then
168 * the DECO status field will be set to 0x0D
170 if (deco_state == DECO_STAT_HOST_ERR)
174 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
176 *status = rd_reg32(&deco->op_status_hi) &
177 DECO_OP_STATUS_HI_ERR_MASK;
179 if (ctrlpriv->virt_en == 1)
180 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
182 /* Mark the DECO as free */
183 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
192 * deinstantiate_rng - builds and executes a descriptor on DECO0,
193 * which deinitializes the RNG block.
194 * @ctrldev - pointer to device
195 * @state_handle_mask - bitmask containing the instantiation status
196 * for the RNG4 state handles which exist in
197 * the RNG4 block: 1 if it's been instantiated
199 * Return: - 0 if no error occurred
200 * - -ENOMEM if there isn't enough memory to allocate the descriptor
201 * - -ENODEV if DECO0 couldn't be acquired
202 * - -EAGAIN if an error occurred when executing the descriptor
204 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
209 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
213 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
215 * If the corresponding bit is set, then it means the state
216 * handle was initialized by us, and thus it needs to be
217 * deinitialized as well
219 if ((1 << sh_idx) & state_handle_mask) {
221 * Create the descriptor for deinstantating this state
224 build_deinstantiation_desc(desc, sh_idx);
226 /* Try to run it through DECO0 */
227 ret = run_descriptor_deco0(ctrldev, desc, &status);
230 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
232 "Failed to deinstantiate RNG4 SH%d\n",
236 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
245 static void devm_deinstantiate_rng(void *data)
247 struct device *ctrldev = data;
248 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
251 * De-initialize RNG state handles initialized by this driver.
252 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
254 if (ctrlpriv->rng4_sh_init)
255 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
259 * instantiate_rng - builds and executes a descriptor on DECO0,
260 * which initializes the RNG block.
261 * @ctrldev - pointer to device
262 * @state_handle_mask - bitmask containing the instantiation status
263 * for the RNG4 state handles which exist in
264 * the RNG4 block: 1 if it's been instantiated
265 * by an external entry, 0 otherwise.
266 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
267 * Caution: this can be done only once; if the keys need to be
268 * regenerated, a POR is required
270 * Return: - 0 if no error occurred
271 * - -ENOMEM if there isn't enough memory to allocate the descriptor
272 * - -ENODEV if DECO0 couldn't be acquired
273 * - -EAGAIN if an error occurred when executing the descriptor
274 * f.i. there was a RNG hardware error due to not "good enough"
275 * entropy being acquired.
277 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
280 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
281 struct caam_ctrl __iomem *ctrl;
282 u32 *desc, status = 0, rdsta_val;
285 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
286 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
290 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
291 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
292 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
293 const u32 rdsta_mask = rdsta_if | rdsta_pr;
295 /* Clear the contents before using the descriptor */
296 memset(desc, 0x00, CAAM_CMD_SZ * 7);
299 * If the corresponding bit is set, this state handle
300 * was initialized by somebody else, so it's left alone.
302 if (rdsta_if & state_handle_mask) {
303 if (rdsta_pr & state_handle_mask)
307 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
310 ret = deinstantiate_rng(ctrldev, rdsta_if);
315 /* Create the descriptor for instantiating RNG State Handle */
316 build_instantiation_desc(desc, sh_idx, gen_sk);
318 /* Try to run it through DECO0 */
319 ret = run_descriptor_deco0(ctrldev, desc, &status);
322 * If ret is not 0, or descriptor status is not 0, then
323 * something went wrong. No need to try the next state
324 * handle (if available), bail out here.
325 * Also, if for some reason, the State Handle didn't get
326 * instantiated although the descriptor has finished
327 * without any error (HW optimizations for later
328 * CAAM eras), then try again.
333 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
334 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
335 (rdsta_val & rdsta_mask) != rdsta_mask) {
340 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
348 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
352 * kick_trng - sets the various parameters for enabling the initialization
353 * of the RNG4 block in CAAM
354 * @dev - pointer to the controller device
355 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
357 static void kick_trng(struct device *dev, int ent_delay)
359 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
360 struct caam_ctrl __iomem *ctrl;
361 struct rng4tst __iomem *r4tst;
364 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
365 r4tst = &ctrl->r4tst[0];
368 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
369 * properly invalidate the entropy in the entropy register and
370 * force re-generation.
372 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
375 * Performance-wise, it does not make sense to
376 * set the delay to a value that is lower
377 * than the last one that worked (i.e. the state handles
378 * were instantiated properly).
380 rtsdctl = rd_reg32(&r4tst->rtsdctl);
381 val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
382 if (ent_delay > val) {
384 /* min. freq. count, equal to 1/4 of the entropy sample length */
385 wr_reg32(&r4tst->rtfrqmin, val >> 2);
386 /* disable maximum frequency count */
387 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
390 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
391 RTSDCTL_SAMP_SIZE_VAL);
394 * To avoid reprogramming the self-test parameters over and over again,
395 * use RTSDCTL[SAMP_SIZE] as an indicator.
397 if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
398 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
399 wr_reg32(&r4tst->rtpkrrng, 570);
400 wr_reg32(&r4tst->rtpkrmax, 1600);
401 wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
402 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
403 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
404 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
405 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
406 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
407 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
411 * select raw sampling in both entropy shifter
412 * and statistical checker; ; put RNG4 into run mode
414 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
415 RTMCTL_SAMP_MODE_RAW_ES_SC);
418 static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
420 static const struct {
444 ccbvid = rd_reg32(&perfmon->ccb_id);
445 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
446 if (era) /* This is '0' prior to CAAM ERA-6 */
449 id_ms = rd_reg32(&perfmon->caam_id_ms);
450 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
451 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
453 for (i = 0; i < ARRAY_SIZE(id); i++)
454 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
461 * caam_get_era() - Return the ERA of the SEC on SoC, based
462 * on "sec-era" optional property in the DTS. This property is updated
464 * In case this property is not passed an attempt to retrieve the CAAM
465 * era via register reads will be made.
467 * @perfmon: Performance Monitor Registers
469 static int caam_get_era(struct caam_perfmon __iomem *perfmon)
471 struct device_node *caam_node;
475 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
476 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
477 of_node_put(caam_node);
482 return caam_get_era_from_hw(perfmon);
486 * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
487 * have an issue wherein AXI bus transactions may not occur in the correct
488 * order. This isn't a problem running single descriptors, but can be if
489 * running multiple concurrent descriptors. Reworking the driver to throttle
490 * to single requests is impractical, thus the workaround is to limit the AXI
491 * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
494 static void handle_imx6_err005766(u32 __iomem *mcr)
496 if (of_machine_is_compatible("fsl,imx6q") ||
497 of_machine_is_compatible("fsl,imx6dl") ||
498 of_machine_is_compatible("fsl,imx6qp"))
499 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
500 1 << MCFGR_AXIPIPE_SHIFT);
503 static const struct of_device_id caam_match[] = {
505 .compatible = "fsl,sec-v4.0",
508 .compatible = "fsl,sec4.0",
512 MODULE_DEVICE_TABLE(of, caam_match);
514 struct caam_imx_data {
515 const struct clk_bulk_data *clks;
519 static const struct clk_bulk_data caam_imx6_clks[] = {
523 { .id = "emi_slow" },
526 static const struct caam_imx_data caam_imx6_data = {
527 .clks = caam_imx6_clks,
528 .num_clks = ARRAY_SIZE(caam_imx6_clks),
531 static const struct clk_bulk_data caam_imx7_clks[] = {
536 static const struct caam_imx_data caam_imx7_data = {
537 .clks = caam_imx7_clks,
538 .num_clks = ARRAY_SIZE(caam_imx7_clks),
541 static const struct clk_bulk_data caam_imx6ul_clks[] = {
547 static const struct caam_imx_data caam_imx6ul_data = {
548 .clks = caam_imx6ul_clks,
549 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
552 static const struct clk_bulk_data caam_vf610_clks[] = {
556 static const struct caam_imx_data caam_vf610_data = {
557 .clks = caam_vf610_clks,
558 .num_clks = ARRAY_SIZE(caam_vf610_clks),
561 static const struct soc_device_attribute caam_imx_soc_table[] = {
562 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
563 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
564 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
565 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
566 { .soc_id = "VF*", .data = &caam_vf610_data },
567 { .family = "Freescale i.MX" },
571 static void disable_clocks(void *data)
573 struct caam_drv_private *ctrlpriv = data;
575 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
578 static int init_clocks(struct device *dev, const struct caam_imx_data *data)
580 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
583 ctrlpriv->num_clks = data->num_clks;
584 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
585 data->num_clks * sizeof(data->clks[0]),
590 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
593 "Failed to request all necessary clocks\n");
597 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
600 "Failed to prepare/enable all necessary clocks\n");
604 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
607 static void caam_remove_debugfs(void *root)
609 debugfs_remove_recursive(root);
612 #ifdef CONFIG_FSL_MC_BUS
613 static bool check_version(struct fsl_mc_version *mc_version, u32 major,
614 u32 minor, u32 revision)
616 if (mc_version->major > major)
619 if (mc_version->major == major) {
620 if (mc_version->minor > minor)
623 if (mc_version->minor == minor &&
624 mc_version->revision > revision)
632 static bool needs_entropy_delay_adjustment(void)
634 if (of_machine_is_compatible("fsl,imx6sx"))
639 static int caam_ctrl_rng_init(struct device *dev)
641 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
642 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
643 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
646 if (ctrlpriv->era < 10) {
647 struct caam_perfmon __iomem *perfmon;
649 perfmon = ctrlpriv->total_jobrs ?
650 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
651 (struct caam_perfmon __iomem *)&ctrl->perfmon;
653 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
654 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
656 struct version_regs __iomem *vreg;
658 vreg = ctrlpriv->total_jobrs ?
659 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
660 (struct version_regs __iomem *)&ctrl->vreg;
662 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
667 * If SEC has RNG version >= 4 and RNG state handle has not been
668 * already instantiated, do RNG instantiation
669 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
671 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {
672 ctrlpriv->rng4_sh_init =
673 rd_reg32(&ctrl->r4tst[0].rdsta);
675 * If the secure keys (TDKEK, JDKEK, TDSK), were already
676 * generated, signal this to the function that is instantiating
677 * the state handles. An error would occur if RNG4 attempts
678 * to regenerate these keys before the next POR.
680 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
681 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
684 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
686 * If either SH were instantiated by somebody else
687 * (e.g. u-boot) then it is assumed that the entropy
688 * parameters are properly set and thus the function
689 * setting these (kick_trng(...)) is skipped.
690 * Also, if a handle was instantiated, do not change
691 * the TRNG parameters.
693 if (needs_entropy_delay_adjustment())
695 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
697 "Entropy delay = %u\n",
699 kick_trng(dev, ent_delay);
703 * if instantiate_rng(...) fails, the loop will rerun
704 * and the kick_trng(...) function will modify the
705 * upper and lower limits of the entropy sampling
706 * interval, leading to a successful initialization of
709 ret = instantiate_rng(dev, inst_handles,
712 * Entropy delay is determined via TRNG characterization.
713 * TRNG characterization is run across different voltages
715 * If worst case value for ent_dly is identified,
716 * the loop can be skipped for that platform.
718 if (needs_entropy_delay_adjustment())
722 * if here, the loop will rerun,
723 * so don't hog the CPU
726 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
728 dev_err(dev, "failed to instantiate RNG");
732 * Set handles initialized by this module as the complement of
733 * the already initialized ones
735 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
737 /* Enable RDB bit so that RNG works faster */
738 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
744 /* Indicate if the internal state of the CAAM is lost during PM */
745 static int caam_off_during_pm(void)
747 bool not_off_during_pm = of_machine_is_compatible("fsl,imx6q") ||
748 of_machine_is_compatible("fsl,imx6qp") ||
749 of_machine_is_compatible("fsl,imx6dl");
751 return not_off_during_pm ? 0 : 1;
754 static void caam_state_save(struct device *dev)
756 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
757 struct caam_ctl_state *state = &ctrlpriv->state;
758 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
759 u32 deco_inst, jr_inst;
762 state->mcr = rd_reg32(&ctrl->mcr);
763 state->scfgr = rd_reg32(&ctrl->scfgr);
765 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
766 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
767 for (i = 0; i < deco_inst; i++) {
768 state->deco_mid[i].liodn_ms =
769 rd_reg32(&ctrl->deco_mid[i].liodn_ms);
770 state->deco_mid[i].liodn_ls =
771 rd_reg32(&ctrl->deco_mid[i].liodn_ls);
774 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
775 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
776 for (i = 0; i < jr_inst; i++) {
777 state->jr_mid[i].liodn_ms =
778 rd_reg32(&ctrl->jr_mid[i].liodn_ms);
779 state->jr_mid[i].liodn_ls =
780 rd_reg32(&ctrl->jr_mid[i].liodn_ls);
784 static void caam_state_restore(const struct device *dev)
786 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
787 const struct caam_ctl_state *state = &ctrlpriv->state;
788 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
789 u32 deco_inst, jr_inst;
792 wr_reg32(&ctrl->mcr, state->mcr);
793 wr_reg32(&ctrl->scfgr, state->scfgr);
795 deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
796 CHA_ID_MS_DECO_MASK) >> CHA_ID_MS_DECO_SHIFT;
797 for (i = 0; i < deco_inst; i++) {
798 wr_reg32(&ctrl->deco_mid[i].liodn_ms,
799 state->deco_mid[i].liodn_ms);
800 wr_reg32(&ctrl->deco_mid[i].liodn_ls,
801 state->deco_mid[i].liodn_ls);
804 jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &
805 CHA_ID_MS_JR_MASK) >> CHA_ID_MS_JR_SHIFT;
806 for (i = 0; i < jr_inst; i++) {
807 wr_reg32(&ctrl->jr_mid[i].liodn_ms,
808 state->jr_mid[i].liodn_ms);
809 wr_reg32(&ctrl->jr_mid[i].liodn_ls,
810 state->jr_mid[i].liodn_ls);
813 if (ctrlpriv->virt_en == 1)
814 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
815 JRSTART_JR1_START | JRSTART_JR2_START |
819 static int caam_ctrl_suspend(struct device *dev)
821 const struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
823 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en)
824 caam_state_save(dev);
829 static int caam_ctrl_resume(struct device *dev)
831 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
834 if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) {
835 caam_state_restore(dev);
837 /* HW and rng will be reset so deinstantiation can be removed */
838 devm_remove_action(dev, devm_deinstantiate_rng, dev);
839 ret = caam_ctrl_rng_init(dev);
845 static DEFINE_SIMPLE_DEV_PM_OPS(caam_ctrl_pm_ops, caam_ctrl_suspend, caam_ctrl_resume);
847 /* Probe routine for CAAM top (controller) level */
848 static int caam_probe(struct platform_device *pdev)
852 const struct soc_device_attribute *imx_soc_match;
854 struct device_node *nprop, *np;
855 struct caam_ctrl __iomem *ctrl;
856 struct caam_drv_private *ctrlpriv;
857 struct caam_perfmon __iomem *perfmon;
858 struct dentry *dfs_root;
859 u32 scfgr, comp_params;
861 int BLOCK_OFFSET = 0;
862 bool reg_access = true;
864 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
869 dev_set_drvdata(dev, ctrlpriv);
870 nprop = pdev->dev.of_node;
872 imx_soc_match = soc_device_match(caam_imx_soc_table);
873 if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root))
874 return -EPROBE_DEFER;
876 caam_imx = (bool)imx_soc_match;
878 ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();
882 * Until Layerscape and i.MX OP-TEE get in sync,
883 * only i.MX OP-TEE use cases disallow access to
884 * caam page 0 (controller) registers.
886 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
887 ctrlpriv->optee_en = !!np;
890 reg_access = !ctrlpriv->optee_en;
892 if (!imx_soc_match->data) {
893 dev_err(dev, "No clock data provided for i.MX SoC");
897 ret = init_clocks(dev, imx_soc_match->data);
903 /* Get configuration properties from device tree */
904 /* First, get register page */
905 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
906 ret = PTR_ERR_OR_ZERO(ctrl);
908 dev_err(dev, "caam: of_iomap() failed\n");
913 for_each_available_child_of_node(nprop, np)
914 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
915 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
918 if (of_property_read_u32_index(np, "reg", 0, ®)) {
919 dev_err(dev, "%s read reg property error\n",
924 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
925 ((__force uint8_t *)ctrl + reg);
927 ctrlpriv->total_jobrs++;
932 * Wherever possible, instead of accessing registers from the global page,
933 * use the alias registers in the first (cf. DT nodes order)
936 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
937 (struct caam_perfmon __iomem *)&ctrl->perfmon;
939 caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
940 (CSTA_PLEND | CSTA_ALT_PLEND));
941 comp_params = rd_reg32(&perfmon->comp_parms_ms);
942 if (reg_access && comp_params & CTPR_MS_PS &&
943 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
944 caam_ptr_sz = sizeof(u64);
946 caam_ptr_sz = sizeof(u32);
947 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
948 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
950 #ifdef CONFIG_CAAM_QI
951 /* If (DPAA 1.x) QI present, check whether dependencies are available */
952 if (ctrlpriv->qi_present && !caam_dpaa2) {
953 ret = qman_is_probed();
955 return -EPROBE_DEFER;
956 } else if (ret < 0) {
957 dev_err(dev, "failing probe due to qman probe error\n");
961 ret = qman_portals_probed();
963 return -EPROBE_DEFER;
964 } else if (ret < 0) {
965 dev_err(dev, "failing probe due to qman portals probe error\n");
971 /* Allocating the BLOCK_OFFSET based on the supported page size on
974 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
976 BLOCK_OFFSET = PG_SIZE_4K;
978 BLOCK_OFFSET = PG_SIZE_64K;
980 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
981 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
982 ((__force uint8_t *)ctrl +
983 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
985 ctrlpriv->deco = (struct caam_deco __iomem __force *)
986 ((__force uint8_t *)ctrl +
987 BLOCK_OFFSET * DECO_BLOCK_NUMBER
990 /* Get the IRQ of the controller (for security violations only) */
991 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
992 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
993 ctrlpriv->mc_en = !!np;
996 #ifdef CONFIG_FSL_MC_BUS
997 if (ctrlpriv->mc_en) {
998 struct fsl_mc_version *mc_version;
1000 mc_version = fsl_mc_get_version();
1002 ctrlpriv->pr_support = check_version(mc_version, 10, 20,
1005 return -EPROBE_DEFER;
1013 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
1014 * long pointers in master configuration register.
1015 * In case of SoCs with Management Complex, MC f/w performs
1016 * the configuration.
1018 if (!ctrlpriv->mc_en)
1019 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
1020 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
1021 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
1023 handle_imx6_err005766(&ctrl->mcr);
1026 * Read the Compile Time parameters and SCFGR to determine
1027 * if virtualization is enabled for this platform
1029 scfgr = rd_reg32(&ctrl->scfgr);
1031 ctrlpriv->virt_en = 0;
1032 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
1033 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
1034 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
1036 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
1037 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
1038 (scfgr & SCFGR_VIRT_EN)))
1039 ctrlpriv->virt_en = 1;
1041 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
1042 if (comp_params & CTPR_MS_VIRT_EN_POR)
1043 ctrlpriv->virt_en = 1;
1046 if (ctrlpriv->virt_en == 1)
1047 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
1048 JRSTART_JR1_START | JRSTART_JR2_START |
1052 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
1054 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
1058 ctrlpriv->era = caam_get_era(perfmon);
1059 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
1061 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
1062 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1063 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
1069 caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
1071 /* Check to see if (DPAA 1.x) QI present. If so, enable */
1072 if (ctrlpriv->qi_present && !caam_dpaa2) {
1073 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
1074 ((__force uint8_t *)ctrl +
1075 BLOCK_OFFSET * QI_BLOCK_NUMBER
1077 /* This is all that's required to physically enable QI */
1078 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
1080 /* If QMAN driver is present, init CAAM-QI backend */
1081 #ifdef CONFIG_CAAM_QI
1082 ret = caam_qi_init(pdev);
1084 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
1088 /* If no QI and no rings specified, quit and go home */
1089 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
1090 dev_err(dev, "no queues configured, terminating\n");
1094 comp_params = rd_reg32(&perfmon->comp_parms_ls);
1095 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);
1098 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,
1099 * but fail when actually using it due to missing AES support, so
1102 if (ctrlpriv->era < 10) {
1103 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1104 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
1106 struct version_regs __iomem *vreg;
1108 vreg = ctrlpriv->total_jobrs ?
1109 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
1110 (struct version_regs __iomem *)&ctrl->vreg;
1112 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1113 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
1117 ret = caam_ctrl_rng_init(dev);
1122 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
1123 (u64)rd_reg32(&perfmon->caam_id_ls);
1125 /* Report "alive" for developer to see */
1126 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
1128 dev_info(dev, "job rings = %d, qi = %d\n",
1129 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
1131 ret = devm_of_platform_populate(dev);
1133 dev_err(dev, "JR platform devices creation error\n");
1138 static struct platform_driver caam_driver = {
1141 .of_match_table = caam_match,
1142 .pm = pm_ptr(&caam_ctrl_pm_ops),
1144 .probe = caam_probe,
1147 module_platform_driver(caam_driver);
1149 MODULE_LICENSE("GPL");
1150 MODULE_DESCRIPTION("FSL CAAM request backend");
1151 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");