drivers/crypto/caam/ctrl.c

   1 /* * CAAM control-plane driver backend
   2  * Controller-level driver, kernel property detection, initialization
   3  *
   4  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/device.h>
   8 #include <linux/of_address.h>
   9 #include <linux/of_irq.h>
  10
  11 #include "compat.h"
  12 #include "regs.h"
  13 #include "intern.h"
  14 #include "jr.h"
  15 #include "desc_constr.h"
  16 #include "error.h"
  17 #include "ctrl.h"
  18
  19 bool caam_little_end;
  20 EXPORT_SYMBOL(caam_little_end);
  21
  22 /*
  23  * i.MX targets tend to have clock control subsystems that can
  24  * enable/disable clocking to our device.
  25  */
  26 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
  27 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  28                                                 char *clk_name)
  29 {
  30         return devm_clk_get(dev, clk_name);
  31 }
  32 #else
  33 static inline struct clk *caam_drv_identify_clk(struct device *dev,
  34                                                 char *clk_name)
  35 {
  36         return NULL;
  37 }
  38 #endif
  39
  40 /*
  41  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  42  * load the JDKEK, TDKEK and TDSK registers
  43  */
  44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  45 {
  46         u32 *jump_cmd, op_flags;
  47
  48         init_job_desc(desc, 0);
  49
  50         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  51                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  52
  53         /* INIT RNG in non-test mode */
  54         append_operation(desc, op_flags);
  55
  56         if (!handle && do_sk) {
  57                 /*
  58                  * For SH0, Secure Keys must be generated as well
  59                  */
  60
  61                 /* wait for done */
  62                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  63                 set_jump_tgt_here(desc, jump_cmd);
  64
  65                 /*
  66                  * load 1 to clear written reg:
  67                  * resets the done interrrupt and returns the RNG to idle.
  68                  */
  69                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  70
  71                 /* Initialize State Handle  */
  72                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  73                                  OP_ALG_AAI_RNG4_SK);
  74         }
  75
  76         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  77 }
  78
  79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  80 static void build_deinstantiation_desc(u32 *desc, int handle)
  81 {
  82         init_job_desc(desc, 0);
  83
  84         /* Uninstantiate State Handle 0 */
  85         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  86                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  87
  88         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  89 }
  90
  91 /*
  92  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  93  *                        the software (no JR/QI used).
  94  * @ctrldev - pointer to device
  95  * @status - descriptor status, after being run
  96  *
  97  * Return: - 0 if no error occurred
  98  *         - -ENODEV if the DECO couldn't be acquired
  99  *         - -EAGAIN if an error occurred while executing the descriptor
 100  */
 101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
 102                                         u32 *status)
 103 {
 104         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 105         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
 106         struct caam_deco __iomem *deco = ctrlpriv->deco;
 107         unsigned int timeout = 100000;
 108         u32 deco_dbg_reg, flags;
 109         int i;
 110
 111
 112         if (ctrlpriv->virt_en == 1) {
 113                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 114
 115                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 116                        --timeout)
 117                         cpu_relax();
 118
 119                 timeout = 100000;
 120         }
 121
 122         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 123
 124         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 125                                                                  --timeout)
 126                 cpu_relax();
 127
 128         if (!timeout) {
 129                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 130                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 131                 return -ENODEV;
 132         }
 133
 134         for (i = 0; i < desc_len(desc); i++)
 135                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 136
 137         flags = DECO_JQCR_WHL;
 138         /*
 139          * If the descriptor length is longer than 4 words, then the
 140          * FOUR bit in JRCTRL register must be set.
 141          */
 142         if (desc_len(desc) >= 4)
 143                 flags |= DECO_JQCR_FOUR;
 144
 145         /* Instruct the DECO to execute it */
 146         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 147
 148         timeout = 10000000;
 149         do {
 150                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 151                 /*
 152                  * If an error occured in the descriptor, then
 153                  * the DECO status field will be set to 0x0D
 154                  */
 155                 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
 156                     DESC_DBG_DECO_STAT_HOST_ERR)
 157                         break;
 158                 cpu_relax();
 159         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 160
 161         *status = rd_reg32(&deco->op_status_hi) &
 162                   DECO_OP_STATUS_HI_ERR_MASK;
 163
 164         if (ctrlpriv->virt_en == 1)
 165                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 166
 167         /* Mark the DECO as free */
 168         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 169
 170         if (!timeout)
 171                 return -EAGAIN;
 172
 173         return 0;
 174 }
 175
 176 /*
 177  * instantiate_rng - builds and executes a descriptor on DECO0,
 178  *                   which initializes the RNG block.
 179  * @ctrldev - pointer to device
 180  * @state_handle_mask - bitmask containing the instantiation status
 181  *                      for the RNG4 state handles which exist in
 182  *                      the RNG4 block: 1 if it's been instantiated
 183  *                      by an external entry, 0 otherwise.
 184  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 185  *            Caution: this can be done only once; if the keys need to be
 186  *            regenerated, a POR is required
 187  *
 188  * Return: - 0 if no error occurred
 189  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 190  *         - -ENODEV if DECO0 couldn't be acquired
 191  *         - -EAGAIN if an error occurred when executing the descriptor
 192  *            f.i. there was a RNG hardware error due to not "good enough"
 193  *            entropy being aquired.
 194  */
 195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 196                            int gen_sk)
 197 {
 198         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 199         struct caam_ctrl __iomem *ctrl;
 200         u32 *desc, status = 0, rdsta_val;
 201         int ret = 0, sh_idx;
 202
 203         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 204         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 205         if (!desc)
 206                 return -ENOMEM;
 207
 208         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 209                 /*
 210                  * If the corresponding bit is set, this state handle
 211                  * was initialized by somebody else, so it's left alone.
 212                  */
 213                 if ((1 << sh_idx) & state_handle_mask)
 214                         continue;
 215
 216                 /* Create the descriptor for instantiating RNG State Handle */
 217                 build_instantiation_desc(desc, sh_idx, gen_sk);
 218
 219                 /* Try to run it through DECO0 */
 220                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 221
 222                 /*
 223                  * If ret is not 0, or descriptor status is not 0, then
 224                  * something went wrong. No need to try the next state
 225                  * handle (if available), bail out here.
 226                  * Also, if for some reason, the State Handle didn't get
 227                  * instantiated although the descriptor has finished
 228                  * without any error (HW optimizations for later
 229                  * CAAM eras), then try again.
 230                  */
 231                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 232                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 233                     !(rdsta_val & (1 << sh_idx)))
 234                         ret = -EAGAIN;
 235                 if (ret)
 236                         break;
 237                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 238                 /* Clear the contents before recreating the descriptor */
 239                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 240         }
 241
 242         kfree(desc);
 243
 244         return ret;
 245 }
 246
 247 /*
 248  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 249  *                     which deinitializes the RNG block.
 250  * @ctrldev - pointer to device
 251  * @state_handle_mask - bitmask containing the instantiation status
 252  *                      for the RNG4 state handles which exist in
 253  *                      the RNG4 block: 1 if it's been instantiated
 254  *
 255  * Return: - 0 if no error occurred
 256  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 257  *         - -ENODEV if DECO0 couldn't be acquired
 258  *         - -EAGAIN if an error occurred when executing the descriptor
 259  */
 260 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 261 {
 262         u32 *desc, status;
 263         int sh_idx, ret = 0;
 264
 265         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 266         if (!desc)
 267                 return -ENOMEM;
 268
 269         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 270                 /*
 271                  * If the corresponding bit is set, then it means the state
 272                  * handle was initialized by us, and thus it needs to be
 273                  * deintialized as well
 274                  */
 275                 if ((1 << sh_idx) & state_handle_mask) {
 276                         /*
 277                          * Create the descriptor for deinstantating this state
 278                          * handle
 279                          */
 280                         build_deinstantiation_desc(desc, sh_idx);
 281
 282                         /* Try to run it through DECO0 */
 283                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 284
 285                         if (ret || status) {
 286                                 dev_err(ctrldev,
 287                                         "Failed to deinstantiate RNG4 SH%d\n",
 288                                         sh_idx);
 289                                 break;
 290                         }
 291                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 292                 }
 293         }
 294
 295         kfree(desc);
 296
 297         return ret;
 298 }
 299
 300 static int caam_remove(struct platform_device *pdev)
 301 {
 302         struct device *ctrldev;
 303         struct caam_drv_private *ctrlpriv;
 304         struct caam_ctrl __iomem *ctrl;
 305         int ring;
 306
 307         ctrldev = &pdev->dev;
 308         ctrlpriv = dev_get_drvdata(ctrldev);
 309         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 310
 311         /* Remove platform devices for JobRs */
 312         for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
 313                 if (ctrlpriv->jrpdev[ring])
 314                         of_device_unregister(ctrlpriv->jrpdev[ring]);
 315         }
 316
 317         /* De-initialize RNG state handles initialized by this driver. */
 318         if (ctrlpriv->rng4_sh_init)
 319                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 320
 321         /* Shut down debug views */
 322 #ifdef CONFIG_DEBUG_FS
 323         debugfs_remove_recursive(ctrlpriv->dfs_root);
 324 #endif
 325
 326         /* Unmap controller region */
 327         iounmap(ctrl);
 328
 329         /* shut clocks off before finalizing shutdown */
 330         clk_disable_unprepare(ctrlpriv->caam_ipg);
 331         clk_disable_unprepare(ctrlpriv->caam_mem);
 332         clk_disable_unprepare(ctrlpriv->caam_aclk);
 333         if (ctrlpriv->caam_emi_slow)
 334                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 335         return 0;
 336 }
 337
 338 /*
 339  * kick_trng - sets the various parameters for enabling the initialization
 340  *             of the RNG4 block in CAAM
 341  * @pdev - pointer to the platform device
 342  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 343  */
 344 static void kick_trng(struct platform_device *pdev, int ent_delay)
 345 {
 346         struct device *ctrldev = &pdev->dev;
 347         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 348         struct caam_ctrl __iomem *ctrl;
 349         struct rng4tst __iomem *r4tst;
 350         u32 val;
 351
 352         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 353         r4tst = &ctrl->r4tst[0];
 354
 355         /* put RNG4 into program mode */
 356         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 357
 358         /*
 359          * Performance-wise, it does not make sense to
 360          * set the delay to a value that is lower
 361          * than the last one that worked (i.e. the state handles
 362          * were instantiated properly. Thus, instead of wasting
 363          * time trying to set the values controlling the sample
 364          * frequency, the function simply returns.
 365          */
 366         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 367               >> RTSDCTL_ENT_DLY_SHIFT;
 368         if (ent_delay <= val)
 369                 goto start_rng;
 370
 371         val = rd_reg32(&r4tst->rtsdctl);
 372         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 373               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 374         wr_reg32(&r4tst->rtsdctl, val);
 375         /* min. freq. count, equal to 1/4 of the entropy sample length */
 376         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 377         /* disable maximum frequency count */
 378         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 379         /* read the control register */
 380         val = rd_reg32(&r4tst->rtmctl);
 381 start_rng:
 382         /*
 383          * select raw sampling in both entropy shifter
 384          * and statistical checker; ; put RNG4 into run mode
 385          */
 386         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 387 }
 388
 389 /**
 390  * caam_get_era() - Return the ERA of the SEC on SoC, based
 391  * on "sec-era" propery in the DTS. This property is updated by u-boot.
 392  **/
 393 int caam_get_era(void)
 394 {
 395         struct device_node *caam_node;
 396         int ret;
 397         u32 prop;
 398
 399         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 400         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 401         of_node_put(caam_node);
 402
 403         return ret ? -ENOTSUPP : prop;
 404 }
 405 EXPORT_SYMBOL(caam_get_era);
 406
 407 #ifdef CONFIG_DEBUG_FS
 408 static int caam_debugfs_u64_get(void *data, u64 *val)
 409 {
 410         *val = caam64_to_cpu(*(u64 *)data);
 411         return 0;
 412 }
 413
 414 static int caam_debugfs_u32_get(void *data, u64 *val)
 415 {
 416         *val = caam32_to_cpu(*(u32 *)data);
 417         return 0;
 418 }
 419
 420 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
 421 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
 422 #endif
 423
 424 /* Probe routine for CAAM top (controller) level */
 425 static int caam_probe(struct platform_device *pdev)
 426 {
 427         int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 428         u64 caam_id;
 429         struct device *dev;
 430         struct device_node *nprop, *np;
 431         struct caam_ctrl __iomem *ctrl;
 432         struct caam_drv_private *ctrlpriv;
 433         struct clk *clk;
 434 #ifdef CONFIG_DEBUG_FS
 435         struct caam_perfmon *perfmon;
 436 #endif
 437         u32 scfgr, comp_params;
 438         u32 cha_vid_ls;
 439         int pg_size;
 440         int BLOCK_OFFSET = 0;
 441
 442         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 443         if (!ctrlpriv)
 444                 return -ENOMEM;
 445
 446         dev = &pdev->dev;
 447         dev_set_drvdata(dev, ctrlpriv);
 448         ctrlpriv->pdev = pdev;
 449         nprop = pdev->dev.of_node;
 450
 451         /* Enable clocking */
 452         clk = caam_drv_identify_clk(&pdev->dev, "ipg");
 453         if (IS_ERR(clk)) {
 454                 ret = PTR_ERR(clk);
 455                 dev_err(&pdev->dev,
 456                         "can't identify CAAM ipg clk: %d\n", ret);
 457                 return ret;
 458         }
 459         ctrlpriv->caam_ipg = clk;
 460
 461         clk = caam_drv_identify_clk(&pdev->dev, "mem");
 462         if (IS_ERR(clk)) {
 463                 ret = PTR_ERR(clk);
 464                 dev_err(&pdev->dev,
 465                         "can't identify CAAM mem clk: %d\n", ret);
 466                 return ret;
 467         }
 468         ctrlpriv->caam_mem = clk;
 469
 470         clk = caam_drv_identify_clk(&pdev->dev, "aclk");
 471         if (IS_ERR(clk)) {
 472                 ret = PTR_ERR(clk);
 473                 dev_err(&pdev->dev,
 474                         "can't identify CAAM aclk clk: %d\n", ret);
 475                 return ret;
 476         }
 477         ctrlpriv->caam_aclk = clk;
 478
 479         if (!of_machine_is_compatible("fsl,imx6ul")) {
 480                 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
 481                 if (IS_ERR(clk)) {
 482                         ret = PTR_ERR(clk);
 483                         dev_err(&pdev->dev,
 484                                 "can't identify CAAM emi_slow clk: %d\n", ret);
 485                         return ret;
 486                 }
 487                 ctrlpriv->caam_emi_slow = clk;
 488         }
 489
 490         ret = clk_prepare_enable(ctrlpriv->caam_ipg);
 491         if (ret < 0) {
 492                 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
 493                 return ret;
 494         }
 495
 496         ret = clk_prepare_enable(ctrlpriv->caam_mem);
 497         if (ret < 0) {
 498                 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
 499                         ret);
 500                 goto disable_caam_ipg;
 501         }
 502
 503         ret = clk_prepare_enable(ctrlpriv->caam_aclk);
 504         if (ret < 0) {
 505                 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
 506                 goto disable_caam_mem;
 507         }
 508
 509         if (ctrlpriv->caam_emi_slow) {
 510                 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
 511                 if (ret < 0) {
 512                         dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
 513                                 ret);
 514                         goto disable_caam_aclk;
 515                 }
 516         }
 517
 518         /* Get configuration properties from device tree */
 519         /* First, get register page */
 520         ctrl = of_iomap(nprop, 0);
 521         if (ctrl == NULL) {
 522                 dev_err(dev, "caam: of_iomap() failed\n");
 523                 ret = -ENOMEM;
 524                 goto disable_caam_emi_slow;
 525         }
 526
 527         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 528                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 529
 530         /* Finding the page size for using the CTPR_MS register */
 531         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 532         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 533
 534         /* Allocating the BLOCK_OFFSET based on the supported page size on
 535          * the platform
 536          */
 537         if (pg_size == 0)
 538                 BLOCK_OFFSET = PG_SIZE_4K;
 539         else
 540                 BLOCK_OFFSET = PG_SIZE_64K;
 541
 542         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 543         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 544                            ((__force uint8_t *)ctrl +
 545                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 546                            );
 547         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 548                          ((__force uint8_t *)ctrl +
 549                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 550                          );
 551
 552         /* Get the IRQ of the controller (for security violations only) */
 553         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 554
 555         /*
 556          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 557          * long pointers in master configuration register
 558          */
 559         clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
 560                       MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 561                       MCFGR_WDENABLE | MCFGR_LARGE_BURST |
 562                       (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
 563
 564         /*
 565          *  Read the Compile Time paramters and SCFGR to determine
 566          * if Virtualization is enabled for this platform
 567          */
 568         scfgr = rd_reg32(&ctrl->scfgr);
 569
 570         ctrlpriv->virt_en = 0;
 571         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 572                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 573                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 574                  */
 575                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 576                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 577                        (scfgr & SCFGR_VIRT_EN)))
 578                                 ctrlpriv->virt_en = 1;
 579         } else {
 580                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 581                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 582                                 ctrlpriv->virt_en = 1;
 583         }
 584
 585         if (ctrlpriv->virt_en == 1)
 586                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 587                               JRSTART_JR1_START | JRSTART_JR2_START |
 588                               JRSTART_JR3_START);
 589
 590         if (sizeof(dma_addr_t) == sizeof(u64))
 591                 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
 592                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
 593                 else
 594                         dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 595         else
 596                 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 597
 598         /*
 599          * Detect and enable JobRs
 600          * First, find out how many ring spec'ed, allocate references
 601          * for all, then go probe each one.
 602          */
 603         rspec = 0;
 604         for_each_available_child_of_node(nprop, np)
 605                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 606                     of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
 607                         rspec++;
 608
 609         ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec,
 610                                         sizeof(*ctrlpriv->jrpdev), GFP_KERNEL);
 611         if (ctrlpriv->jrpdev == NULL) {
 612                 ret = -ENOMEM;
 613                 goto iounmap_ctrl;
 614         }
 615
 616         ring = 0;
 617         ctrlpriv->total_jobrs = 0;
 618         for_each_available_child_of_node(nprop, np)
 619                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 620                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 621                         ctrlpriv->jrpdev[ring] =
 622                                 of_platform_device_create(np, NULL, dev);
 623                         if (!ctrlpriv->jrpdev[ring]) {
 624                                 pr_warn("JR%d Platform device creation error\n",
 625                                         ring);
 626                                 continue;
 627                         }
 628                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 629                                              ((__force uint8_t *)ctrl +
 630                                              (ring + JR_BLOCK_NUMBER) *
 631                                               BLOCK_OFFSET
 632                                              );
 633                         ctrlpriv->total_jobrs++;
 634                         ring++;
 635         }
 636
 637         /* Check to see if QI present. If so, enable */
 638         ctrlpriv->qi_present =
 639                         !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
 640                            CTPR_MS_QI_MASK);
 641         if (ctrlpriv->qi_present) {
 642                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 643                                ((__force uint8_t *)ctrl +
 644                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 645                                );
 646                 /* This is all that's required to physically enable QI */
 647                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 648         }
 649
 650         /* If no QI and no rings specified, quit and go home */
 651         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 652                 dev_err(dev, "no queues configured, terminating\n");
 653                 ret = -ENOMEM;
 654                 goto caam_remove;
 655         }
 656
 657         cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 658
 659         /*
 660          * If SEC has RNG version >= 4 and RNG state handle has not been
 661          * already instantiated, do RNG instantiation
 662          */
 663         if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 664                 ctrlpriv->rng4_sh_init =
 665                         rd_reg32(&ctrl->r4tst[0].rdsta);
 666                 /*
 667                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 668                  * generated, signal this to the function that is instantiating
 669                  * the state handles. An error would occur if RNG4 attempts
 670                  * to regenerate these keys before the next POR.
 671                  */
 672                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 673                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 674                 do {
 675                         int inst_handles =
 676                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 677                                                                 RDSTA_IFMASK;
 678                         /*
 679                          * If either SH were instantiated by somebody else
 680                          * (e.g. u-boot) then it is assumed that the entropy
 681                          * parameters are properly set and thus the function
 682                          * setting these (kick_trng(...)) is skipped.
 683                          * Also, if a handle was instantiated, do not change
 684                          * the TRNG parameters.
 685                          */
 686                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 687                                 dev_info(dev,
 688                                          "Entropy delay = %u\n",
 689                                          ent_delay);
 690                                 kick_trng(pdev, ent_delay);
 691                                 ent_delay += 400;
 692                         }
 693                         /*
 694                          * if instantiate_rng(...) fails, the loop will rerun
 695                          * and the kick_trng(...) function will modfiy the
 696                          * upper and lower limits of the entropy sampling
 697                          * interval, leading to a sucessful initialization of
 698                          * the RNG.
 699                          */
 700                         ret = instantiate_rng(dev, inst_handles,
 701                                               gen_sk);
 702                         if (ret == -EAGAIN)
 703                                 /*
 704                                  * if here, the loop will rerun,
 705                                  * so don't hog the CPU
 706                                  */
 707                                 cpu_relax();
 708                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 709                 if (ret) {
 710                         dev_err(dev, "failed to instantiate RNG");
 711                         goto caam_remove;
 712                 }
 713                 /*
 714                  * Set handles init'ed by this module as the complement of the
 715                  * already initialized ones
 716                  */
 717                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 718
 719                 /* Enable RDB bit so that RNG works faster */
 720                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 721         }
 722
 723         /* NOTE: RTIC detection ought to go here, around Si time */
 724
 725         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 726                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 727
 728         /* Report "alive" for developer to see */
 729         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 730                  caam_get_era());
 731         dev_info(dev, "job rings = %d, qi = %d\n",
 732                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 733
 734 #ifdef CONFIG_DEBUG_FS
 735         /*
 736          * FIXME: needs better naming distinction, as some amalgamation of
 737          * "caam" and nprop->full_name. The OF name isn't distinctive,
 738          * but does separate instances
 739          */
 740         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 741
 742         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 743         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 744
 745         /* Controller-level - performance monitor counters */
 746
 747         ctrlpriv->ctl_rq_dequeued =
 748                 debugfs_create_file("rq_dequeued",
 749                                     S_IRUSR | S_IRGRP | S_IROTH,
 750                                     ctrlpriv->ctl, &perfmon->req_dequeued,
 751                                     &caam_fops_u64_ro);
 752         ctrlpriv->ctl_ob_enc_req =
 753                 debugfs_create_file("ob_rq_encrypted",
 754                                     S_IRUSR | S_IRGRP | S_IROTH,
 755                                     ctrlpriv->ctl, &perfmon->ob_enc_req,
 756                                     &caam_fops_u64_ro);
 757         ctrlpriv->ctl_ib_dec_req =
 758                 debugfs_create_file("ib_rq_decrypted",
 759                                     S_IRUSR | S_IRGRP | S_IROTH,
 760                                     ctrlpriv->ctl, &perfmon->ib_dec_req,
 761                                     &caam_fops_u64_ro);
 762         ctrlpriv->ctl_ob_enc_bytes =
 763                 debugfs_create_file("ob_bytes_encrypted",
 764                                     S_IRUSR | S_IRGRP | S_IROTH,
 765                                     ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 766                                     &caam_fops_u64_ro);
 767         ctrlpriv->ctl_ob_prot_bytes =
 768                 debugfs_create_file("ob_bytes_protected",
 769                                     S_IRUSR | S_IRGRP | S_IROTH,
 770                                     ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 771                                     &caam_fops_u64_ro);
 772         ctrlpriv->ctl_ib_dec_bytes =
 773                 debugfs_create_file("ib_bytes_decrypted",
 774                                     S_IRUSR | S_IRGRP | S_IROTH,
 775                                     ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 776                                     &caam_fops_u64_ro);
 777         ctrlpriv->ctl_ib_valid_bytes =
 778                 debugfs_create_file("ib_bytes_validated",
 779                                     S_IRUSR | S_IRGRP | S_IROTH,
 780                                     ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 781                                     &caam_fops_u64_ro);
 782
 783         /* Controller level - global status values */
 784         ctrlpriv->ctl_faultaddr =
 785                 debugfs_create_file("fault_addr",
 786                                     S_IRUSR | S_IRGRP | S_IROTH,
 787                                     ctrlpriv->ctl, &perfmon->faultaddr,
 788                                     &caam_fops_u32_ro);
 789         ctrlpriv->ctl_faultdetail =
 790                 debugfs_create_file("fault_detail",
 791                                     S_IRUSR | S_IRGRP | S_IROTH,
 792                                     ctrlpriv->ctl, &perfmon->faultdetail,
 793                                     &caam_fops_u32_ro);
 794         ctrlpriv->ctl_faultstatus =
 795                 debugfs_create_file("fault_status",
 796                                     S_IRUSR | S_IRGRP | S_IROTH,
 797                                     ctrlpriv->ctl, &perfmon->status,
 798                                     &caam_fops_u32_ro);
 799
 800         /* Internal covering keys (useful in non-secure mode only) */
 801         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 802         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 803         ctrlpriv->ctl_kek = debugfs_create_blob("kek",
 804                                                 S_IRUSR |
 805                                                 S_IRGRP | S_IROTH,
 806                                                 ctrlpriv->ctl,
 807                                                 &ctrlpriv->ctl_kek_wrap);
 808
 809         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 810         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 811         ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
 812                                                  S_IRUSR |
 813                                                  S_IRGRP | S_IROTH,
 814                                                  ctrlpriv->ctl,
 815                                                  &ctrlpriv->ctl_tkek_wrap);
 816
 817         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 818         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 819         ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
 820                                                  S_IRUSR |
 821                                                  S_IRGRP | S_IROTH,
 822                                                  ctrlpriv->ctl,
 823                                                  &ctrlpriv->ctl_tdsk_wrap);
 824 #endif
 825         return 0;
 826
 827 caam_remove:
 828         caam_remove(pdev);
 829         return ret;
 830
 831 iounmap_ctrl:
 832         iounmap(ctrl);
 833 disable_caam_emi_slow:
 834         if (ctrlpriv->caam_emi_slow)
 835                 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
 836 disable_caam_aclk:
 837         clk_disable_unprepare(ctrlpriv->caam_aclk);
 838 disable_caam_mem:
 839         clk_disable_unprepare(ctrlpriv->caam_mem);
 840 disable_caam_ipg:
 841         clk_disable_unprepare(ctrlpriv->caam_ipg);
 842         return ret;
 843 }
 844
 845 static struct of_device_id caam_match[] = {
 846         {
 847                 .compatible = "fsl,sec-v4.0",
 848         },
 849         {
 850                 .compatible = "fsl,sec4.0",
 851         },
 852         {},
 853 };
 854 MODULE_DEVICE_TABLE(of, caam_match);
 855
 856 static struct platform_driver caam_driver = {
 857         .driver = {
 858                 .name = "caam",
 859                 .of_match_table = caam_match,
 860         },
 861         .probe       = caam_probe,
 862         .remove      = caam_remove,
 863 };
 864
 865 module_platform_driver(caam_driver);
 866
 867 MODULE_LICENSE("GPL");
 868 MODULE_DESCRIPTION("FSL CAAM request backend");
 869 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");