1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3 * Controller-level driver, kernel property detection, initialization
5 * Copyright 2008-2012 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019, 2023 NXP
9 #include <linux/device.h>
10 #include <linux/of_address.h>
11 #include <linux/of_irq.h>
12 #include <linux/sys_soc.h>
13 #include <linux/fsl/mc.h>
20 #include "desc_constr.h"
24 EXPORT_SYMBOL(caam_dpaa2);
31 * Descriptor to instantiate RNG State Handle 0 in normal mode and
32 * load the JDKEK, TDKEK and TDSK registers
34 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
36 u32 *jump_cmd, op_flags;
38 init_job_desc(desc, 0);
40 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
41 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
44 /* INIT RNG in non-test mode */
45 append_operation(desc, op_flags);
47 if (!handle && do_sk) {
49 * For SH0, Secure Keys must be generated as well
53 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
54 set_jump_tgt_here(desc, jump_cmd);
57 * load 1 to clear written reg:
58 * resets the done interrupt and returns the RNG to idle.
60 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
62 /* Initialize State Handle */
63 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
67 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
70 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
71 static void build_deinstantiation_desc(u32 *desc, int handle)
73 init_job_desc(desc, 0);
75 /* Uninstantiate State Handle 0 */
76 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
77 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
79 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
82 static const struct of_device_id imx8m_machine_match[] = {
83 { .compatible = "fsl,imx8mm", },
84 { .compatible = "fsl,imx8mn", },
85 { .compatible = "fsl,imx8mp", },
86 { .compatible = "fsl,imx8mq", },
87 { .compatible = "fsl,imx8ulp", },
92 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
93 * the software (no JR/QI used).
94 * @ctrldev - pointer to device
95 * @status - descriptor status, after being run
97 * Return: - 0 if no error occurred
98 * - -ENODEV if the DECO couldn't be acquired
99 * - -EAGAIN if an error occurred while executing the descriptor
101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
104 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
105 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
106 struct caam_deco __iomem *deco = ctrlpriv->deco;
107 unsigned int timeout = 100000;
108 u32 deco_dbg_reg, deco_state, flags;
112 if (ctrlpriv->virt_en == 1 ||
114 * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
115 * and the following steps should be performed regardless
117 of_match_node(imx8m_machine_match, of_root)) {
118 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
120 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
127 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
129 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
134 dev_err(ctrldev, "failed to acquire DECO 0\n");
135 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
139 for (i = 0; i < desc_len(desc); i++)
140 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
142 flags = DECO_JQCR_WHL;
144 * If the descriptor length is longer than 4 words, then the
145 * FOUR bit in JRCTRL register must be set.
147 if (desc_len(desc) >= 4)
148 flags |= DECO_JQCR_FOUR;
150 /* Instruct the DECO to execute it */
151 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
155 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
157 if (ctrlpriv->era < 10)
158 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
159 DESC_DBG_DECO_STAT_SHIFT;
161 deco_state = (rd_reg32(&deco->dbg_exec) &
162 DESC_DER_DECO_STAT_MASK) >>
163 DESC_DER_DECO_STAT_SHIFT;
166 * If an error occurred in the descriptor, then
167 * the DECO status field will be set to 0x0D
169 if (deco_state == DECO_STAT_HOST_ERR)
173 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
175 *status = rd_reg32(&deco->op_status_hi) &
176 DECO_OP_STATUS_HI_ERR_MASK;
178 if (ctrlpriv->virt_en == 1)
179 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
181 /* Mark the DECO as free */
182 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
191 * deinstantiate_rng - builds and executes a descriptor on DECO0,
192 * which deinitializes the RNG block.
193 * @ctrldev - pointer to device
194 * @state_handle_mask - bitmask containing the instantiation status
195 * for the RNG4 state handles which exist in
196 * the RNG4 block: 1 if it's been instantiated
198 * Return: - 0 if no error occurred
199 * - -ENOMEM if there isn't enough memory to allocate the descriptor
200 * - -ENODEV if DECO0 couldn't be acquired
201 * - -EAGAIN if an error occurred when executing the descriptor
203 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
208 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
212 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
214 * If the corresponding bit is set, then it means the state
215 * handle was initialized by us, and thus it needs to be
216 * deinitialized as well
218 if ((1 << sh_idx) & state_handle_mask) {
220 * Create the descriptor for deinstantating this state
223 build_deinstantiation_desc(desc, sh_idx);
225 /* Try to run it through DECO0 */
226 ret = run_descriptor_deco0(ctrldev, desc, &status);
229 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
231 "Failed to deinstantiate RNG4 SH%d\n",
235 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
244 static void devm_deinstantiate_rng(void *data)
246 struct device *ctrldev = data;
247 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
250 * De-initialize RNG state handles initialized by this driver.
251 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
253 if (ctrlpriv->rng4_sh_init)
254 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
258 * instantiate_rng - builds and executes a descriptor on DECO0,
259 * which initializes the RNG block.
260 * @ctrldev - pointer to device
261 * @state_handle_mask - bitmask containing the instantiation status
262 * for the RNG4 state handles which exist in
263 * the RNG4 block: 1 if it's been instantiated
264 * by an external entry, 0 otherwise.
265 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
266 * Caution: this can be done only once; if the keys need to be
267 * regenerated, a POR is required
269 * Return: - 0 if no error occurred
270 * - -ENOMEM if there isn't enough memory to allocate the descriptor
271 * - -ENODEV if DECO0 couldn't be acquired
272 * - -EAGAIN if an error occurred when executing the descriptor
273 * f.i. there was a RNG hardware error due to not "good enough"
274 * entropy being acquired.
276 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
279 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
280 struct caam_ctrl __iomem *ctrl;
281 u32 *desc, status = 0, rdsta_val;
284 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
285 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
289 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
290 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
291 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
292 const u32 rdsta_mask = rdsta_if | rdsta_pr;
294 /* Clear the contents before using the descriptor */
295 memset(desc, 0x00, CAAM_CMD_SZ * 7);
298 * If the corresponding bit is set, this state handle
299 * was initialized by somebody else, so it's left alone.
301 if (rdsta_if & state_handle_mask) {
302 if (rdsta_pr & state_handle_mask)
306 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
309 ret = deinstantiate_rng(ctrldev, rdsta_if);
314 /* Create the descriptor for instantiating RNG State Handle */
315 build_instantiation_desc(desc, sh_idx, gen_sk);
317 /* Try to run it through DECO0 */
318 ret = run_descriptor_deco0(ctrldev, desc, &status);
321 * If ret is not 0, or descriptor status is not 0, then
322 * something went wrong. No need to try the next state
323 * handle (if available), bail out here.
324 * Also, if for some reason, the State Handle didn't get
325 * instantiated although the descriptor has finished
326 * without any error (HW optimizations for later
327 * CAAM eras), then try again.
332 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
333 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
334 (rdsta_val & rdsta_mask) != rdsta_mask) {
339 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
347 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
351 * kick_trng - sets the various parameters for enabling the initialization
352 * of the RNG4 block in CAAM
353 * @dev - pointer to the controller device
354 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
356 static void kick_trng(struct device *dev, int ent_delay)
358 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
359 struct caam_ctrl __iomem *ctrl;
360 struct rng4tst __iomem *r4tst;
363 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
364 r4tst = &ctrl->r4tst[0];
367 * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
368 * properly invalidate the entropy in the entropy register and
369 * force re-generation.
371 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
374 * Performance-wise, it does not make sense to
375 * set the delay to a value that is lower
376 * than the last one that worked (i.e. the state handles
377 * were instantiated properly).
379 rtsdctl = rd_reg32(&r4tst->rtsdctl);
380 val = (rtsdctl & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT;
381 if (ent_delay > val) {
383 /* min. freq. count, equal to 1/4 of the entropy sample length */
384 wr_reg32(&r4tst->rtfrqmin, val >> 2);
385 /* disable maximum frequency count */
386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
389 wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |
390 RTSDCTL_SAMP_SIZE_VAL);
393 * To avoid reprogramming the self-test parameters over and over again,
394 * use RTSDCTL[SAMP_SIZE] as an indicator.
396 if ((rtsdctl & RTSDCTL_SAMP_SIZE_MASK) != RTSDCTL_SAMP_SIZE_VAL) {
397 wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);
398 wr_reg32(&r4tst->rtpkrrng, 570);
399 wr_reg32(&r4tst->rtpkrmax, 1600);
400 wr_reg32(&r4tst->rtscml, (122 << 16) | 317);
401 wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);
402 wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);
403 wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);
404 wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);
405 wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);
406 wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);
410 * select raw sampling in both entropy shifter
411 * and statistical checker; ; put RNG4 into run mode
413 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
414 RTMCTL_SAMP_MODE_RAW_ES_SC);
417 static int caam_get_era_from_hw(struct caam_perfmon __iomem *perfmon)
419 static const struct {
443 ccbvid = rd_reg32(&perfmon->ccb_id);
444 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
445 if (era) /* This is '0' prior to CAAM ERA-6 */
448 id_ms = rd_reg32(&perfmon->caam_id_ms);
449 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
450 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
452 for (i = 0; i < ARRAY_SIZE(id); i++)
453 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
460 * caam_get_era() - Return the ERA of the SEC on SoC, based
461 * on "sec-era" optional property in the DTS. This property is updated
463 * In case this property is not passed an attempt to retrieve the CAAM
464 * era via register reads will be made.
466 * @perfmon: Performance Monitor Registers
468 static int caam_get_era(struct caam_perfmon __iomem *perfmon)
470 struct device_node *caam_node;
474 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
475 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
476 of_node_put(caam_node);
481 return caam_get_era_from_hw(perfmon);
485 * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
486 * have an issue wherein AXI bus transactions may not occur in the correct
487 * order. This isn't a problem running single descriptors, but can be if
488 * running multiple concurrent descriptors. Reworking the driver to throttle
489 * to single requests is impractical, thus the workaround is to limit the AXI
490 * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
493 static void handle_imx6_err005766(u32 __iomem *mcr)
495 if (of_machine_is_compatible("fsl,imx6q") ||
496 of_machine_is_compatible("fsl,imx6dl") ||
497 of_machine_is_compatible("fsl,imx6qp"))
498 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
499 1 << MCFGR_AXIPIPE_SHIFT);
502 static const struct of_device_id caam_match[] = {
504 .compatible = "fsl,sec-v4.0",
507 .compatible = "fsl,sec4.0",
511 MODULE_DEVICE_TABLE(of, caam_match);
513 struct caam_imx_data {
514 const struct clk_bulk_data *clks;
518 static const struct clk_bulk_data caam_imx6_clks[] = {
522 { .id = "emi_slow" },
525 static const struct caam_imx_data caam_imx6_data = {
526 .clks = caam_imx6_clks,
527 .num_clks = ARRAY_SIZE(caam_imx6_clks),
530 static const struct clk_bulk_data caam_imx7_clks[] = {
535 static const struct caam_imx_data caam_imx7_data = {
536 .clks = caam_imx7_clks,
537 .num_clks = ARRAY_SIZE(caam_imx7_clks),
540 static const struct clk_bulk_data caam_imx6ul_clks[] = {
546 static const struct caam_imx_data caam_imx6ul_data = {
547 .clks = caam_imx6ul_clks,
548 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
551 static const struct clk_bulk_data caam_vf610_clks[] = {
555 static const struct caam_imx_data caam_vf610_data = {
556 .clks = caam_vf610_clks,
557 .num_clks = ARRAY_SIZE(caam_vf610_clks),
560 static const struct soc_device_attribute caam_imx_soc_table[] = {
561 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
562 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
563 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
564 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
565 { .soc_id = "VF*", .data = &caam_vf610_data },
566 { .family = "Freescale i.MX" },
570 static void disable_clocks(void *data)
572 struct caam_drv_private *ctrlpriv = data;
574 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
577 static int init_clocks(struct device *dev, const struct caam_imx_data *data)
579 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
582 ctrlpriv->num_clks = data->num_clks;
583 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
584 data->num_clks * sizeof(data->clks[0]),
589 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
592 "Failed to request all necessary clocks\n");
596 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
599 "Failed to prepare/enable all necessary clocks\n");
603 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
606 static void caam_remove_debugfs(void *root)
608 debugfs_remove_recursive(root);
611 #ifdef CONFIG_FSL_MC_BUS
612 static bool check_version(struct fsl_mc_version *mc_version, u32 major,
613 u32 minor, u32 revision)
615 if (mc_version->major > major)
618 if (mc_version->major == major) {
619 if (mc_version->minor > minor)
622 if (mc_version->minor == minor &&
623 mc_version->revision > revision)
631 static bool needs_entropy_delay_adjustment(void)
633 if (of_machine_is_compatible("fsl,imx6sx"))
638 static int caam_ctrl_rng_init(struct device *dev)
640 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
641 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
642 int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
645 if (ctrlpriv->era < 10) {
646 struct caam_perfmon __iomem *perfmon;
648 perfmon = ctrlpriv->total_jobrs ?
649 (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
650 (struct caam_perfmon __iomem *)&ctrl->perfmon;
652 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
653 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
655 struct version_regs __iomem *vreg;
657 vreg = ctrlpriv->total_jobrs ?
658 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
659 (struct version_regs __iomem *)&ctrl->vreg;
661 rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>
666 * If SEC has RNG version >= 4 and RNG state handle has not been
667 * already instantiated, do RNG instantiation
668 * In case of SoCs with Management Complex, RNG is managed by MC f/w.
670 if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {
671 ctrlpriv->rng4_sh_init =
672 rd_reg32(&ctrl->r4tst[0].rdsta);
674 * If the secure keys (TDKEK, JDKEK, TDSK), were already
675 * generated, signal this to the function that is instantiating
676 * the state handles. An error would occur if RNG4 attempts
677 * to regenerate these keys before the next POR.
679 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
680 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
683 rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
685 * If either SH were instantiated by somebody else
686 * (e.g. u-boot) then it is assumed that the entropy
687 * parameters are properly set and thus the function
688 * setting these (kick_trng(...)) is skipped.
689 * Also, if a handle was instantiated, do not change
690 * the TRNG parameters.
692 if (needs_entropy_delay_adjustment())
694 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
696 "Entropy delay = %u\n",
698 kick_trng(dev, ent_delay);
702 * if instantiate_rng(...) fails, the loop will rerun
703 * and the kick_trng(...) function will modify the
704 * upper and lower limits of the entropy sampling
705 * interval, leading to a successful initialization of
708 ret = instantiate_rng(dev, inst_handles,
711 * Entropy delay is determined via TRNG characterization.
712 * TRNG characterization is run across different voltages
714 * If worst case value for ent_dly is identified,
715 * the loop can be skipped for that platform.
717 if (needs_entropy_delay_adjustment())
721 * if here, the loop will rerun,
722 * so don't hog the CPU
725 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
727 dev_err(dev, "failed to instantiate RNG");
731 * Set handles initialized by this module as the complement of
732 * the already initialized ones
734 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
736 /* Enable RDB bit so that RNG works faster */
737 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
743 /* Probe routine for CAAM top (controller) level */
744 static int caam_probe(struct platform_device *pdev)
748 const struct soc_device_attribute *imx_soc_match;
750 struct device_node *nprop, *np;
751 struct caam_ctrl __iomem *ctrl;
752 struct caam_drv_private *ctrlpriv;
753 struct caam_perfmon __iomem *perfmon;
754 struct dentry *dfs_root;
755 u32 scfgr, comp_params;
757 int BLOCK_OFFSET = 0;
758 bool reg_access = true;
760 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
765 dev_set_drvdata(dev, ctrlpriv);
766 nprop = pdev->dev.of_node;
768 imx_soc_match = soc_device_match(caam_imx_soc_table);
769 if (!imx_soc_match && of_match_node(imx8m_machine_match, of_root))
770 return -EPROBE_DEFER;
772 caam_imx = (bool)imx_soc_match;
776 * Until Layerscape and i.MX OP-TEE get in sync,
777 * only i.MX OP-TEE use cases disallow access to
778 * caam page 0 (controller) registers.
780 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
781 ctrlpriv->optee_en = !!np;
784 reg_access = !ctrlpriv->optee_en;
786 if (!imx_soc_match->data) {
787 dev_err(dev, "No clock data provided for i.MX SoC");
791 ret = init_clocks(dev, imx_soc_match->data);
797 /* Get configuration properties from device tree */
798 /* First, get register page */
799 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
800 ret = PTR_ERR_OR_ZERO(ctrl);
802 dev_err(dev, "caam: of_iomap() failed\n");
807 for_each_available_child_of_node(nprop, np)
808 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
809 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
812 if (of_property_read_u32_index(np, "reg", 0, ®)) {
813 dev_err(dev, "%s read reg property error\n",
818 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
819 ((__force uint8_t *)ctrl + reg);
821 ctrlpriv->total_jobrs++;
826 * Wherever possible, instead of accessing registers from the global page,
827 * use the alias registers in the first (cf. DT nodes order)
830 perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :
831 (struct caam_perfmon __iomem *)&ctrl->perfmon;
833 caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
834 (CSTA_PLEND | CSTA_ALT_PLEND));
835 comp_params = rd_reg32(&perfmon->comp_parms_ms);
836 if (reg_access && comp_params & CTPR_MS_PS &&
837 rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
838 caam_ptr_sz = sizeof(u64);
840 caam_ptr_sz = sizeof(u32);
841 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
842 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
844 #ifdef CONFIG_CAAM_QI
845 /* If (DPAA 1.x) QI present, check whether dependencies are available */
846 if (ctrlpriv->qi_present && !caam_dpaa2) {
847 ret = qman_is_probed();
849 return -EPROBE_DEFER;
850 } else if (ret < 0) {
851 dev_err(dev, "failing probe due to qman probe error\n");
855 ret = qman_portals_probed();
857 return -EPROBE_DEFER;
858 } else if (ret < 0) {
859 dev_err(dev, "failing probe due to qman portals probe error\n");
865 /* Allocating the BLOCK_OFFSET based on the supported page size on
868 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
870 BLOCK_OFFSET = PG_SIZE_4K;
872 BLOCK_OFFSET = PG_SIZE_64K;
874 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
875 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
876 ((__force uint8_t *)ctrl +
877 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
879 ctrlpriv->deco = (struct caam_deco __iomem __force *)
880 ((__force uint8_t *)ctrl +
881 BLOCK_OFFSET * DECO_BLOCK_NUMBER
884 /* Get the IRQ of the controller (for security violations only) */
885 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
886 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
887 ctrlpriv->mc_en = !!np;
890 #ifdef CONFIG_FSL_MC_BUS
891 if (ctrlpriv->mc_en) {
892 struct fsl_mc_version *mc_version;
894 mc_version = fsl_mc_get_version();
896 ctrlpriv->pr_support = check_version(mc_version, 10, 20,
899 return -EPROBE_DEFER;
907 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
908 * long pointers in master configuration register.
909 * In case of SoCs with Management Complex, MC f/w performs
912 if (!ctrlpriv->mc_en)
913 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
914 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
915 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
917 handle_imx6_err005766(&ctrl->mcr);
920 * Read the Compile Time parameters and SCFGR to determine
921 * if virtualization is enabled for this platform
923 scfgr = rd_reg32(&ctrl->scfgr);
925 ctrlpriv->virt_en = 0;
926 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
927 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
928 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
930 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
931 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
932 (scfgr & SCFGR_VIRT_EN)))
933 ctrlpriv->virt_en = 1;
935 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
936 if (comp_params & CTPR_MS_VIRT_EN_POR)
937 ctrlpriv->virt_en = 1;
940 if (ctrlpriv->virt_en == 1)
941 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
942 JRSTART_JR1_START | JRSTART_JR2_START |
946 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
948 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
952 ctrlpriv->era = caam_get_era(perfmon);
953 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
955 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
956 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
957 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
963 caam_debugfs_init(ctrlpriv, perfmon, dfs_root);
965 /* Check to see if (DPAA 1.x) QI present. If so, enable */
966 if (ctrlpriv->qi_present && !caam_dpaa2) {
967 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
968 ((__force uint8_t *)ctrl +
969 BLOCK_OFFSET * QI_BLOCK_NUMBER
971 /* This is all that's required to physically enable QI */
972 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
974 /* If QMAN driver is present, init CAAM-QI backend */
975 #ifdef CONFIG_CAAM_QI
976 ret = caam_qi_init(pdev);
978 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
982 /* If no QI and no rings specified, quit and go home */
983 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
984 dev_err(dev, "no queues configured, terminating\n");
988 comp_params = rd_reg32(&perfmon->comp_parms_ls);
989 ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);
992 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,
993 * but fail when actually using it due to missing AES support, so
996 if (ctrlpriv->era < 10) {
997 ctrlpriv->blob_present = ctrlpriv->blob_present &&
998 (rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);
1000 struct version_regs __iomem *vreg;
1002 vreg = ctrlpriv->total_jobrs ?
1003 (struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :
1004 (struct version_regs __iomem *)&ctrl->vreg;
1006 ctrlpriv->blob_present = ctrlpriv->blob_present &&
1007 (rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);
1011 ret = caam_ctrl_rng_init(dev);
1016 caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
1017 (u64)rd_reg32(&perfmon->caam_id_ls);
1019 /* Report "alive" for developer to see */
1020 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
1022 dev_info(dev, "job rings = %d, qi = %d\n",
1023 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
1025 ret = devm_of_platform_populate(dev);
1027 dev_err(dev, "JR platform devices creation error\n");
1032 static struct platform_driver caam_driver = {
1035 .of_match_table = caam_match,
1037 .probe = caam_probe,
1040 module_platform_driver(caam_driver);
1042 MODULE_LICENSE("GPL");
1043 MODULE_DESCRIPTION("FSL CAAM request backend");
1044 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");