1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
5 * Library for common functions for Intel SpeedStep v.1 and v.2 support
7 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/cpufreq.h>
20 #include "speedstep-lib.h"
22 #define PFX "speedstep-lib: "
24 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
25 static int relaxed_check;
27 #define relaxed_check 0
30 /*********************************************************************
31 * GET PROCESSOR CORE SPEED IN KHZ *
32 *********************************************************************/
34 static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
36 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
38 unsigned int ratio; /* Frequency Multiplier (x10) */
39 u8 bitmap; /* power on configuration bits
40 [27, 25:22] (in MSR 0x2a) */
41 } msr_decode_mult[] = {
56 { 0, 0xff } /* error or unknown value */
59 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
61 unsigned int value; /* Front Side Bus speed in MHz */
62 u8 bitmap; /* power on configuration bits [18: 19]
64 } msr_decode_fsb[] = {
74 /* read MSR 0x2a - we only need the low 32 bits */
75 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
76 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
82 while (msr_tmp != msr_decode_fsb[i].bitmap) {
83 if (msr_decode_fsb[i].bitmap == 0xff)
88 /* decode the multiplier */
89 if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
90 pr_debug("workaround for early PIIIs\n");
95 while (msr_lo != msr_decode_mult[j].bitmap) {
96 if (msr_decode_mult[j].bitmap == 0xff)
101 pr_debug("speed is %u\n",
102 (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
104 return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
108 static unsigned int pentiumM_get_frequency(void)
112 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
113 pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
115 /* see table B-2 of 24547212.pdf */
116 if (msr_lo & 0x00040000) {
117 printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
122 msr_tmp = (msr_lo >> 22) & 0x1f;
123 pr_debug("bits 22-26 are 0x%x, speed is %u\n",
124 msr_tmp, (msr_tmp * 100 * 1000));
126 return msr_tmp * 100 * 1000;
129 static unsigned int pentium_core_get_frequency(void)
135 rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
136 /* see table B-2 of 25366920.pdf */
137 switch (msr_lo & 0x07) {
157 pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
160 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
161 pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
164 msr_tmp = (msr_lo >> 22) & 0x1f;
165 pr_debug("bits 22-26 are 0x%x, speed is %u\n",
166 msr_tmp, (msr_tmp * fsb));
168 ret = (msr_tmp * fsb);
173 static unsigned int pentium4_get_frequency(void)
175 struct cpuinfo_x86 *c = &boot_cpu_data;
176 u32 msr_lo, msr_hi, mult;
177 unsigned int fsb = 0;
181 /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
182 * to System Bus Frequency Ratio Field in the Processor Frequency
183 * Configuration Register of the MSR. Therefore the current
184 * frequency cannot be calculated and has to be measured.
186 if (c->x86_model < 2)
189 rdmsr(0x2c, msr_lo, msr_hi);
191 pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
193 /* decode the FSB: see IA-32 Intel (C) Architecture Software
194 * Developer's Manual, Volume 3: System Prgramming Guide,
195 * revision #12 in Table B-1: MSRs in the Pentium 4 and
196 * Intel Xeon Processors, on page B-4 and B-5.
198 fsb_code = (msr_lo >> 16) & 0x7;
212 printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
213 "Please send an e-mail to <linux@brodo.de>\n");
218 pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
219 fsb, mult, (fsb * mult));
226 /* Warning: may get called from smp_call_function_single. */
227 unsigned int speedstep_get_frequency(enum speedstep_processor processor)
230 case SPEEDSTEP_CPU_PCORE:
231 return pentium_core_get_frequency();
232 case SPEEDSTEP_CPU_PM:
233 return pentiumM_get_frequency();
234 case SPEEDSTEP_CPU_P4D:
235 case SPEEDSTEP_CPU_P4M:
236 return pentium4_get_frequency();
237 case SPEEDSTEP_CPU_PIII_T:
238 case SPEEDSTEP_CPU_PIII_C:
239 case SPEEDSTEP_CPU_PIII_C_EARLY:
240 return pentium3_get_frequency(processor);
246 EXPORT_SYMBOL_GPL(speedstep_get_frequency);
249 /*********************************************************************
250 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
251 *********************************************************************/
253 /* Keep in sync with the x86_cpu_id tables in the different modules */
254 enum speedstep_processor speedstep_detect_processor(void)
256 struct cpuinfo_x86 *c = &cpu_data(0);
257 u32 ebx, msr_lo, msr_hi;
259 pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
261 if ((c->x86_vendor != X86_VENDOR_INTEL) ||
262 ((c->x86 != 6) && (c->x86 != 0xF)))
266 /* Intel Mobile Pentium 4-M
267 * or Intel Mobile Pentium 4 with 533 MHz FSB */
268 if (c->x86_model != 2)
271 ebx = cpuid_ebx(0x00000001);
274 pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
276 switch (c->x86_stepping) {
279 * B-stepping [M-P4-M]
280 * sample has ebx = 0x0f, production has 0x0e.
282 if ((ebx == 0x0e) || (ebx == 0x0f))
283 return SPEEDSTEP_CPU_P4M;
287 * C-stepping [M-P4-M]
288 * needs to have ebx=0x0e, else it's a celeron:
289 * cf. 25130917.pdf / page 7, footnote 5 even
290 * though 25072120.pdf / page 7 doesn't say
291 * samples are only of B-stepping...
294 return SPEEDSTEP_CPU_P4M;
298 * D-stepping [M-P4-M or M-P4/533]
300 * this is totally strange: CPUID 0x0F29 is
301 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
302 * The latter need to be sorted out as they don't
304 * Celerons with CPUID 0x0F29 may have either
305 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
307 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
308 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
309 * also, M-P4M HTs have ebx=0x8, too
310 * For now, they are distinguished by the model_id
314 (strstr(c->x86_model_id,
315 "Mobile Intel(R) Pentium(R) 4") != NULL))
316 return SPEEDSTEP_CPU_P4M;
324 switch (c->x86_model) {
325 case 0x0B: /* Intel PIII [Tualatin] */
326 /* cpuid_ebx(1) is 0x04 for desktop PIII,
327 * 0x06 for mobile PIII-M */
328 ebx = cpuid_ebx(0x00000001);
329 pr_debug("ebx is %x\n", ebx);
336 /* So far all PIII-M processors support SpeedStep. See
337 * Intel's 24540640.pdf of June 2003
339 return SPEEDSTEP_CPU_PIII_T;
341 case 0x08: /* Intel PIII [Coppermine] */
343 /* all mobile PIII Coppermines have FSB 100 MHz
344 * ==> sort out a few desktop PIIIs. */
345 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
346 pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
349 if (msr_lo != 0x0080000)
353 * If the processor is a mobile version,
354 * platform ID has bit 50 set
355 * it has SpeedStep technology if either
356 * bit 56 or 57 is set
358 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
359 pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
361 if ((msr_hi & (1<<18)) &&
362 (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
363 if (c->x86_stepping == 0x01) {
364 pr_debug("early PIII version\n");
365 return SPEEDSTEP_CPU_PIII_C_EARLY;
367 return SPEEDSTEP_CPU_PIII_C;
374 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
377 /*********************************************************************
378 * DETECT SPEEDSTEP SPEEDS *
379 *********************************************************************/
381 unsigned int speedstep_get_freqs(enum speedstep_processor processor,
382 unsigned int *low_speed,
383 unsigned int *high_speed,
384 unsigned int *transition_latency,
385 void (*set_state) (unsigned int state))
387 unsigned int prev_speed;
388 unsigned int ret = 0;
392 if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
395 pr_debug("trying to determine both speeds\n");
397 /* get current speed */
398 prev_speed = speedstep_get_frequency(processor);
402 pr_debug("previous speed is %u\n", prev_speed);
405 local_irq_save(flags);
407 /* switch to low state */
408 set_state(SPEEDSTEP_LOW);
409 *low_speed = speedstep_get_frequency(processor);
415 pr_debug("low speed is %u\n", *low_speed);
417 /* start latency measurement */
418 if (transition_latency)
421 /* switch to high state */
422 set_state(SPEEDSTEP_HIGH);
424 /* end latency measurement */
425 if (transition_latency)
428 *high_speed = speedstep_get_frequency(processor);
434 pr_debug("high speed is %u\n", *high_speed);
436 if (*low_speed == *high_speed) {
441 /* switch to previous state, if necessary */
442 if (*high_speed != prev_speed)
443 set_state(SPEEDSTEP_LOW);
445 if (transition_latency) {
446 *transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
447 pr_debug("transition latency is %u uSec\n", *transition_latency);
449 /* convert uSec to nSec and add 20% for safety reasons */
450 *transition_latency *= 1200;
452 /* check if the latency measurement is too high or too low
453 * and set it to a safe value (500uSec) in that case
455 if (*transition_latency > 10000000 ||
456 *transition_latency < 50000) {
457 pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
458 *transition_latency, 500000);
459 *transition_latency = 500000;
464 local_irq_restore(flags);
469 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
471 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
472 module_param(relaxed_check, int, 0444);
473 MODULE_PARM_DESC(relaxed_check,
474 "Don't do all checks for speedstep capability.");
477 MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
478 MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
479 MODULE_LICENSE("GPL");