drivers/cpufreq/qcom-cpufreq-nvmem.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 /*
   7  * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
   8  * the CPU frequency subset and voltage value of each OPP varies
   9  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
  10  * defines the voltage and frequency value based on the msm-id in SMEM
  11  * and speedbin blown in the efuse combination.
  12  * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  13  * to provide the OPP framework with required information.
  14  * This is used to determine the voltage and frequency value for each OPP of
  15  * operating-points-v2 table when it is parsed by the OPP framework.
  16  */
  17
  18 #include <linux/cpu.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/nvmem-consumer.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_domain.h>
  28 #include <linux/pm_opp.h>
  29 #include <linux/slab.h>
  30 #include <linux/soc/qcom/smem.h>
  31
  32 #define MSM_ID_SMEM     137
  33
  34 enum _msm_id {
  35         MSM8996V3 = 0xF6ul,
  36         APQ8096V3 = 0x123ul,
  37         MSM8996SG = 0x131ul,
  38         APQ8096SG = 0x138ul,
  39 };
  40
  41 enum _msm8996_version {
  42         MSM8996_V3,
  43         MSM8996_SG,
  44         NUM_OF_MSM8996_VERSIONS,
  45 };
  46
  47 struct qcom_cpufreq_drv;
  48
  49 struct qcom_cpufreq_match_data {
  50         int (*get_version)(struct device *cpu_dev,
  51                            struct nvmem_cell *speedbin_nvmem,
  52                            char **pvs_name,
  53                            struct qcom_cpufreq_drv *drv);
  54         const char **genpd_names;
  55 };
  56
  57 struct qcom_cpufreq_drv {
  58         int *opp_tokens;
  59         u32 versions;
  60         const struct qcom_cpufreq_match_data *data;
  61 };
  62
  63 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
  64
  65 static void get_krait_bin_format_a(struct device *cpu_dev,
  66                                           int *speed, int *pvs, int *pvs_ver,
  67                                           struct nvmem_cell *pvs_nvmem, u8 *buf)
  68 {
  69         u32 pte_efuse;
  70
  71         pte_efuse = *((u32 *)buf);
  72
  73         *speed = pte_efuse & 0xf;
  74         if (*speed == 0xf)
  75                 *speed = (pte_efuse >> 4) & 0xf;
  76
  77         if (*speed == 0xf) {
  78                 *speed = 0;
  79                 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
  80         } else {
  81                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
  82         }
  83
  84         *pvs = (pte_efuse >> 10) & 0x7;
  85         if (*pvs == 0x7)
  86                 *pvs = (pte_efuse >> 13) & 0x7;
  87
  88         if (*pvs == 0x7) {
  89                 *pvs = 0;
  90                 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
  91         } else {
  92                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
  93         }
  94 }
  95
  96 static void get_krait_bin_format_b(struct device *cpu_dev,
  97                                           int *speed, int *pvs, int *pvs_ver,
  98                                           struct nvmem_cell *pvs_nvmem, u8 *buf)
  99 {
 100         u32 pte_efuse, redundant_sel;
 101
 102         pte_efuse = *((u32 *)buf);
 103         redundant_sel = (pte_efuse >> 24) & 0x7;
 104
 105         *pvs_ver = (pte_efuse >> 4) & 0x3;
 106
 107         switch (redundant_sel) {
 108         case 1:
 109                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 110                 *speed = (pte_efuse >> 27) & 0xf;
 111                 break;
 112         case 2:
 113                 *pvs = (pte_efuse >> 27) & 0xf;
 114                 *speed = pte_efuse & 0x7;
 115                 break;
 116         default:
 117                 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
 118                 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 119                 *speed = pte_efuse & 0x7;
 120         }
 121
 122         /* Check SPEED_BIN_BLOW_STATUS */
 123         if (pte_efuse & BIT(3)) {
 124                 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
 125         } else {
 126                 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
 127                 *speed = 0;
 128         }
 129
 130         /* Check PVS_BLOW_STATUS */
 131         pte_efuse = *(((u32 *)buf) + 1);
 132         pte_efuse &= BIT(21);
 133         if (pte_efuse) {
 134                 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
 135         } else {
 136                 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
 137                 *pvs = 0;
 138         }
 139
 140         dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
 141 }
 142
 143 static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
 144 {
 145         size_t len;
 146         u32 *msm_id;
 147         enum _msm8996_version version;
 148
 149         msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
 150         if (IS_ERR(msm_id))
 151                 return NUM_OF_MSM8996_VERSIONS;
 152
 153         /* The first 4 bytes are format, next to them is the actual msm-id */
 154         msm_id++;
 155
 156         switch ((enum _msm_id)*msm_id) {
 157         case MSM8996V3:
 158         case APQ8096V3:
 159                 version = MSM8996_V3;
 160                 break;
 161         case MSM8996SG:
 162         case APQ8096SG:
 163                 version = MSM8996_SG;
 164                 break;
 165         default:
 166                 version = NUM_OF_MSM8996_VERSIONS;
 167         }
 168
 169         return version;
 170 }
 171
 172 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
 173                                           struct nvmem_cell *speedbin_nvmem,
 174                                           char **pvs_name,
 175                                           struct qcom_cpufreq_drv *drv)
 176 {
 177         size_t len;
 178         u8 *speedbin;
 179         enum _msm8996_version msm8996_version;
 180         *pvs_name = NULL;
 181
 182         msm8996_version = qcom_cpufreq_get_msm_id();
 183         if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
 184                 dev_err(cpu_dev, "Not Snapdragon 820/821!");
 185                 return -ENODEV;
 186         }
 187
 188         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 189         if (IS_ERR(speedbin))
 190                 return PTR_ERR(speedbin);
 191
 192         switch (msm8996_version) {
 193         case MSM8996_V3:
 194                 drv->versions = 1 << (unsigned int)(*speedbin);
 195                 break;
 196         case MSM8996_SG:
 197                 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
 198                 break;
 199         default:
 200                 BUG();
 201                 break;
 202         }
 203
 204         kfree(speedbin);
 205         return 0;
 206 }
 207
 208 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
 209                                            struct nvmem_cell *speedbin_nvmem,
 210                                            char **pvs_name,
 211                                            struct qcom_cpufreq_drv *drv)
 212 {
 213         int speed = 0, pvs = 0, pvs_ver = 0;
 214         u8 *speedbin;
 215         size_t len;
 216
 217         speedbin = nvmem_cell_read(speedbin_nvmem, &len);
 218
 219         if (IS_ERR(speedbin))
 220                 return PTR_ERR(speedbin);
 221
 222         switch (len) {
 223         case 4:
 224                 get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
 225                                        speedbin_nvmem, speedbin);
 226                 break;
 227         case 8:
 228                 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
 229                                        speedbin_nvmem, speedbin);
 230                 break;
 231         default:
 232                 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
 233                 return -ENODEV;
 234         }
 235
 236         snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
 237                  speed, pvs, pvs_ver);
 238
 239         drv->versions = (1 << speed);
 240
 241         kfree(speedbin);
 242         return 0;
 243 }
 244
 245 static const struct qcom_cpufreq_match_data match_data_kryo = {
 246         .get_version = qcom_cpufreq_kryo_name_version,
 247 };
 248
 249 static const struct qcom_cpufreq_match_data match_data_krait = {
 250         .get_version = qcom_cpufreq_krait_name_version,
 251 };
 252
 253 static const char *qcs404_genpd_names[] = { "cpr", NULL };
 254
 255 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
 256         .genpd_names = qcs404_genpd_names,
 257 };
 258
 259 static int qcom_cpufreq_probe(struct platform_device *pdev)
 260 {
 261         struct qcom_cpufreq_drv *drv;
 262         struct nvmem_cell *speedbin_nvmem;
 263         struct device_node *np;
 264         struct device *cpu_dev;
 265         char *pvs_name = "speedXX-pvsXX-vXX";
 266         unsigned cpu;
 267         const struct of_device_id *match;
 268         int ret;
 269
 270         cpu_dev = get_cpu_device(0);
 271         if (!cpu_dev)
 272                 return -ENODEV;
 273
 274         np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
 275         if (!np)
 276                 return -ENOENT;
 277
 278         ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
 279         if (!ret) {
 280                 of_node_put(np);
 281                 return -ENOENT;
 282         }
 283
 284         drv = kzalloc(sizeof(*drv), GFP_KERNEL);
 285         if (!drv)
 286                 return -ENOMEM;
 287
 288         match = pdev->dev.platform_data;
 289         drv->data = match->data;
 290         if (!drv->data) {
 291                 ret = -ENODEV;
 292                 goto free_drv;
 293         }
 294
 295         if (drv->data->get_version) {
 296                 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
 297                 if (IS_ERR(speedbin_nvmem)) {
 298                         if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
 299                                 dev_err(cpu_dev,
 300                                         "Could not get nvmem cell: %ld\n",
 301                                         PTR_ERR(speedbin_nvmem));
 302                         ret = PTR_ERR(speedbin_nvmem);
 303                         goto free_drv;
 304                 }
 305
 306                 ret = drv->data->get_version(cpu_dev,
 307                                                         speedbin_nvmem, &pvs_name, drv);
 308                 if (ret) {
 309                         nvmem_cell_put(speedbin_nvmem);
 310                         goto free_drv;
 311                 }
 312                 nvmem_cell_put(speedbin_nvmem);
 313         }
 314         of_node_put(np);
 315
 316         drv->opp_tokens = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tokens),
 317                                   GFP_KERNEL);
 318         if (!drv->opp_tokens) {
 319                 ret = -ENOMEM;
 320                 goto free_drv;
 321         }
 322
 323         for_each_possible_cpu(cpu) {
 324                 struct dev_pm_opp_config config = {
 325                         .supported_hw = NULL,
 326                 };
 327
 328                 cpu_dev = get_cpu_device(cpu);
 329                 if (NULL == cpu_dev) {
 330                         ret = -ENODEV;
 331                         goto free_opp;
 332                 }
 333
 334                 if (drv->data->get_version) {
 335                         config.supported_hw = &drv->versions;
 336                         config.supported_hw_count = 1;
 337
 338                         if (pvs_name)
 339                                 config.prop_name = pvs_name;
 340                 }
 341
 342                 if (drv->data->genpd_names) {
 343                         config.genpd_names = drv->data->genpd_names;
 344                         config.virt_devs = NULL;
 345                 }
 346
 347                 if (config.supported_hw || config.genpd_names) {
 348                         drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
 349                         if (drv->opp_tokens[cpu] < 0) {
 350                                 ret = drv->opp_tokens[cpu];
 351                                 dev_err(cpu_dev, "Failed to set OPP config\n");
 352                                 goto free_opp;
 353                         }
 354                 }
 355         }
 356
 357         cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
 358                                                           NULL, 0);
 359         if (!IS_ERR(cpufreq_dt_pdev)) {
 360                 platform_set_drvdata(pdev, drv);
 361                 return 0;
 362         }
 363
 364         ret = PTR_ERR(cpufreq_dt_pdev);
 365         dev_err(cpu_dev, "Failed to register platform device\n");
 366
 367 free_opp:
 368         for_each_possible_cpu(cpu)
 369                 dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
 370         kfree(drv->opp_tokens);
 371 free_drv:
 372         kfree(drv);
 373
 374         return ret;
 375 }
 376
 377 static int qcom_cpufreq_remove(struct platform_device *pdev)
 378 {
 379         struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
 380         unsigned int cpu;
 381
 382         platform_device_unregister(cpufreq_dt_pdev);
 383
 384         for_each_possible_cpu(cpu)
 385                 dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
 386
 387         kfree(drv->opp_tokens);
 388         kfree(drv);
 389
 390         return 0;
 391 }
 392
 393 static struct platform_driver qcom_cpufreq_driver = {
 394         .probe = qcom_cpufreq_probe,
 395         .remove = qcom_cpufreq_remove,
 396         .driver = {
 397                 .name = "qcom-cpufreq-nvmem",
 398         },
 399 };
 400
 401 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
 402         { .compatible = "qcom,apq8096", .data = &match_data_kryo },
 403         { .compatible = "qcom,msm8996", .data = &match_data_kryo },
 404         { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
 405         { .compatible = "qcom,ipq8064", .data = &match_data_krait },
 406         { .compatible = "qcom,apq8064", .data = &match_data_krait },
 407         { .compatible = "qcom,msm8974", .data = &match_data_krait },
 408         { .compatible = "qcom,msm8960", .data = &match_data_krait },
 409         {},
 410 };
 411 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
 412
 413 /*
 414  * Since the driver depends on smem and nvmem drivers, which may
 415  * return EPROBE_DEFER, all the real activity is done in the probe,
 416  * which may be defered as well. The init here is only registering
 417  * the driver and the platform device.
 418  */
 419 static int __init qcom_cpufreq_init(void)
 420 {
 421         struct device_node *np = of_find_node_by_path("/");
 422         const struct of_device_id *match;
 423         int ret;
 424
 425         if (!np)
 426                 return -ENODEV;
 427
 428         match = of_match_node(qcom_cpufreq_match_list, np);
 429         of_node_put(np);
 430         if (!match)
 431                 return -ENODEV;
 432
 433         ret = platform_driver_register(&qcom_cpufreq_driver);
 434         if (unlikely(ret < 0))
 435                 return ret;
 436
 437         cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
 438                                                      -1, match, sizeof(*match));
 439         ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
 440         if (0 == ret)
 441                 return 0;
 442
 443         platform_driver_unregister(&qcom_cpufreq_driver);
 444         return ret;
 445 }
 446 module_init(qcom_cpufreq_init);
 447
 448 static void __exit qcom_cpufreq_exit(void)
 449 {
 450         platform_device_unregister(cpufreq_pdev);
 451         platform_driver_unregister(&qcom_cpufreq_driver);
 452 }
 453 module_exit(qcom_cpufreq_exit);
 454
 455 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
 456 MODULE_LICENSE("GPL v2");