drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18
  19 #define LUT_MAX_ENTRIES                 40U
  20 #define LUT_SRC                         GENMASK(31, 30)
  21 #define LUT_L_VAL                       GENMASK(7, 0)
  22 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  23 #define LUT_VOLT                        GENMASK(11, 0)
  24 #define CLK_HW_DIV                      2
  25 #define LUT_TURBO_IND                   1
  26
  27 #define GT_IRQ_STATUS                   BIT(2)
  28
  29 #define HZ_PER_KHZ                      1000
  30
  31 struct qcom_cpufreq_soc_data {
  32         u32 reg_enable;
  33         u32 reg_domain_state;
  34         u32 reg_freq_lut;
  35         u32 reg_volt_lut;
  36         u32 reg_intr_clr;
  37         u32 reg_current_vote;
  38         u32 reg_perf_state;
  39         u8 lut_row_size;
  40 };
  41
  42 struct qcom_cpufreq_data {
  43         void __iomem *base;
  44         struct resource *res;
  45         const struct qcom_cpufreq_soc_data *soc_data;
  46
  47         /*
  48          * Mutex to synchronize between de-init sequence and re-starting LMh
  49          * polling/interrupts
  50          */
  51         struct mutex throttle_lock;
  52         int throttle_irq;
  53         bool cancel_throttle;
  54         struct delayed_work throttle_work;
  55         struct cpufreq_policy *policy;
  56 };
  57
  58 static unsigned long cpu_hw_rate, xo_rate;
  59 static bool icc_scaling_enabled;
  60
  61 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  62                                unsigned long freq_khz)
  63 {
  64         unsigned long freq_hz = freq_khz * 1000;
  65         struct dev_pm_opp *opp;
  66         struct device *dev;
  67         int ret;
  68
  69         dev = get_cpu_device(policy->cpu);
  70         if (!dev)
  71                 return -ENODEV;
  72
  73         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  74         if (IS_ERR(opp))
  75                 return PTR_ERR(opp);
  76
  77         ret = dev_pm_opp_set_opp(dev, opp);
  78         dev_pm_opp_put(opp);
  79         return ret;
  80 }
  81
  82 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  83                                    unsigned long freq_khz,
  84                                    unsigned long volt)
  85 {
  86         unsigned long freq_hz = freq_khz * 1000;
  87         int ret;
  88
  89         /* Skip voltage update if the opp table is not available */
  90         if (!icc_scaling_enabled)
  91                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  92
  93         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  94         if (ret) {
  95                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  96                 return ret;
  97         }
  98
  99         return dev_pm_opp_enable(cpu_dev, freq_hz);
 100 }
 101
 102 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
 103                                         unsigned int index)
 104 {
 105         struct qcom_cpufreq_data *data = policy->driver_data;
 106         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 107         unsigned long freq = policy->freq_table[index].frequency;
 108
 109         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 110
 111         if (icc_scaling_enabled)
 112                 qcom_cpufreq_set_bw(policy, freq);
 113
 114         return 0;
 115 }
 116
 117 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
 118 {
 119         struct qcom_cpufreq_data *data;
 120         const struct qcom_cpufreq_soc_data *soc_data;
 121         struct cpufreq_policy *policy;
 122         unsigned int index;
 123
 124         policy = cpufreq_cpu_get_raw(cpu);
 125         if (!policy)
 126                 return 0;
 127
 128         data = policy->driver_data;
 129         soc_data = data->soc_data;
 130
 131         index = readl_relaxed(data->base + soc_data->reg_perf_state);
 132         index = min(index, LUT_MAX_ENTRIES - 1);
 133
 134         return policy->freq_table[index].frequency;
 135 }
 136
 137 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 138                                                 unsigned int target_freq)
 139 {
 140         struct qcom_cpufreq_data *data = policy->driver_data;
 141         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 142         unsigned int index;
 143
 144         index = policy->cached_resolved_idx;
 145         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 146
 147         return policy->freq_table[index].frequency;
 148 }
 149
 150 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 151                                     struct cpufreq_policy *policy)
 152 {
 153         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 154         u32 volt;
 155         struct cpufreq_frequency_table  *table;
 156         struct dev_pm_opp *opp;
 157         unsigned long rate;
 158         int ret;
 159         struct qcom_cpufreq_data *drv_data = policy->driver_data;
 160         const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
 161
 162         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 163         if (!table)
 164                 return -ENOMEM;
 165
 166         ret = dev_pm_opp_of_add_table(cpu_dev);
 167         if (!ret) {
 168                 /* Disable all opps and cross-validate against LUT later */
 169                 icc_scaling_enabled = true;
 170                 for (rate = 0; ; rate++) {
 171                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 172                         if (IS_ERR(opp))
 173                                 break;
 174
 175                         dev_pm_opp_put(opp);
 176                         dev_pm_opp_disable(cpu_dev, rate);
 177                 }
 178         } else if (ret != -ENODEV) {
 179                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 180                 kfree(table);
 181                 return ret;
 182         } else {
 183                 policy->fast_switch_possible = true;
 184                 icc_scaling_enabled = false;
 185         }
 186
 187         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 188                 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
 189                                       i * soc_data->lut_row_size);
 190                 src = FIELD_GET(LUT_SRC, data);
 191                 lval = FIELD_GET(LUT_L_VAL, data);
 192                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 193
 194                 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
 195                                       i * soc_data->lut_row_size);
 196                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 197
 198                 if (src)
 199                         freq = xo_rate * lval / 1000;
 200                 else
 201                         freq = cpu_hw_rate / 1000;
 202
 203                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 204                         if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
 205                                 table[i].frequency = freq;
 206                                 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 207                                 freq, core_count);
 208                         } else {
 209                                 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
 210                                 table[i].frequency = CPUFREQ_ENTRY_INVALID;
 211                         }
 212
 213                 } else if (core_count == LUT_TURBO_IND) {
 214                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 215                 }
 216
 217                 /*
 218                  * Two of the same frequencies with the same core counts means
 219                  * end of table
 220                  */
 221                 if (i > 0 && prev_freq == freq) {
 222                         struct cpufreq_frequency_table *prev = &table[i - 1];
 223
 224                         /*
 225                          * Only treat the last frequency that might be a boost
 226                          * as the boost frequency
 227                          */
 228                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 229                                 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
 230                                         prev->frequency = prev_freq;
 231                                         prev->flags = CPUFREQ_BOOST_FREQ;
 232                                 } else {
 233                                         dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
 234                                                  freq);
 235                                 }
 236                         }
 237
 238                         break;
 239                 }
 240
 241                 prev_freq = freq;
 242         }
 243
 244         table[i].frequency = CPUFREQ_TABLE_END;
 245         policy->freq_table = table;
 246         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 247
 248         return 0;
 249 }
 250
 251 static void qcom_get_related_cpus(int index, struct cpumask *m)
 252 {
 253         struct device_node *cpu_np;
 254         struct of_phandle_args args;
 255         int cpu, ret;
 256
 257         for_each_possible_cpu(cpu) {
 258                 cpu_np = of_cpu_device_node_get(cpu);
 259                 if (!cpu_np)
 260                         continue;
 261
 262                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 263                                                  "#freq-domain-cells", 0,
 264                                                  &args);
 265                 of_node_put(cpu_np);
 266                 if (ret < 0)
 267                         continue;
 268
 269                 if (index == args.args[0])
 270                         cpumask_set_cpu(cpu, m);
 271         }
 272 }
 273
 274 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
 275 {
 276         unsigned int lval;
 277
 278         if (data->soc_data->reg_current_vote)
 279                 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
 280         else
 281                 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
 282
 283         return lval * xo_rate;
 284 }
 285
 286 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
 287 {
 288         unsigned long max_capacity, capacity, freq_hz, throttled_freq;
 289         struct cpufreq_policy *policy = data->policy;
 290         int cpu = cpumask_first(policy->related_cpus);
 291         struct device *dev = get_cpu_device(cpu);
 292         struct dev_pm_opp *opp;
 293
 294         /*
 295          * Get the h/w throttled frequency, normalize it using the
 296          * registered opp table and use it to calculate thermal pressure.
 297          */
 298         freq_hz = qcom_lmh_get_throttle_freq(data);
 299
 300         opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
 301         if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
 302                 dev_pm_opp_find_freq_ceil(dev, &freq_hz);
 303
 304         throttled_freq = freq_hz / HZ_PER_KHZ;
 305
 306         /* Update thermal pressure */
 307
 308         max_capacity = arch_scale_cpu_capacity(cpu);
 309         capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq);
 310
 311         /* Don't pass boost capacity to scheduler */
 312         if (capacity > max_capacity)
 313                 capacity = max_capacity;
 314
 315         arch_set_thermal_pressure(policy->related_cpus,
 316                                   max_capacity - capacity);
 317
 318         /*
 319          * In the unlikely case policy is unregistered do not enable
 320          * polling or h/w interrupt
 321          */
 322         mutex_lock(&data->throttle_lock);
 323         if (data->cancel_throttle)
 324                 goto out;
 325
 326         /*
 327          * If h/w throttled frequency is higher than what cpufreq has requested
 328          * for, then stop polling and switch back to interrupt mechanism.
 329          */
 330         if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
 331                 enable_irq(data->throttle_irq);
 332         else
 333                 mod_delayed_work(system_highpri_wq, &data->throttle_work,
 334                                  msecs_to_jiffies(10));
 335
 336 out:
 337         mutex_unlock(&data->throttle_lock);
 338 }
 339
 340 static void qcom_lmh_dcvs_poll(struct work_struct *work)
 341 {
 342         struct qcom_cpufreq_data *data;
 343
 344         data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
 345         qcom_lmh_dcvs_notify(data);
 346 }
 347
 348 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
 349 {
 350         struct qcom_cpufreq_data *c_data = data;
 351
 352         /* Disable interrupt and enable polling */
 353         disable_irq_nosync(c_data->throttle_irq);
 354         schedule_delayed_work(&c_data->throttle_work, 0);
 355
 356         if (c_data->soc_data->reg_intr_clr)
 357                 writel_relaxed(GT_IRQ_STATUS,
 358                                c_data->base + c_data->soc_data->reg_intr_clr);
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
 364         .reg_enable = 0x0,
 365         .reg_freq_lut = 0x110,
 366         .reg_volt_lut = 0x114,
 367         .reg_current_vote = 0x704,
 368         .reg_perf_state = 0x920,
 369         .lut_row_size = 32,
 370 };
 371
 372 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 373         .reg_enable = 0x0,
 374         .reg_domain_state = 0x20,
 375         .reg_freq_lut = 0x100,
 376         .reg_volt_lut = 0x200,
 377         .reg_intr_clr = 0x308,
 378         .reg_perf_state = 0x320,
 379         .lut_row_size = 4,
 380 };
 381
 382 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 383         { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
 384         { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
 385         {}
 386 };
 387 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 388
 389 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
 390 {
 391         struct qcom_cpufreq_data *data = policy->driver_data;
 392         struct platform_device *pdev = cpufreq_get_driver_data();
 393         char irq_name[15];
 394         int ret;
 395
 396         /*
 397          * Look for LMh interrupt. If no interrupt line is specified /
 398          * if there is an error, allow cpufreq to be enabled as usual.
 399          */
 400         data->throttle_irq = platform_get_irq(pdev, index);
 401         if (data->throttle_irq <= 0)
 402                 return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0;
 403
 404         data->cancel_throttle = false;
 405         data->policy = policy;
 406
 407         mutex_init(&data->throttle_lock);
 408         INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
 409
 410         snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu);
 411         ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
 412                                    IRQF_ONESHOT, irq_name, data);
 413         if (ret) {
 414                 dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret);
 415                 return 0;
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 422 {
 423         if (data->throttle_irq <= 0)
 424                 return;
 425
 426         mutex_lock(&data->throttle_lock);
 427         data->cancel_throttle = true;
 428         mutex_unlock(&data->throttle_lock);
 429
 430         cancel_delayed_work_sync(&data->throttle_work);
 431         free_irq(data->throttle_irq, data);
 432 }
 433
 434 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 435 {
 436         struct platform_device *pdev = cpufreq_get_driver_data();
 437         struct device *dev = &pdev->dev;
 438         struct of_phandle_args args;
 439         struct device_node *cpu_np;
 440         struct device *cpu_dev;
 441         struct resource *res;
 442         void __iomem *base;
 443         struct qcom_cpufreq_data *data;
 444         int ret, index;
 445
 446         cpu_dev = get_cpu_device(policy->cpu);
 447         if (!cpu_dev) {
 448                 pr_err("%s: failed to get cpu%d device\n", __func__,
 449                        policy->cpu);
 450                 return -ENODEV;
 451         }
 452
 453         cpu_np = of_cpu_device_node_get(policy->cpu);
 454         if (!cpu_np)
 455                 return -EINVAL;
 456
 457         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 458                                          "#freq-domain-cells", 0, &args);
 459         of_node_put(cpu_np);
 460         if (ret)
 461                 return ret;
 462
 463         index = args.args[0];
 464
 465         res = platform_get_resource(pdev, IORESOURCE_MEM, index);
 466         if (!res) {
 467                 dev_err(dev, "failed to get mem resource %d\n", index);
 468                 return -ENODEV;
 469         }
 470
 471         if (!request_mem_region(res->start, resource_size(res), res->name)) {
 472                 dev_err(dev, "failed to request resource %pR\n", res);
 473                 return -EBUSY;
 474         }
 475
 476         base = ioremap(res->start, resource_size(res));
 477         if (!base) {
 478                 dev_err(dev, "failed to map resource %pR\n", res);
 479                 ret = -ENOMEM;
 480                 goto release_region;
 481         }
 482
 483         data = kzalloc(sizeof(*data), GFP_KERNEL);
 484         if (!data) {
 485                 ret = -ENOMEM;
 486                 goto unmap_base;
 487         }
 488
 489         data->soc_data = of_device_get_match_data(&pdev->dev);
 490         data->base = base;
 491         data->res = res;
 492
 493         /* HW should be in enabled state to proceed */
 494         if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
 495                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 496                 ret = -ENODEV;
 497                 goto error;
 498         }
 499
 500         qcom_get_related_cpus(index, policy->cpus);
 501         if (!cpumask_weight(policy->cpus)) {
 502                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 503                 ret = -ENOENT;
 504                 goto error;
 505         }
 506
 507         policy->driver_data = data;
 508         policy->dvfs_possible_from_any_cpu = true;
 509
 510         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
 511         if (ret) {
 512                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 513                 goto error;
 514         }
 515
 516         ret = dev_pm_opp_get_opp_count(cpu_dev);
 517         if (ret <= 0) {
 518                 dev_err(cpu_dev, "Failed to add OPPs\n");
 519                 ret = -ENODEV;
 520                 goto error;
 521         }
 522
 523         if (policy_has_boost_freq(policy)) {
 524                 ret = cpufreq_enable_boost_support();
 525                 if (ret)
 526                         dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
 527         }
 528
 529         ret = qcom_cpufreq_hw_lmh_init(policy, index);
 530         if (ret)
 531                 goto error;
 532
 533         return 0;
 534 error:
 535         kfree(data);
 536 unmap_base:
 537         iounmap(base);
 538 release_region:
 539         release_mem_region(res->start, resource_size(res));
 540         return ret;
 541 }
 542
 543 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 544 {
 545         struct device *cpu_dev = get_cpu_device(policy->cpu);
 546         struct qcom_cpufreq_data *data = policy->driver_data;
 547         struct resource *res = data->res;
 548         void __iomem *base = data->base;
 549
 550         dev_pm_opp_remove_all_dynamic(cpu_dev);
 551         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 552         qcom_cpufreq_hw_lmh_exit(data);
 553         kfree(policy->freq_table);
 554         kfree(data);
 555         iounmap(base);
 556         release_mem_region(res->start, resource_size(res));
 557
 558         return 0;
 559 }
 560
 561 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 562         &cpufreq_freq_attr_scaling_available_freqs,
 563         &cpufreq_freq_attr_scaling_boost_freqs,
 564         NULL
 565 };
 566
 567 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 568         .flags          = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 569                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 570                           CPUFREQ_IS_COOLING_DEV,
 571         .verify         = cpufreq_generic_frequency_table_verify,
 572         .target_index   = qcom_cpufreq_hw_target_index,
 573         .get            = qcom_cpufreq_hw_get,
 574         .init           = qcom_cpufreq_hw_cpu_init,
 575         .exit           = qcom_cpufreq_hw_cpu_exit,
 576         .register_em    = cpufreq_register_em_with_opp,
 577         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 578         .name           = "qcom-cpufreq-hw",
 579         .attr           = qcom_cpufreq_hw_attr,
 580 };
 581
 582 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 583 {
 584         struct device *cpu_dev;
 585         struct clk *clk;
 586         int ret;
 587
 588         clk = clk_get(&pdev->dev, "xo");
 589         if (IS_ERR(clk))
 590                 return PTR_ERR(clk);
 591
 592         xo_rate = clk_get_rate(clk);
 593         clk_put(clk);
 594
 595         clk = clk_get(&pdev->dev, "alternate");
 596         if (IS_ERR(clk))
 597                 return PTR_ERR(clk);
 598
 599         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 600         clk_put(clk);
 601
 602         cpufreq_qcom_hw_driver.driver_data = pdev;
 603
 604         /* Check for optional interconnect paths on CPU0 */
 605         cpu_dev = get_cpu_device(0);
 606         if (!cpu_dev)
 607                 return -EPROBE_DEFER;
 608
 609         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 610         if (ret)
 611                 return ret;
 612
 613         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 614         if (ret)
 615                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 616         else
 617                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 618
 619         return ret;
 620 }
 621
 622 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 623 {
 624         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 625 }
 626
 627 static struct platform_driver qcom_cpufreq_hw_driver = {
 628         .probe = qcom_cpufreq_hw_driver_probe,
 629         .remove = qcom_cpufreq_hw_driver_remove,
 630         .driver = {
 631                 .name = "qcom-cpufreq-hw",
 632                 .of_match_table = qcom_cpufreq_hw_match,
 633         },
 634 };
 635
 636 static int __init qcom_cpufreq_hw_init(void)
 637 {
 638         return platform_driver_register(&qcom_cpufreq_hw_driver);
 639 }
 640 postcore_initcall(qcom_cpufreq_hw_init);
 641
 642 static void __exit qcom_cpufreq_hw_exit(void)
 643 {
 644         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 645 }
 646 module_exit(qcom_cpufreq_hw_exit);
 647
 648 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 649 MODULE_LICENSE("GPL v2");