1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitfield.h>
7 #include <linux/cpufreq.h>
8 #include <linux/init.h>
9 #include <linux/interconnect.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/pm_opp.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
19 #define LUT_MAX_ENTRIES 40U
20 #define LUT_SRC GENMASK(31, 30)
21 #define LUT_L_VAL GENMASK(7, 0)
22 #define LUT_CORE_COUNT GENMASK(18, 16)
23 #define LUT_VOLT GENMASK(11, 0)
25 #define LUT_TURBO_IND 1
27 #define HZ_PER_KHZ 1000
29 struct qcom_cpufreq_soc_data {
38 struct qcom_cpufreq_data {
41 const struct qcom_cpufreq_soc_data *soc_data;
44 * Mutex to synchronize between de-init sequence and re-starting LMh
47 struct mutex throttle_lock;
50 struct delayed_work throttle_work;
51 struct cpufreq_policy *policy;
54 static unsigned long cpu_hw_rate, xo_rate;
55 static bool icc_scaling_enabled;
57 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
58 unsigned long freq_khz)
60 unsigned long freq_hz = freq_khz * 1000;
61 struct dev_pm_opp *opp;
65 dev = get_cpu_device(policy->cpu);
69 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
73 ret = dev_pm_opp_set_opp(dev, opp);
78 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
79 unsigned long freq_khz,
82 unsigned long freq_hz = freq_khz * 1000;
85 /* Skip voltage update if the opp table is not available */
86 if (!icc_scaling_enabled)
87 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
89 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
91 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
95 return dev_pm_opp_enable(cpu_dev, freq_hz);
98 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
101 struct qcom_cpufreq_data *data = policy->driver_data;
102 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
103 unsigned long freq = policy->freq_table[index].frequency;
105 writel_relaxed(index, data->base + soc_data->reg_perf_state);
107 if (icc_scaling_enabled)
108 qcom_cpufreq_set_bw(policy, freq);
113 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
115 struct qcom_cpufreq_data *data;
116 const struct qcom_cpufreq_soc_data *soc_data;
117 struct cpufreq_policy *policy;
120 policy = cpufreq_cpu_get_raw(cpu);
124 data = policy->driver_data;
125 soc_data = data->soc_data;
127 index = readl_relaxed(data->base + soc_data->reg_perf_state);
128 index = min(index, LUT_MAX_ENTRIES - 1);
130 return policy->freq_table[index].frequency;
133 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
134 unsigned int target_freq)
136 struct qcom_cpufreq_data *data = policy->driver_data;
137 const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
140 index = policy->cached_resolved_idx;
141 writel_relaxed(index, data->base + soc_data->reg_perf_state);
143 return policy->freq_table[index].frequency;
146 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
147 struct cpufreq_policy *policy)
149 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
151 struct cpufreq_frequency_table *table;
152 struct dev_pm_opp *opp;
155 struct qcom_cpufreq_data *drv_data = policy->driver_data;
156 const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
158 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
162 ret = dev_pm_opp_of_add_table(cpu_dev);
164 /* Disable all opps and cross-validate against LUT later */
165 icc_scaling_enabled = true;
166 for (rate = 0; ; rate++) {
167 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
172 dev_pm_opp_disable(cpu_dev, rate);
174 } else if (ret != -ENODEV) {
175 dev_err(cpu_dev, "Invalid opp table in device tree\n");
178 policy->fast_switch_possible = true;
179 icc_scaling_enabled = false;
182 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
183 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
184 i * soc_data->lut_row_size);
185 src = FIELD_GET(LUT_SRC, data);
186 lval = FIELD_GET(LUT_L_VAL, data);
187 core_count = FIELD_GET(LUT_CORE_COUNT, data);
189 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
190 i * soc_data->lut_row_size);
191 volt = FIELD_GET(LUT_VOLT, data) * 1000;
194 freq = xo_rate * lval / 1000;
196 freq = cpu_hw_rate / 1000;
198 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
199 if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
200 table[i].frequency = freq;
201 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
204 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
205 table[i].frequency = CPUFREQ_ENTRY_INVALID;
208 } else if (core_count == LUT_TURBO_IND) {
209 table[i].frequency = CPUFREQ_ENTRY_INVALID;
213 * Two of the same frequencies with the same core counts means
216 if (i > 0 && prev_freq == freq) {
217 struct cpufreq_frequency_table *prev = &table[i - 1];
220 * Only treat the last frequency that might be a boost
221 * as the boost frequency
223 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
224 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
225 prev->frequency = prev_freq;
226 prev->flags = CPUFREQ_BOOST_FREQ;
228 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
239 table[i].frequency = CPUFREQ_TABLE_END;
240 policy->freq_table = table;
241 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
246 static void qcom_get_related_cpus(int index, struct cpumask *m)
248 struct device_node *cpu_np;
249 struct of_phandle_args args;
252 for_each_possible_cpu(cpu) {
253 cpu_np = of_cpu_device_node_get(cpu);
257 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
258 "#freq-domain-cells", 0,
264 if (index == args.args[0])
265 cpumask_set_cpu(cpu, m);
269 static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
271 unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote);
273 return (val & 0x3FF) * 19200;
276 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
278 unsigned long max_capacity, capacity, freq_hz, throttled_freq;
279 struct cpufreq_policy *policy = data->policy;
280 int cpu = cpumask_first(policy->cpus);
281 struct device *dev = get_cpu_device(cpu);
282 struct dev_pm_opp *opp;
286 * Get the h/w throttled frequency, normalize it using the
287 * registered opp table and use it to calculate thermal pressure.
289 freq = qcom_lmh_get_throttle_freq(data);
290 freq_hz = freq * HZ_PER_KHZ;
292 opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
293 if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
294 dev_pm_opp_find_freq_ceil(dev, &freq_hz);
296 throttled_freq = freq_hz / HZ_PER_KHZ;
298 /* Update thermal pressure */
300 max_capacity = arch_scale_cpu_capacity(cpu);
301 capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq);
303 /* Don't pass boost capacity to scheduler */
304 if (capacity > max_capacity)
305 capacity = max_capacity;
307 arch_set_thermal_pressure(policy->cpus, max_capacity - capacity);
310 * In the unlikely case policy is unregistered do not enable
311 * polling or h/w interrupt
313 mutex_lock(&data->throttle_lock);
314 if (data->cancel_throttle)
318 * If h/w throttled frequency is higher than what cpufreq has requested
319 * for, then stop polling and switch back to interrupt mechanism.
321 if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
322 enable_irq(data->throttle_irq);
324 mod_delayed_work(system_highpri_wq, &data->throttle_work,
325 msecs_to_jiffies(10));
328 mutex_unlock(&data->throttle_lock);
331 static void qcom_lmh_dcvs_poll(struct work_struct *work)
333 struct qcom_cpufreq_data *data;
335 data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
336 qcom_lmh_dcvs_notify(data);
339 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
341 struct qcom_cpufreq_data *c_data = data;
343 /* Disable interrupt and enable polling */
344 disable_irq_nosync(c_data->throttle_irq);
345 qcom_lmh_dcvs_notify(c_data);
350 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
352 .reg_freq_lut = 0x110,
353 .reg_volt_lut = 0x114,
354 .reg_current_vote = 0x704,
355 .reg_perf_state = 0x920,
359 static const struct qcom_cpufreq_soc_data epss_soc_data = {
361 .reg_freq_lut = 0x100,
362 .reg_volt_lut = 0x200,
363 .reg_perf_state = 0x320,
367 static const struct of_device_id qcom_cpufreq_hw_match[] = {
368 { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
369 { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
372 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
374 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
376 struct qcom_cpufreq_data *data = policy->driver_data;
377 struct platform_device *pdev = cpufreq_get_driver_data();
382 * Look for LMh interrupt. If no interrupt line is specified /
383 * if there is an error, allow cpufreq to be enabled as usual.
385 data->throttle_irq = platform_get_irq(pdev, index);
386 if (data->throttle_irq <= 0)
387 return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0;
389 data->cancel_throttle = false;
390 data->policy = policy;
392 mutex_init(&data->throttle_lock);
393 INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
395 snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu);
396 ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
397 IRQF_ONESHOT, irq_name, data);
399 dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret);
406 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
408 if (data->throttle_irq <= 0)
411 mutex_lock(&data->throttle_lock);
412 data->cancel_throttle = true;
413 mutex_unlock(&data->throttle_lock);
415 cancel_delayed_work_sync(&data->throttle_work);
416 free_irq(data->throttle_irq, data);
419 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
421 struct platform_device *pdev = cpufreq_get_driver_data();
422 struct device *dev = &pdev->dev;
423 struct of_phandle_args args;
424 struct device_node *cpu_np;
425 struct device *cpu_dev;
426 struct resource *res;
428 struct qcom_cpufreq_data *data;
431 cpu_dev = get_cpu_device(policy->cpu);
433 pr_err("%s: failed to get cpu%d device\n", __func__,
438 cpu_np = of_cpu_device_node_get(policy->cpu);
442 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
443 "#freq-domain-cells", 0, &args);
448 index = args.args[0];
450 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
452 dev_err(dev, "failed to get mem resource %d\n", index);
456 if (!request_mem_region(res->start, resource_size(res), res->name)) {
457 dev_err(dev, "failed to request resource %pR\n", res);
461 base = ioremap(res->start, resource_size(res));
463 dev_err(dev, "failed to map resource %pR\n", res);
468 data = kzalloc(sizeof(*data), GFP_KERNEL);
474 data->soc_data = of_device_get_match_data(&pdev->dev);
478 /* HW should be in enabled state to proceed */
479 if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
480 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
485 qcom_get_related_cpus(index, policy->cpus);
486 if (!cpumask_weight(policy->cpus)) {
487 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
492 policy->driver_data = data;
493 policy->dvfs_possible_from_any_cpu = true;
495 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
497 dev_err(dev, "Domain-%d failed to read LUT\n", index);
501 ret = dev_pm_opp_get_opp_count(cpu_dev);
503 dev_err(cpu_dev, "Failed to add OPPs\n");
508 if (policy_has_boost_freq(policy)) {
509 ret = cpufreq_enable_boost_support();
511 dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
514 ret = qcom_cpufreq_hw_lmh_init(policy, index);
524 release_mem_region(res->start, resource_size(res));
528 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
530 struct device *cpu_dev = get_cpu_device(policy->cpu);
531 struct qcom_cpufreq_data *data = policy->driver_data;
532 struct resource *res = data->res;
533 void __iomem *base = data->base;
535 dev_pm_opp_remove_all_dynamic(cpu_dev);
536 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
537 qcom_cpufreq_hw_lmh_exit(data);
538 kfree(policy->freq_table);
541 release_mem_region(res->start, resource_size(res));
546 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
547 &cpufreq_freq_attr_scaling_available_freqs,
548 &cpufreq_freq_attr_scaling_boost_freqs,
552 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
553 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
554 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
555 CPUFREQ_IS_COOLING_DEV,
556 .verify = cpufreq_generic_frequency_table_verify,
557 .target_index = qcom_cpufreq_hw_target_index,
558 .get = qcom_cpufreq_hw_get,
559 .init = qcom_cpufreq_hw_cpu_init,
560 .exit = qcom_cpufreq_hw_cpu_exit,
561 .register_em = cpufreq_register_em_with_opp,
562 .fast_switch = qcom_cpufreq_hw_fast_switch,
563 .name = "qcom-cpufreq-hw",
564 .attr = qcom_cpufreq_hw_attr,
567 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
569 struct device *cpu_dev;
573 clk = clk_get(&pdev->dev, "xo");
577 xo_rate = clk_get_rate(clk);
580 clk = clk_get(&pdev->dev, "alternate");
584 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
587 cpufreq_qcom_hw_driver.driver_data = pdev;
589 /* Check for optional interconnect paths on CPU0 */
590 cpu_dev = get_cpu_device(0);
592 return -EPROBE_DEFER;
594 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
598 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
600 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
602 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
607 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
609 return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
612 static struct platform_driver qcom_cpufreq_hw_driver = {
613 .probe = qcom_cpufreq_hw_driver_probe,
614 .remove = qcom_cpufreq_hw_driver_remove,
616 .name = "qcom-cpufreq-hw",
617 .of_match_table = qcom_cpufreq_hw_match,
621 static int __init qcom_cpufreq_hw_init(void)
623 return platform_driver_register(&qcom_cpufreq_hw_driver);
625 postcore_initcall(qcom_cpufreq_hw_init);
627 static void __exit qcom_cpufreq_hw_exit(void)
629 platform_driver_unregister(&qcom_cpufreq_hw_driver);
631 module_exit(qcom_cpufreq_hw_exit);
633 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
634 MODULE_LICENSE("GPL v2");