drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/pm_qos.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/units.h>
  20
  21 #define LUT_MAX_ENTRIES                 40U
  22 #define LUT_SRC                         GENMASK(31, 30)
  23 #define LUT_L_VAL                       GENMASK(7, 0)
  24 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  25 #define LUT_VOLT                        GENMASK(11, 0)
  26 #define CLK_HW_DIV                      2
  27 #define LUT_TURBO_IND                   1
  28
  29 #define GT_IRQ_STATUS                   BIT(2)
  30
  31 struct qcom_cpufreq_soc_data {
  32         u32 reg_enable;
  33         u32 reg_domain_state;
  34         u32 reg_dcvs_ctrl;
  35         u32 reg_freq_lut;
  36         u32 reg_volt_lut;
  37         u32 reg_intr_clr;
  38         u32 reg_current_vote;
  39         u32 reg_perf_state;
  40         u8 lut_row_size;
  41 };
  42
  43 struct qcom_cpufreq_data {
  44         void __iomem *base;
  45         struct resource *res;
  46         const struct qcom_cpufreq_soc_data *soc_data;
  47
  48         /*
  49          * Mutex to synchronize between de-init sequence and re-starting LMh
  50          * polling/interrupts
  51          */
  52         struct mutex throttle_lock;
  53         int throttle_irq;
  54         char irq_name[15];
  55         bool cancel_throttle;
  56         struct delayed_work throttle_work;
  57         struct cpufreq_policy *policy;
  58
  59         bool per_core_dcvs;
  60
  61         struct freq_qos_request throttle_freq_req;
  62 };
  63
  64 static unsigned long cpu_hw_rate, xo_rate;
  65 static bool icc_scaling_enabled;
  66
  67 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  68                                unsigned long freq_khz)
  69 {
  70         unsigned long freq_hz = freq_khz * 1000;
  71         struct dev_pm_opp *opp;
  72         struct device *dev;
  73         int ret;
  74
  75         dev = get_cpu_device(policy->cpu);
  76         if (!dev)
  77                 return -ENODEV;
  78
  79         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  80         if (IS_ERR(opp))
  81                 return PTR_ERR(opp);
  82
  83         ret = dev_pm_opp_set_opp(dev, opp);
  84         dev_pm_opp_put(opp);
  85         return ret;
  86 }
  87
  88 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  89                                    unsigned long freq_khz,
  90                                    unsigned long volt)
  91 {
  92         unsigned long freq_hz = freq_khz * 1000;
  93         int ret;
  94
  95         /* Skip voltage update if the opp table is not available */
  96         if (!icc_scaling_enabled)
  97                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  98
  99         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
 100         if (ret) {
 101                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
 102                 return ret;
 103         }
 104
 105         return dev_pm_opp_enable(cpu_dev, freq_hz);
 106 }
 107
 108 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
 109                                         unsigned int index)
 110 {
 111         struct qcom_cpufreq_data *data = policy->driver_data;
 112         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 113         unsigned long freq = policy->freq_table[index].frequency;
 114         unsigned int i;
 115
 116         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 117
 118         if (data->per_core_dcvs)
 119                 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
 120                         writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
 121
 122         if (icc_scaling_enabled)
 123                 qcom_cpufreq_set_bw(policy, freq);
 124
 125         return 0;
 126 }
 127
 128 static unsigned long qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
 129 {
 130         unsigned int lval;
 131
 132         if (data->soc_data->reg_current_vote)
 133                 lval = readl_relaxed(data->base + data->soc_data->reg_current_vote) & 0x3ff;
 134         else
 135                 lval = readl_relaxed(data->base + data->soc_data->reg_domain_state) & 0xff;
 136
 137         return lval * xo_rate;
 138 }
 139
 140 /* Get the current frequency of the CPU (after throttling) */
 141 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
 142 {
 143         struct qcom_cpufreq_data *data;
 144         struct cpufreq_policy *policy;
 145
 146         policy = cpufreq_cpu_get_raw(cpu);
 147         if (!policy)
 148                 return 0;
 149
 150         data = policy->driver_data;
 151
 152         return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ;
 153 }
 154
 155 /* Get the frequency requested by the cpufreq core for the CPU */
 156 static unsigned int qcom_cpufreq_get_freq(unsigned int cpu)
 157 {
 158         struct qcom_cpufreq_data *data;
 159         const struct qcom_cpufreq_soc_data *soc_data;
 160         struct cpufreq_policy *policy;
 161         unsigned int index;
 162
 163         policy = cpufreq_cpu_get_raw(cpu);
 164         if (!policy)
 165                 return 0;
 166
 167         data = policy->driver_data;
 168         soc_data = data->soc_data;
 169
 170         index = readl_relaxed(data->base + soc_data->reg_perf_state);
 171         index = min(index, LUT_MAX_ENTRIES - 1);
 172
 173         return policy->freq_table[index].frequency;
 174 }
 175
 176 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 177                                                 unsigned int target_freq)
 178 {
 179         struct qcom_cpufreq_data *data = policy->driver_data;
 180         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 181         unsigned int index;
 182         unsigned int i;
 183
 184         index = policy->cached_resolved_idx;
 185         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 186
 187         if (data->per_core_dcvs)
 188                 for (i = 1; i < cpumask_weight(policy->related_cpus); i++)
 189                         writel_relaxed(index, data->base + soc_data->reg_perf_state + i * 4);
 190
 191         return policy->freq_table[index].frequency;
 192 }
 193
 194 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 195                                     struct cpufreq_policy *policy)
 196 {
 197         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 198         u32 volt;
 199         struct cpufreq_frequency_table  *table;
 200         struct dev_pm_opp *opp;
 201         unsigned long rate;
 202         int ret;
 203         struct qcom_cpufreq_data *drv_data = policy->driver_data;
 204         const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
 205
 206         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 207         if (!table)
 208                 return -ENOMEM;
 209
 210         ret = dev_pm_opp_of_add_table(cpu_dev);
 211         if (!ret) {
 212                 /* Disable all opps and cross-validate against LUT later */
 213                 icc_scaling_enabled = true;
 214                 for (rate = 0; ; rate++) {
 215                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 216                         if (IS_ERR(opp))
 217                                 break;
 218
 219                         dev_pm_opp_put(opp);
 220                         dev_pm_opp_disable(cpu_dev, rate);
 221                 }
 222         } else if (ret != -ENODEV) {
 223                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 224                 kfree(table);
 225                 return ret;
 226         } else {
 227                 policy->fast_switch_possible = true;
 228                 icc_scaling_enabled = false;
 229         }
 230
 231         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 232                 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
 233                                       i * soc_data->lut_row_size);
 234                 src = FIELD_GET(LUT_SRC, data);
 235                 lval = FIELD_GET(LUT_L_VAL, data);
 236                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 237
 238                 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
 239                                       i * soc_data->lut_row_size);
 240                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 241
 242                 if (src)
 243                         freq = xo_rate * lval / 1000;
 244                 else
 245                         freq = cpu_hw_rate / 1000;
 246
 247                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 248                         if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
 249                                 table[i].frequency = freq;
 250                                 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 251                                 freq, core_count);
 252                         } else {
 253                                 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
 254                                 table[i].frequency = CPUFREQ_ENTRY_INVALID;
 255                         }
 256
 257                 } else if (core_count == LUT_TURBO_IND) {
 258                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 259                 }
 260
 261                 /*
 262                  * Two of the same frequencies with the same core counts means
 263                  * end of table
 264                  */
 265                 if (i > 0 && prev_freq == freq) {
 266                         struct cpufreq_frequency_table *prev = &table[i - 1];
 267
 268                         /*
 269                          * Only treat the last frequency that might be a boost
 270                          * as the boost frequency
 271                          */
 272                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 273                                 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
 274                                         prev->frequency = prev_freq;
 275                                         prev->flags = CPUFREQ_BOOST_FREQ;
 276                                 } else {
 277                                         dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
 278                                                  freq);
 279                                 }
 280                         }
 281
 282                         break;
 283                 }
 284
 285                 prev_freq = freq;
 286         }
 287
 288         table[i].frequency = CPUFREQ_TABLE_END;
 289         policy->freq_table = table;
 290         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 291
 292         return 0;
 293 }
 294
 295 static void qcom_get_related_cpus(int index, struct cpumask *m)
 296 {
 297         struct device_node *cpu_np;
 298         struct of_phandle_args args;
 299         int cpu, ret;
 300
 301         for_each_possible_cpu(cpu) {
 302                 cpu_np = of_cpu_device_node_get(cpu);
 303                 if (!cpu_np)
 304                         continue;
 305
 306                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 307                                                  "#freq-domain-cells", 0,
 308                                                  &args);
 309                 of_node_put(cpu_np);
 310                 if (ret < 0)
 311                         continue;
 312
 313                 if (index == args.args[0])
 314                         cpumask_set_cpu(cpu, m);
 315         }
 316 }
 317
 318 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
 319 {
 320         struct cpufreq_policy *policy = data->policy;
 321         int cpu = cpumask_first(policy->related_cpus);
 322         struct device *dev = get_cpu_device(cpu);
 323         unsigned long freq_hz, throttled_freq;
 324         struct dev_pm_opp *opp;
 325
 326         /*
 327          * Get the h/w throttled frequency, normalize it using the
 328          * registered opp table and use it to calculate thermal pressure.
 329          */
 330         freq_hz = qcom_lmh_get_throttle_freq(data);
 331
 332         opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
 333         if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
 334                 opp = dev_pm_opp_find_freq_ceil(dev, &freq_hz);
 335
 336         if (IS_ERR(opp)) {
 337                 dev_warn(dev, "Can't find the OPP for throttling: %pe!\n", opp);
 338         } else {
 339                 dev_pm_opp_put(opp);
 340         }
 341
 342         throttled_freq = freq_hz / HZ_PER_KHZ;
 343
 344         freq_qos_update_request(&data->throttle_freq_req, throttled_freq);
 345
 346         /* Update thermal pressure (the boost frequencies are accepted) */
 347         arch_update_thermal_pressure(policy->related_cpus, throttled_freq);
 348
 349         /*
 350          * In the unlikely case policy is unregistered do not enable
 351          * polling or h/w interrupt
 352          */
 353         mutex_lock(&data->throttle_lock);
 354         if (data->cancel_throttle)
 355                 goto out;
 356
 357         /*
 358          * If h/w throttled frequency is higher than what cpufreq has requested
 359          * for, then stop polling and switch back to interrupt mechanism.
 360          */
 361         if (throttled_freq >= qcom_cpufreq_get_freq(cpu))
 362                 enable_irq(data->throttle_irq);
 363         else
 364                 mod_delayed_work(system_highpri_wq, &data->throttle_work,
 365                                  msecs_to_jiffies(10));
 366
 367 out:
 368         mutex_unlock(&data->throttle_lock);
 369 }
 370
 371 static void qcom_lmh_dcvs_poll(struct work_struct *work)
 372 {
 373         struct qcom_cpufreq_data *data;
 374
 375         data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
 376         qcom_lmh_dcvs_notify(data);
 377 }
 378
 379 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
 380 {
 381         struct qcom_cpufreq_data *c_data = data;
 382
 383         /* Disable interrupt and enable polling */
 384         disable_irq_nosync(c_data->throttle_irq);
 385         schedule_delayed_work(&c_data->throttle_work, 0);
 386
 387         if (c_data->soc_data->reg_intr_clr)
 388                 writel_relaxed(GT_IRQ_STATUS,
 389                                c_data->base + c_data->soc_data->reg_intr_clr);
 390
 391         return IRQ_HANDLED;
 392 }
 393
 394 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
 395         .reg_enable = 0x0,
 396         .reg_dcvs_ctrl = 0xbc,
 397         .reg_freq_lut = 0x110,
 398         .reg_volt_lut = 0x114,
 399         .reg_current_vote = 0x704,
 400         .reg_perf_state = 0x920,
 401         .lut_row_size = 32,
 402 };
 403
 404 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 405         .reg_enable = 0x0,
 406         .reg_domain_state = 0x20,
 407         .reg_dcvs_ctrl = 0xb0,
 408         .reg_freq_lut = 0x100,
 409         .reg_volt_lut = 0x200,
 410         .reg_intr_clr = 0x308,
 411         .reg_perf_state = 0x320,
 412         .lut_row_size = 4,
 413 };
 414
 415 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 416         { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
 417         { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
 418         {}
 419 };
 420 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 421
 422 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
 423 {
 424         struct qcom_cpufreq_data *data = policy->driver_data;
 425         struct platform_device *pdev = cpufreq_get_driver_data();
 426         int ret;
 427
 428         /*
 429          * Look for LMh interrupt. If no interrupt line is specified /
 430          * if there is an error, allow cpufreq to be enabled as usual.
 431          */
 432         data->throttle_irq = platform_get_irq_optional(pdev, index);
 433         if (data->throttle_irq == -ENXIO)
 434                 return 0;
 435         if (data->throttle_irq < 0)
 436                 return data->throttle_irq;
 437
 438         ret = freq_qos_add_request(&policy->constraints,
 439                                    &data->throttle_freq_req, FREQ_QOS_MAX,
 440                                    FREQ_QOS_MAX_DEFAULT_VALUE);
 441         if (ret < 0) {
 442                 dev_err(&pdev->dev, "Failed to add freq constraint (%d)\n", ret);
 443                 return ret;
 444         }
 445
 446         data->cancel_throttle = false;
 447         data->policy = policy;
 448
 449         mutex_init(&data->throttle_lock);
 450         INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
 451
 452         snprintf(data->irq_name, sizeof(data->irq_name), "dcvsh-irq-%u", policy->cpu);
 453         ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
 454                                    IRQF_ONESHOT | IRQF_NO_AUTOEN, data->irq_name, data);
 455         if (ret) {
 456                 dev_err(&pdev->dev, "Error registering %s: %d\n", data->irq_name, ret);
 457                 return 0;
 458         }
 459
 460         ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
 461         if (ret)
 462                 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
 463                         data->irq_name, data->throttle_irq);
 464
 465         return 0;
 466 }
 467
 468 static int qcom_cpufreq_hw_cpu_online(struct cpufreq_policy *policy)
 469 {
 470         struct qcom_cpufreq_data *data = policy->driver_data;
 471         struct platform_device *pdev = cpufreq_get_driver_data();
 472         int ret;
 473
 474         if (data->throttle_irq <= 0)
 475                 return 0;
 476
 477         mutex_lock(&data->throttle_lock);
 478         data->cancel_throttle = false;
 479         mutex_unlock(&data->throttle_lock);
 480
 481         ret = irq_set_affinity_and_hint(data->throttle_irq, policy->cpus);
 482         if (ret)
 483                 dev_err(&pdev->dev, "Failed to set CPU affinity of %s[%d]\n",
 484                         data->irq_name, data->throttle_irq);
 485
 486         return ret;
 487 }
 488
 489 static int qcom_cpufreq_hw_cpu_offline(struct cpufreq_policy *policy)
 490 {
 491         struct qcom_cpufreq_data *data = policy->driver_data;
 492
 493         if (data->throttle_irq <= 0)
 494                 return 0;
 495
 496         mutex_lock(&data->throttle_lock);
 497         data->cancel_throttle = true;
 498         mutex_unlock(&data->throttle_lock);
 499
 500         cancel_delayed_work_sync(&data->throttle_work);
 501         irq_set_affinity_and_hint(data->throttle_irq, NULL);
 502         disable_irq_nosync(data->throttle_irq);
 503
 504         return 0;
 505 }
 506
 507 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 508 {
 509         if (data->throttle_irq <= 0)
 510                 return;
 511
 512         freq_qos_remove_request(&data->throttle_freq_req);
 513         free_irq(data->throttle_irq, data);
 514 }
 515
 516 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 517 {
 518         struct platform_device *pdev = cpufreq_get_driver_data();
 519         struct device *dev = &pdev->dev;
 520         struct of_phandle_args args;
 521         struct device_node *cpu_np;
 522         struct device *cpu_dev;
 523         struct resource *res;
 524         void __iomem *base;
 525         struct qcom_cpufreq_data *data;
 526         int ret, index;
 527
 528         cpu_dev = get_cpu_device(policy->cpu);
 529         if (!cpu_dev) {
 530                 pr_err("%s: failed to get cpu%d device\n", __func__,
 531                        policy->cpu);
 532                 return -ENODEV;
 533         }
 534
 535         cpu_np = of_cpu_device_node_get(policy->cpu);
 536         if (!cpu_np)
 537                 return -EINVAL;
 538
 539         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 540                                          "#freq-domain-cells", 0, &args);
 541         of_node_put(cpu_np);
 542         if (ret)
 543                 return ret;
 544
 545         index = args.args[0];
 546
 547         res = platform_get_resource(pdev, IORESOURCE_MEM, index);
 548         if (!res) {
 549                 dev_err(dev, "failed to get mem resource %d\n", index);
 550                 return -ENODEV;
 551         }
 552
 553         if (!request_mem_region(res->start, resource_size(res), res->name)) {
 554                 dev_err(dev, "failed to request resource %pR\n", res);
 555                 return -EBUSY;
 556         }
 557
 558         base = ioremap(res->start, resource_size(res));
 559         if (!base) {
 560                 dev_err(dev, "failed to map resource %pR\n", res);
 561                 ret = -ENOMEM;
 562                 goto release_region;
 563         }
 564
 565         data = kzalloc(sizeof(*data), GFP_KERNEL);
 566         if (!data) {
 567                 ret = -ENOMEM;
 568                 goto unmap_base;
 569         }
 570
 571         data->soc_data = of_device_get_match_data(&pdev->dev);
 572         data->base = base;
 573         data->res = res;
 574
 575         /* HW should be in enabled state to proceed */
 576         if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
 577                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 578                 ret = -ENODEV;
 579                 goto error;
 580         }
 581
 582         if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1)
 583                 data->per_core_dcvs = true;
 584
 585         qcom_get_related_cpus(index, policy->cpus);
 586         if (cpumask_empty(policy->cpus)) {
 587                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 588                 ret = -ENOENT;
 589                 goto error;
 590         }
 591
 592         policy->driver_data = data;
 593         policy->dvfs_possible_from_any_cpu = true;
 594
 595         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
 596         if (ret) {
 597                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 598                 goto error;
 599         }
 600
 601         ret = dev_pm_opp_get_opp_count(cpu_dev);
 602         if (ret <= 0) {
 603                 dev_err(cpu_dev, "Failed to add OPPs\n");
 604                 ret = -ENODEV;
 605                 goto error;
 606         }
 607
 608         if (policy_has_boost_freq(policy)) {
 609                 ret = cpufreq_enable_boost_support();
 610                 if (ret)
 611                         dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
 612         }
 613
 614         ret = qcom_cpufreq_hw_lmh_init(policy, index);
 615         if (ret)
 616                 goto error;
 617
 618         return 0;
 619 error:
 620         kfree(data);
 621 unmap_base:
 622         iounmap(base);
 623 release_region:
 624         release_mem_region(res->start, resource_size(res));
 625         return ret;
 626 }
 627
 628 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 629 {
 630         struct device *cpu_dev = get_cpu_device(policy->cpu);
 631         struct qcom_cpufreq_data *data = policy->driver_data;
 632         struct resource *res = data->res;
 633         void __iomem *base = data->base;
 634
 635         dev_pm_opp_remove_all_dynamic(cpu_dev);
 636         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 637         qcom_cpufreq_hw_lmh_exit(data);
 638         kfree(policy->freq_table);
 639         kfree(data);
 640         iounmap(base);
 641         release_mem_region(res->start, resource_size(res));
 642
 643         return 0;
 644 }
 645
 646 static void qcom_cpufreq_ready(struct cpufreq_policy *policy)
 647 {
 648         struct qcom_cpufreq_data *data = policy->driver_data;
 649
 650         if (data->throttle_irq >= 0)
 651                 enable_irq(data->throttle_irq);
 652 }
 653
 654 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 655         &cpufreq_freq_attr_scaling_available_freqs,
 656         &cpufreq_freq_attr_scaling_boost_freqs,
 657         NULL
 658 };
 659
 660 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 661         .flags          = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 662                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 663                           CPUFREQ_IS_COOLING_DEV,
 664         .verify         = cpufreq_generic_frequency_table_verify,
 665         .target_index   = qcom_cpufreq_hw_target_index,
 666         .get            = qcom_cpufreq_hw_get,
 667         .init           = qcom_cpufreq_hw_cpu_init,
 668         .exit           = qcom_cpufreq_hw_cpu_exit,
 669         .online         = qcom_cpufreq_hw_cpu_online,
 670         .offline        = qcom_cpufreq_hw_cpu_offline,
 671         .register_em    = cpufreq_register_em_with_opp,
 672         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 673         .name           = "qcom-cpufreq-hw",
 674         .attr           = qcom_cpufreq_hw_attr,
 675         .ready          = qcom_cpufreq_ready,
 676 };
 677
 678 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 679 {
 680         struct device *cpu_dev;
 681         struct clk *clk;
 682         int ret;
 683
 684         clk = clk_get(&pdev->dev, "xo");
 685         if (IS_ERR(clk))
 686                 return PTR_ERR(clk);
 687
 688         xo_rate = clk_get_rate(clk);
 689         clk_put(clk);
 690
 691         clk = clk_get(&pdev->dev, "alternate");
 692         if (IS_ERR(clk))
 693                 return PTR_ERR(clk);
 694
 695         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 696         clk_put(clk);
 697
 698         cpufreq_qcom_hw_driver.driver_data = pdev;
 699
 700         /* Check for optional interconnect paths on CPU0 */
 701         cpu_dev = get_cpu_device(0);
 702         if (!cpu_dev)
 703                 return -EPROBE_DEFER;
 704
 705         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 706         if (ret)
 707                 return ret;
 708
 709         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 710         if (ret)
 711                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 712         else
 713                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 714
 715         return ret;
 716 }
 717
 718 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 719 {
 720         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 721 }
 722
 723 static struct platform_driver qcom_cpufreq_hw_driver = {
 724         .probe = qcom_cpufreq_hw_driver_probe,
 725         .remove = qcom_cpufreq_hw_driver_remove,
 726         .driver = {
 727                 .name = "qcom-cpufreq-hw",
 728                 .of_match_table = qcom_cpufreq_hw_match,
 729         },
 730 };
 731
 732 static int __init qcom_cpufreq_hw_init(void)
 733 {
 734         return platform_driver_register(&qcom_cpufreq_hw_driver);
 735 }
 736 postcore_initcall(qcom_cpufreq_hw_init);
 737
 738 static void __exit qcom_cpufreq_hw_exit(void)
 739 {
 740         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 741 }
 742 module_exit(qcom_cpufreq_hw_exit);
 743
 744 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 745 MODULE_LICENSE("GPL v2");