drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18
  19 #define LUT_MAX_ENTRIES                 40U
  20 #define LUT_SRC                         GENMASK(31, 30)
  21 #define LUT_L_VAL                       GENMASK(7, 0)
  22 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  23 #define LUT_VOLT                        GENMASK(11, 0)
  24 #define CLK_HW_DIV                      2
  25 #define LUT_TURBO_IND                   1
  26
  27 #define HZ_PER_KHZ                      1000
  28
  29 struct qcom_cpufreq_soc_data {
  30         u32 reg_enable;
  31         u32 reg_freq_lut;
  32         u32 reg_volt_lut;
  33         u32 reg_current_vote;
  34         u32 reg_perf_state;
  35         u8 lut_row_size;
  36 };
  37
  38 struct qcom_cpufreq_data {
  39         void __iomem *base;
  40         struct resource *res;
  41         const struct qcom_cpufreq_soc_data *soc_data;
  42
  43         /*
  44          * Mutex to synchronize between de-init sequence and re-starting LMh
  45          * polling/interrupts
  46          */
  47         struct mutex throttle_lock;
  48         int throttle_irq;
  49         bool cancel_throttle;
  50         struct delayed_work throttle_work;
  51         struct cpufreq_policy *policy;
  52 };
  53
  54 static unsigned long cpu_hw_rate, xo_rate;
  55 static bool icc_scaling_enabled;
  56
  57 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  58                                unsigned long freq_khz)
  59 {
  60         unsigned long freq_hz = freq_khz * 1000;
  61         struct dev_pm_opp *opp;
  62         struct device *dev;
  63         int ret;
  64
  65         dev = get_cpu_device(policy->cpu);
  66         if (!dev)
  67                 return -ENODEV;
  68
  69         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  70         if (IS_ERR(opp))
  71                 return PTR_ERR(opp);
  72
  73         ret = dev_pm_opp_set_opp(dev, opp);
  74         dev_pm_opp_put(opp);
  75         return ret;
  76 }
  77
  78 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  79                                    unsigned long freq_khz,
  80                                    unsigned long volt)
  81 {
  82         unsigned long freq_hz = freq_khz * 1000;
  83         int ret;
  84
  85         /* Skip voltage update if the opp table is not available */
  86         if (!icc_scaling_enabled)
  87                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  88
  89         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  90         if (ret) {
  91                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  92                 return ret;
  93         }
  94
  95         return dev_pm_opp_enable(cpu_dev, freq_hz);
  96 }
  97
  98 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
  99                                         unsigned int index)
 100 {
 101         struct qcom_cpufreq_data *data = policy->driver_data;
 102         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 103         unsigned long freq = policy->freq_table[index].frequency;
 104
 105         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 106
 107         if (icc_scaling_enabled)
 108                 qcom_cpufreq_set_bw(policy, freq);
 109
 110         return 0;
 111 }
 112
 113 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
 114 {
 115         struct qcom_cpufreq_data *data;
 116         const struct qcom_cpufreq_soc_data *soc_data;
 117         struct cpufreq_policy *policy;
 118         unsigned int index;
 119
 120         policy = cpufreq_cpu_get_raw(cpu);
 121         if (!policy)
 122                 return 0;
 123
 124         data = policy->driver_data;
 125         soc_data = data->soc_data;
 126
 127         index = readl_relaxed(data->base + soc_data->reg_perf_state);
 128         index = min(index, LUT_MAX_ENTRIES - 1);
 129
 130         return policy->freq_table[index].frequency;
 131 }
 132
 133 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 134                                                 unsigned int target_freq)
 135 {
 136         struct qcom_cpufreq_data *data = policy->driver_data;
 137         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 138         unsigned int index;
 139
 140         index = policy->cached_resolved_idx;
 141         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 142
 143         return policy->freq_table[index].frequency;
 144 }
 145
 146 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 147                                     struct cpufreq_policy *policy)
 148 {
 149         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 150         u32 volt;
 151         struct cpufreq_frequency_table  *table;
 152         struct dev_pm_opp *opp;
 153         unsigned long rate;
 154         int ret;
 155         struct qcom_cpufreq_data *drv_data = policy->driver_data;
 156         const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
 157
 158         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 159         if (!table)
 160                 return -ENOMEM;
 161
 162         ret = dev_pm_opp_of_add_table(cpu_dev);
 163         if (!ret) {
 164                 /* Disable all opps and cross-validate against LUT later */
 165                 icc_scaling_enabled = true;
 166                 for (rate = 0; ; rate++) {
 167                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 168                         if (IS_ERR(opp))
 169                                 break;
 170
 171                         dev_pm_opp_put(opp);
 172                         dev_pm_opp_disable(cpu_dev, rate);
 173                 }
 174         } else if (ret != -ENODEV) {
 175                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 176                 return ret;
 177         } else {
 178                 policy->fast_switch_possible = true;
 179                 icc_scaling_enabled = false;
 180         }
 181
 182         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 183                 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
 184                                       i * soc_data->lut_row_size);
 185                 src = FIELD_GET(LUT_SRC, data);
 186                 lval = FIELD_GET(LUT_L_VAL, data);
 187                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 188
 189                 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
 190                                       i * soc_data->lut_row_size);
 191                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 192
 193                 if (src)
 194                         freq = xo_rate * lval / 1000;
 195                 else
 196                         freq = cpu_hw_rate / 1000;
 197
 198                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 199                         if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
 200                                 table[i].frequency = freq;
 201                                 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 202                                 freq, core_count);
 203                         } else {
 204                                 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
 205                                 table[i].frequency = CPUFREQ_ENTRY_INVALID;
 206                         }
 207
 208                 } else if (core_count == LUT_TURBO_IND) {
 209                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 210                 }
 211
 212                 /*
 213                  * Two of the same frequencies with the same core counts means
 214                  * end of table
 215                  */
 216                 if (i > 0 && prev_freq == freq) {
 217                         struct cpufreq_frequency_table *prev = &table[i - 1];
 218
 219                         /*
 220                          * Only treat the last frequency that might be a boost
 221                          * as the boost frequency
 222                          */
 223                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 224                                 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
 225                                         prev->frequency = prev_freq;
 226                                         prev->flags = CPUFREQ_BOOST_FREQ;
 227                                 } else {
 228                                         dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
 229                                                  freq);
 230                                 }
 231                         }
 232
 233                         break;
 234                 }
 235
 236                 prev_freq = freq;
 237         }
 238
 239         table[i].frequency = CPUFREQ_TABLE_END;
 240         policy->freq_table = table;
 241         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 242
 243         return 0;
 244 }
 245
 246 static void qcom_get_related_cpus(int index, struct cpumask *m)
 247 {
 248         struct device_node *cpu_np;
 249         struct of_phandle_args args;
 250         int cpu, ret;
 251
 252         for_each_possible_cpu(cpu) {
 253                 cpu_np = of_cpu_device_node_get(cpu);
 254                 if (!cpu_np)
 255                         continue;
 256
 257                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 258                                                  "#freq-domain-cells", 0,
 259                                                  &args);
 260                 of_node_put(cpu_np);
 261                 if (ret < 0)
 262                         continue;
 263
 264                 if (index == args.args[0])
 265                         cpumask_set_cpu(cpu, m);
 266         }
 267 }
 268
 269 static unsigned int qcom_lmh_get_throttle_freq(struct qcom_cpufreq_data *data)
 270 {
 271         unsigned int val = readl_relaxed(data->base + data->soc_data->reg_current_vote);
 272
 273         return (val & 0x3FF) * 19200;
 274 }
 275
 276 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data)
 277 {
 278         unsigned long max_capacity, capacity, freq_hz, throttled_freq;
 279         struct cpufreq_policy *policy = data->policy;
 280         int cpu = cpumask_first(policy->cpus);
 281         struct device *dev = get_cpu_device(cpu);
 282         struct dev_pm_opp *opp;
 283         unsigned int freq;
 284
 285         /*
 286          * Get the h/w throttled frequency, normalize it using the
 287          * registered opp table and use it to calculate thermal pressure.
 288          */
 289         freq = qcom_lmh_get_throttle_freq(data);
 290         freq_hz = freq * HZ_PER_KHZ;
 291
 292         opp = dev_pm_opp_find_freq_floor(dev, &freq_hz);
 293         if (IS_ERR(opp) && PTR_ERR(opp) == -ERANGE)
 294                 dev_pm_opp_find_freq_ceil(dev, &freq_hz);
 295
 296         throttled_freq = freq_hz / HZ_PER_KHZ;
 297
 298         /* Update thermal pressure */
 299
 300         max_capacity = arch_scale_cpu_capacity(cpu);
 301         capacity = mult_frac(max_capacity, throttled_freq, policy->cpuinfo.max_freq);
 302
 303         /* Don't pass boost capacity to scheduler */
 304         if (capacity > max_capacity)
 305                 capacity = max_capacity;
 306
 307         arch_set_thermal_pressure(policy->related_cpus,
 308                                   max_capacity - capacity);
 309
 310         /*
 311          * In the unlikely case policy is unregistered do not enable
 312          * polling or h/w interrupt
 313          */
 314         mutex_lock(&data->throttle_lock);
 315         if (data->cancel_throttle)
 316                 goto out;
 317
 318         /*
 319          * If h/w throttled frequency is higher than what cpufreq has requested
 320          * for, then stop polling and switch back to interrupt mechanism.
 321          */
 322         if (throttled_freq >= qcom_cpufreq_hw_get(cpu))
 323                 enable_irq(data->throttle_irq);
 324         else
 325                 mod_delayed_work(system_highpri_wq, &data->throttle_work,
 326                                  msecs_to_jiffies(10));
 327
 328 out:
 329         mutex_unlock(&data->throttle_lock);
 330 }
 331
 332 static void qcom_lmh_dcvs_poll(struct work_struct *work)
 333 {
 334         struct qcom_cpufreq_data *data;
 335
 336         data = container_of(work, struct qcom_cpufreq_data, throttle_work.work);
 337         qcom_lmh_dcvs_notify(data);
 338 }
 339
 340 static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, void *data)
 341 {
 342         struct qcom_cpufreq_data *c_data = data;
 343
 344         /* Disable interrupt and enable polling */
 345         disable_irq_nosync(c_data->throttle_irq);
 346         schedule_delayed_work(&c_data->throttle_work, 0);
 347
 348         return IRQ_HANDLED;
 349 }
 350
 351 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
 352         .reg_enable = 0x0,
 353         .reg_freq_lut = 0x110,
 354         .reg_volt_lut = 0x114,
 355         .reg_current_vote = 0x704,
 356         .reg_perf_state = 0x920,
 357         .lut_row_size = 32,
 358 };
 359
 360 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 361         .reg_enable = 0x0,
 362         .reg_freq_lut = 0x100,
 363         .reg_volt_lut = 0x200,
 364         .reg_perf_state = 0x320,
 365         .lut_row_size = 4,
 366 };
 367
 368 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 369         { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
 370         { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
 371         {}
 372 };
 373 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 374
 375 static int qcom_cpufreq_hw_lmh_init(struct cpufreq_policy *policy, int index)
 376 {
 377         struct qcom_cpufreq_data *data = policy->driver_data;
 378         struct platform_device *pdev = cpufreq_get_driver_data();
 379         char irq_name[15];
 380         int ret;
 381
 382         /*
 383          * Look for LMh interrupt. If no interrupt line is specified /
 384          * if there is an error, allow cpufreq to be enabled as usual.
 385          */
 386         data->throttle_irq = platform_get_irq(pdev, index);
 387         if (data->throttle_irq <= 0)
 388                 return data->throttle_irq == -EPROBE_DEFER ? -EPROBE_DEFER : 0;
 389
 390         data->cancel_throttle = false;
 391         data->policy = policy;
 392
 393         mutex_init(&data->throttle_lock);
 394         INIT_DEFERRABLE_WORK(&data->throttle_work, qcom_lmh_dcvs_poll);
 395
 396         snprintf(irq_name, sizeof(irq_name), "dcvsh-irq-%u", policy->cpu);
 397         ret = request_threaded_irq(data->throttle_irq, NULL, qcom_lmh_dcvs_handle_irq,
 398                                    IRQF_ONESHOT, irq_name, data);
 399         if (ret) {
 400                 dev_err(&pdev->dev, "Error registering %s: %d\n", irq_name, ret);
 401                 return 0;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data)
 408 {
 409         if (data->throttle_irq <= 0)
 410                 return;
 411
 412         mutex_lock(&data->throttle_lock);
 413         data->cancel_throttle = true;
 414         mutex_unlock(&data->throttle_lock);
 415
 416         cancel_delayed_work_sync(&data->throttle_work);
 417         free_irq(data->throttle_irq, data);
 418 }
 419
 420 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 421 {
 422         struct platform_device *pdev = cpufreq_get_driver_data();
 423         struct device *dev = &pdev->dev;
 424         struct of_phandle_args args;
 425         struct device_node *cpu_np;
 426         struct device *cpu_dev;
 427         struct resource *res;
 428         void __iomem *base;
 429         struct qcom_cpufreq_data *data;
 430         int ret, index;
 431
 432         cpu_dev = get_cpu_device(policy->cpu);
 433         if (!cpu_dev) {
 434                 pr_err("%s: failed to get cpu%d device\n", __func__,
 435                        policy->cpu);
 436                 return -ENODEV;
 437         }
 438
 439         cpu_np = of_cpu_device_node_get(policy->cpu);
 440         if (!cpu_np)
 441                 return -EINVAL;
 442
 443         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 444                                          "#freq-domain-cells", 0, &args);
 445         of_node_put(cpu_np);
 446         if (ret)
 447                 return ret;
 448
 449         index = args.args[0];
 450
 451         res = platform_get_resource(pdev, IORESOURCE_MEM, index);
 452         if (!res) {
 453                 dev_err(dev, "failed to get mem resource %d\n", index);
 454                 return -ENODEV;
 455         }
 456
 457         if (!request_mem_region(res->start, resource_size(res), res->name)) {
 458                 dev_err(dev, "failed to request resource %pR\n", res);
 459                 return -EBUSY;
 460         }
 461
 462         base = ioremap(res->start, resource_size(res));
 463         if (!base) {
 464                 dev_err(dev, "failed to map resource %pR\n", res);
 465                 ret = -ENOMEM;
 466                 goto release_region;
 467         }
 468
 469         data = kzalloc(sizeof(*data), GFP_KERNEL);
 470         if (!data) {
 471                 ret = -ENOMEM;
 472                 goto unmap_base;
 473         }
 474
 475         data->soc_data = of_device_get_match_data(&pdev->dev);
 476         data->base = base;
 477         data->res = res;
 478
 479         /* HW should be in enabled state to proceed */
 480         if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
 481                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 482                 ret = -ENODEV;
 483                 goto error;
 484         }
 485
 486         qcom_get_related_cpus(index, policy->cpus);
 487         if (!cpumask_weight(policy->cpus)) {
 488                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 489                 ret = -ENOENT;
 490                 goto error;
 491         }
 492
 493         policy->driver_data = data;
 494         policy->dvfs_possible_from_any_cpu = true;
 495
 496         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
 497         if (ret) {
 498                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 499                 goto error;
 500         }
 501
 502         ret = dev_pm_opp_get_opp_count(cpu_dev);
 503         if (ret <= 0) {
 504                 dev_err(cpu_dev, "Failed to add OPPs\n");
 505                 ret = -ENODEV;
 506                 goto error;
 507         }
 508
 509         if (policy_has_boost_freq(policy)) {
 510                 ret = cpufreq_enable_boost_support();
 511                 if (ret)
 512                         dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
 513         }
 514
 515         ret = qcom_cpufreq_hw_lmh_init(policy, index);
 516         if (ret)
 517                 goto error;
 518
 519         return 0;
 520 error:
 521         kfree(data);
 522 unmap_base:
 523         iounmap(base);
 524 release_region:
 525         release_mem_region(res->start, resource_size(res));
 526         return ret;
 527 }
 528
 529 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 530 {
 531         struct device *cpu_dev = get_cpu_device(policy->cpu);
 532         struct qcom_cpufreq_data *data = policy->driver_data;
 533         struct resource *res = data->res;
 534         void __iomem *base = data->base;
 535
 536         dev_pm_opp_remove_all_dynamic(cpu_dev);
 537         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 538         qcom_cpufreq_hw_lmh_exit(data);
 539         kfree(policy->freq_table);
 540         kfree(data);
 541         iounmap(base);
 542         release_mem_region(res->start, resource_size(res));
 543
 544         return 0;
 545 }
 546
 547 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 548         &cpufreq_freq_attr_scaling_available_freqs,
 549         &cpufreq_freq_attr_scaling_boost_freqs,
 550         NULL
 551 };
 552
 553 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 554         .flags          = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 555                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 556                           CPUFREQ_IS_COOLING_DEV,
 557         .verify         = cpufreq_generic_frequency_table_verify,
 558         .target_index   = qcom_cpufreq_hw_target_index,
 559         .get            = qcom_cpufreq_hw_get,
 560         .init           = qcom_cpufreq_hw_cpu_init,
 561         .exit           = qcom_cpufreq_hw_cpu_exit,
 562         .register_em    = cpufreq_register_em_with_opp,
 563         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 564         .name           = "qcom-cpufreq-hw",
 565         .attr           = qcom_cpufreq_hw_attr,
 566 };
 567
 568 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 569 {
 570         struct device *cpu_dev;
 571         struct clk *clk;
 572         int ret;
 573
 574         clk = clk_get(&pdev->dev, "xo");
 575         if (IS_ERR(clk))
 576                 return PTR_ERR(clk);
 577
 578         xo_rate = clk_get_rate(clk);
 579         clk_put(clk);
 580
 581         clk = clk_get(&pdev->dev, "alternate");
 582         if (IS_ERR(clk))
 583                 return PTR_ERR(clk);
 584
 585         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 586         clk_put(clk);
 587
 588         cpufreq_qcom_hw_driver.driver_data = pdev;
 589
 590         /* Check for optional interconnect paths on CPU0 */
 591         cpu_dev = get_cpu_device(0);
 592         if (!cpu_dev)
 593                 return -EPROBE_DEFER;
 594
 595         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 596         if (ret)
 597                 return ret;
 598
 599         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 600         if (ret)
 601                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 602         else
 603                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 604
 605         return ret;
 606 }
 607
 608 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 609 {
 610         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 611 }
 612
 613 static struct platform_driver qcom_cpufreq_hw_driver = {
 614         .probe = qcom_cpufreq_hw_driver_probe,
 615         .remove = qcom_cpufreq_hw_driver_remove,
 616         .driver = {
 617                 .name = "qcom-cpufreq-hw",
 618                 .of_match_table = qcom_cpufreq_hw_match,
 619         },
 620 };
 621
 622 static int __init qcom_cpufreq_hw_init(void)
 623 {
 624         return platform_driver_register(&qcom_cpufreq_hw_driver);
 625 }
 626 postcore_initcall(qcom_cpufreq_hw_init);
 627
 628 static void __exit qcom_cpufreq_hw_exit(void)
 629 {
 630         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 631 }
 632 module_exit(qcom_cpufreq_hw_exit);
 633
 634 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 635 MODULE_LICENSE("GPL v2");