drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/div64.h>
  32 #include <asm/msr.h>
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/cpufeature.h>
  35 #include <asm/intel-family.h>
  36 #include "../drivers/thermal/intel/thermal_interrupt.h"
  37
  38 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP      5000
  42 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  43
  44 #ifdef CONFIG_ACPI
  45 #include <acpi/processor.h>
  46 #include <acpi/cppc_acpi.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  54
  55 #define EXT_BITS 6
  56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  59
  60 static inline int32_t mul_fp(int32_t x, int32_t y)
  61 {
  62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  63 }
  64
  65 static inline int32_t div_fp(s64 x, s64 y)
  66 {
  67         return div64_s64((int64_t)x << FRAC_BITS, y);
  68 }
  69
  70 static inline int ceiling_fp(int32_t x)
  71 {
  72         int mask, ret;
  73
  74         ret = fp_toint(x);
  75         mask = (1 << FRAC_BITS) - 1;
  76         if (x & mask)
  77                 ret += 1;
  78         return ret;
  79 }
  80
  81 static inline u64 mul_ext_fp(u64 x, u64 y)
  82 {
  83         return (x * y) >> EXT_FRAC_BITS;
  84 }
  85
  86 static inline u64 div_ext_fp(u64 x, u64 y)
  87 {
  88         return div64_u64(x << EXT_FRAC_BITS, y);
  89 }
  90
  91 /**
  92  * struct sample -      Store performance sample
  93  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  94  *                      performance during last sample period
  95  * @busy_scaled:        Scaled busy value which is used to calculate next
  96  *                      P state. This can be different than core_avg_perf
  97  *                      to account for cpu idle period
  98  * @aperf:              Difference of actual performance frequency clock count
  99  *                      read from APERF MSR between last and current sample
 100  * @mperf:              Difference of maximum performance frequency clock count
 101  *                      read from MPERF MSR between last and current sample
 102  * @tsc:                Difference of time stamp counter between last and
 103  *                      current sample
 104  * @time:               Current time from scheduler
 105  *
 106  * This structure is used in the cpudata structure to store performance sample
 107  * data for choosing next P State.
 108  */
 109 struct sample {
 110         int32_t core_avg_perf;
 111         int32_t busy_scaled;
 112         u64 aperf;
 113         u64 mperf;
 114         u64 tsc;
 115         u64 time;
 116 };
 117
 118 /**
 119  * struct pstate_data - Store P state data
 120  * @current_pstate:     Current requested P state
 121  * @min_pstate:         Min P state possible for this platform
 122  * @max_pstate:         Max P state possible for this platform
 123  * @max_pstate_physical:This is physical Max P state for a processor
 124  *                      This can be higher than the max_pstate which can
 125  *                      be limited by platform thermal design power limits
 126  * @perf_ctl_scaling:   PERF_CTL P-state to frequency scaling factor
 127  * @scaling:            Scaling factor between performance and frequency
 128  * @turbo_pstate:       Max Turbo P state possible for this platform
 129  * @min_freq:           @min_pstate frequency in cpufreq units
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     perf_ctl_scaling;
 141         int     scaling;
 142         int     turbo_pstate;
 143         unsigned int min_freq;
 144         unsigned int max_freq;
 145         unsigned int turbo_freq;
 146 };
 147
 148 /**
 149  * struct vid_data -    Stores voltage information data
 150  * @min:                VID data for this platform corresponding to
 151  *                      the lowest P state
 152  * @max:                VID data corresponding to the highest P State.
 153  * @turbo:              VID data for turbo P state
 154  * @ratio:              Ratio of (vid max - vid min) /
 155  *                      (max P state - Min P State)
 156  *
 157  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 158  * This data is used in Atom platforms, where in addition to target P state,
 159  * the voltage data needs to be specified to select next P State.
 160  */
 161 struct vid_data {
 162         int min;
 163         int max;
 164         int turbo;
 165         int32_t ratio;
 166 };
 167
 168 /**
 169  * struct global_params - Global parameters, mostly tunable via sysfs.
 170  * @no_turbo:           Whether or not to use turbo P-states.
 171  * @turbo_disabled:     Whether or not turbo P-states are available at all,
 172  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 173  *                      not the maximum reported turbo P-state is different from
 174  *                      the maximum reported non-turbo one.
 175  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 176  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 177  *                      P-state capacity.
 178  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 179  *                      P-state capacity.
 180  */
 181 struct global_params {
 182         bool no_turbo;
 183         bool turbo_disabled;
 184         bool turbo_disabled_mf;
 185         int max_perf_pct;
 186         int min_perf_pct;
 187 };
 188
 189 /**
 190  * struct cpudata -     Per CPU instance data storage
 191  * @cpu:                CPU number for this instance data
 192  * @policy:             CPUFreq policy value
 193  * @update_util:        CPUFreq utility callback information
 194  * @update_util_set:    CPUFreq utility callback is set
 195  * @iowait_boost:       iowait-related boost fraction
 196  * @last_update:        Time of the last update.
 197  * @pstate:             Stores P state limits for this CPU
 198  * @vid:                Stores VID limits for this CPU
 199  * @last_sample_time:   Last Sample time
 200  * @aperf_mperf_shift:  APERF vs MPERF counting frequency difference
 201  * @prev_aperf:         Last APERF value read from APERF MSR
 202  * @prev_mperf:         Last MPERF value read from MPERF MSR
 203  * @prev_tsc:           Last timestamp counter (TSC) value
 204  * @prev_cummulative_iowait: IO Wait time difference from last and
 205  *                      current sample
 206  * @sample:             Storage for storing last Sample data
 207  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 208  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 209  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 210  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 211  * @epp_powersave:      Last saved HWP energy performance preference
 212  *                      (EPP) or energy performance bias (EPB),
 213  *                      when policy switched to performance
 214  * @epp_policy:         Last saved policy used to set EPP/EPB
 215  * @epp_default:        Power on default HWP energy performance
 216  *                      preference/bias
 217  * @epp_cached          Cached HWP energy-performance preference value
 218  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 219  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 220  * @last_io_update:     Last time when IO wake flag was set
 221  * @sched_flags:        Store scheduler flags for possible cross CPU update
 222  * @hwp_boost_min:      Last HWP boosted min performance
 223  * @suspended:          Whether or not the driver has been suspended.
 224  * @hwp_notify_work:    workqueue for HWP notifications.
 225  *
 226  * This structure stores per CPU instance data for all CPUs.
 227  */
 228 struct cpudata {
 229         int cpu;
 230
 231         unsigned int policy;
 232         struct update_util_data update_util;
 233         bool   update_util_set;
 234
 235         struct pstate_data pstate;
 236         struct vid_data vid;
 237
 238         u64     last_update;
 239         u64     last_sample_time;
 240         u64     aperf_mperf_shift;
 241         u64     prev_aperf;
 242         u64     prev_mperf;
 243         u64     prev_tsc;
 244         u64     prev_cummulative_iowait;
 245         struct sample sample;
 246         int32_t min_perf_ratio;
 247         int32_t max_perf_ratio;
 248 #ifdef CONFIG_ACPI
 249         struct acpi_processor_performance acpi_perf_data;
 250         bool valid_pss_table;
 251 #endif
 252         unsigned int iowait_boost;
 253         s16 epp_powersave;
 254         s16 epp_policy;
 255         s16 epp_default;
 256         s16 epp_cached;
 257         u64 hwp_req_cached;
 258         u64 hwp_cap_cached;
 259         u64 last_io_update;
 260         unsigned int sched_flags;
 261         u32 hwp_boost_min;
 262         bool suspended;
 263         struct delayed_work hwp_notify_work;
 264 };
 265
 266 static struct cpudata **all_cpu_data;
 267
 268 /**
 269  * struct pstate_funcs - Per CPU model specific callbacks
 270  * @get_max:            Callback to get maximum non turbo effective P state
 271  * @get_max_physical:   Callback to get maximum non turbo physical P state
 272  * @get_min:            Callback to get minimum P state
 273  * @get_turbo:          Callback to get turbo P state
 274  * @get_scaling:        Callback to get frequency scaling factor
 275  * @get_cpu_scaling:    Get frequency scaling factor for a given cpu
 276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(int cpu);
 285         int (*get_max_physical)(int cpu);
 286         int (*get_min)(int cpu);
 287         int (*get_turbo)(int cpu);
 288         int (*get_scaling)(void);
 289         int (*get_cpu_scaling)(int cpu);
 290         int (*get_aperf_mperf_shift)(void);
 291         u64 (*get_val)(struct cpudata*, int pstate);
 292         void (*get_vid)(struct cpudata *);
 293 };
 294
 295 static struct pstate_funcs pstate_funcs __read_mostly;
 296
 297 static int hwp_active __read_mostly;
 298 static int hwp_mode_bdw __read_mostly;
 299 static bool per_cpu_limits __read_mostly;
 300 static bool hwp_boost __read_mostly;
 301 static bool hwp_forced __read_mostly;
 302
 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 304
 305 #define HYBRID_SCALING_FACTOR   78741
 306
 307 static inline int core_get_scaling(void)
 308 {
 309         return 100000;
 310 }
 311
 312 #ifdef CONFIG_ACPI
 313 static bool acpi_ppc;
 314 #endif
 315
 316 static struct global_params global;
 317
 318 static DEFINE_MUTEX(intel_pstate_driver_lock);
 319 static DEFINE_MUTEX(intel_pstate_limits_lock);
 320
 321 #ifdef CONFIG_ACPI
 322
 323 static bool intel_pstate_acpi_pm_profile_server(void)
 324 {
 325         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 326             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 327                 return true;
 328
 329         return false;
 330 }
 331
 332 static bool intel_pstate_get_ppc_enable_status(void)
 333 {
 334         if (intel_pstate_acpi_pm_profile_server())
 335                 return true;
 336
 337         return acpi_ppc;
 338 }
 339
 340 #ifdef CONFIG_ACPI_CPPC_LIB
 341
 342 /* The work item is needed to avoid CPU hotplug locking issues */
 343 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 344 {
 345         sched_set_itmt_support();
 346 }
 347
 348 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 349
 350 #define CPPC_MAX_PERF   U8_MAX
 351
 352 static void intel_pstate_set_itmt_prio(int cpu)
 353 {
 354         struct cppc_perf_caps cppc_perf;
 355         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 356         int ret;
 357
 358         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 359         if (ret)
 360                 return;
 361
 362         /*
 363          * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
 364          * In this case we can't use CPPC.highest_perf to enable ITMT.
 365          * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
 366          */
 367         if (cppc_perf.highest_perf == CPPC_MAX_PERF)
 368                 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
 369
 370         /*
 371          * The priorities can be set regardless of whether or not
 372          * sched_set_itmt_support(true) has been called and it is valid to
 373          * update them at any time after it has been called.
 374          */
 375         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 376
 377         if (max_highest_perf <= min_highest_perf) {
 378                 if (cppc_perf.highest_perf > max_highest_perf)
 379                         max_highest_perf = cppc_perf.highest_perf;
 380
 381                 if (cppc_perf.highest_perf < min_highest_perf)
 382                         min_highest_perf = cppc_perf.highest_perf;
 383
 384                 if (max_highest_perf > min_highest_perf) {
 385                         /*
 386                          * This code can be run during CPU online under the
 387                          * CPU hotplug locks, so sched_set_itmt_support()
 388                          * cannot be called from here.  Queue up a work item
 389                          * to invoke it.
 390                          */
 391                         schedule_work(&sched_itmt_work);
 392                 }
 393         }
 394 }
 395
 396 static int intel_pstate_get_cppc_guaranteed(int cpu)
 397 {
 398         struct cppc_perf_caps cppc_perf;
 399         int ret;
 400
 401         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 402         if (ret)
 403                 return ret;
 404
 405         if (cppc_perf.guaranteed_perf)
 406                 return cppc_perf.guaranteed_perf;
 407
 408         return cppc_perf.nominal_perf;
 409 }
 410
 411 static int intel_pstate_cppc_get_scaling(int cpu)
 412 {
 413         struct cppc_perf_caps cppc_perf;
 414         int ret;
 415
 416         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 417
 418         /*
 419          * If the nominal frequency and the nominal performance are not
 420          * zero and the ratio between them is not 100, return the hybrid
 421          * scaling factor.
 422          */
 423         if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
 424             cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
 425                 return HYBRID_SCALING_FACTOR;
 426
 427         return core_get_scaling();
 428 }
 429
 430 #else /* CONFIG_ACPI_CPPC_LIB */
 431 static inline void intel_pstate_set_itmt_prio(int cpu)
 432 {
 433 }
 434 #endif /* CONFIG_ACPI_CPPC_LIB */
 435
 436 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 437 {
 438         struct cpudata *cpu;
 439         int ret;
 440         int i;
 441
 442         if (hwp_active) {
 443                 intel_pstate_set_itmt_prio(policy->cpu);
 444                 return;
 445         }
 446
 447         if (!intel_pstate_get_ppc_enable_status())
 448                 return;
 449
 450         cpu = all_cpu_data[policy->cpu];
 451
 452         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 453                                                   policy->cpu);
 454         if (ret)
 455                 return;
 456
 457         /*
 458          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 459          * guarantee that the states returned by it map to the states in our
 460          * list directly.
 461          */
 462         if (cpu->acpi_perf_data.control_register.space_id !=
 463                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 464                 goto err;
 465
 466         /*
 467          * If there is only one entry _PSS, simply ignore _PSS and continue as
 468          * usual without taking _PSS into account
 469          */
 470         if (cpu->acpi_perf_data.state_count < 2)
 471                 goto err;
 472
 473         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 474         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 475                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 476                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 477                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 478                          (u32) cpu->acpi_perf_data.states[i].power,
 479                          (u32) cpu->acpi_perf_data.states[i].control);
 480         }
 481
 482         cpu->valid_pss_table = true;
 483         pr_debug("_PPC limits will be enforced\n");
 484
 485         return;
 486
 487  err:
 488         cpu->valid_pss_table = false;
 489         acpi_processor_unregister_performance(policy->cpu);
 490 }
 491
 492 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 493 {
 494         struct cpudata *cpu;
 495
 496         cpu = all_cpu_data[policy->cpu];
 497         if (!cpu->valid_pss_table)
 498                 return;
 499
 500         acpi_processor_unregister_performance(policy->cpu);
 501 }
 502 #else /* CONFIG_ACPI */
 503 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 504 {
 505 }
 506
 507 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 508 {
 509 }
 510
 511 static inline bool intel_pstate_acpi_pm_profile_server(void)
 512 {
 513         return false;
 514 }
 515 #endif /* CONFIG_ACPI */
 516
 517 #ifndef CONFIG_ACPI_CPPC_LIB
 518 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
 519 {
 520         return -ENOTSUPP;
 521 }
 522
 523 static int intel_pstate_cppc_get_scaling(int cpu)
 524 {
 525         return core_get_scaling();
 526 }
 527 #endif /* CONFIG_ACPI_CPPC_LIB */
 528
 529 /**
 530  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
 531  * @cpu: Target CPU.
 532  *
 533  * On hybrid processors, HWP may expose more performance levels than there are
 534  * P-states accessible through the PERF_CTL interface.  If that happens, the
 535  * scaling factor between HWP performance levels and CPU frequency will be less
 536  * than the scaling factor between P-state values and CPU frequency.
 537  *
 538  * In that case, adjust the CPU parameters used in computations accordingly.
 539  */
 540 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
 541 {
 542         int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
 543         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 544         int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
 545         int scaling = cpu->pstate.scaling;
 546
 547         pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
 548         pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
 549         pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
 550         pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
 551         pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
 552         pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
 553
 554         cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
 555                                            perf_ctl_scaling);
 556         cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
 557                                          perf_ctl_scaling);
 558
 559         cpu->pstate.max_pstate_physical =
 560                         DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling,
 561                                      scaling);
 562
 563         cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
 564         /*
 565          * Cast the min P-state value retrieved via pstate_funcs.get_min() to
 566          * the effective range of HWP performance levels.
 567          */
 568         cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling);
 569 }
 570
 571 static inline void update_turbo_state(void)
 572 {
 573         u64 misc_en;
 574         struct cpudata *cpu;
 575
 576         cpu = all_cpu_data[0];
 577         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 578         global.turbo_disabled =
 579                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 580                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 581 }
 582
 583 static int min_perf_pct_min(void)
 584 {
 585         struct cpudata *cpu = all_cpu_data[0];
 586         int turbo_pstate = cpu->pstate.turbo_pstate;
 587
 588         return turbo_pstate ?
 589                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 590 }
 591
 592 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 593 {
 594         u64 epb;
 595         int ret;
 596
 597         if (!boot_cpu_has(X86_FEATURE_EPB))
 598                 return -ENXIO;
 599
 600         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 601         if (ret)
 602                 return (s16)ret;
 603
 604         return (s16)(epb & 0x0f);
 605 }
 606
 607 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 608 {
 609         s16 epp;
 610
 611         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 612                 /*
 613                  * When hwp_req_data is 0, means that caller didn't read
 614                  * MSR_HWP_REQUEST, so need to read and get EPP.
 615                  */
 616                 if (!hwp_req_data) {
 617                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 618                                             &hwp_req_data);
 619                         if (epp)
 620                                 return epp;
 621                 }
 622                 epp = (hwp_req_data >> 24) & 0xff;
 623         } else {
 624                 /* When there is no EPP present, HWP uses EPB settings */
 625                 epp = intel_pstate_get_epb(cpu_data);
 626         }
 627
 628         return epp;
 629 }
 630
 631 static int intel_pstate_set_epb(int cpu, s16 pref)
 632 {
 633         u64 epb;
 634         int ret;
 635
 636         if (!boot_cpu_has(X86_FEATURE_EPB))
 637                 return -ENXIO;
 638
 639         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 640         if (ret)
 641                 return ret;
 642
 643         epb = (epb & ~0x0f) | pref;
 644         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * EPP/EPB display strings corresponding to EPP index in the
 651  * energy_perf_strings[]
 652  *      index           String
 653  *-------------------------------------
 654  *      0               default
 655  *      1               performance
 656  *      2               balance_performance
 657  *      3               balance_power
 658  *      4               power
 659  */
 660
 661 enum energy_perf_value_index {
 662         EPP_INDEX_DEFAULT = 0,
 663         EPP_INDEX_PERFORMANCE,
 664         EPP_INDEX_BALANCE_PERFORMANCE,
 665         EPP_INDEX_BALANCE_POWERSAVE,
 666         EPP_INDEX_POWERSAVE,
 667 };
 668
 669 static const char * const energy_perf_strings[] = {
 670         [EPP_INDEX_DEFAULT] = "default",
 671         [EPP_INDEX_PERFORMANCE] = "performance",
 672         [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
 673         [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
 674         [EPP_INDEX_POWERSAVE] = "power",
 675         NULL
 676 };
 677 static unsigned int epp_values[] = {
 678         [EPP_INDEX_DEFAULT] = 0, /* Unused index */
 679         [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
 680         [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
 681         [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
 682         [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
 683 };
 684
 685 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
 686 {
 687         s16 epp;
 688         int index = -EINVAL;
 689
 690         *raw_epp = 0;
 691         epp = intel_pstate_get_epp(cpu_data, 0);
 692         if (epp < 0)
 693                 return epp;
 694
 695         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 696                 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
 697                         return EPP_INDEX_PERFORMANCE;
 698                 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
 699                         return EPP_INDEX_BALANCE_PERFORMANCE;
 700                 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
 701                         return EPP_INDEX_BALANCE_POWERSAVE;
 702                 if (epp == epp_values[EPP_INDEX_POWERSAVE])
 703                         return EPP_INDEX_POWERSAVE;
 704                 *raw_epp = epp;
 705                 return 0;
 706         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 707                 /*
 708                  * Range:
 709                  *      0x00-0x03       :       Performance
 710                  *      0x04-0x07       :       Balance performance
 711                  *      0x08-0x0B       :       Balance power
 712                  *      0x0C-0x0F       :       Power
 713                  * The EPB is a 4 bit value, but our ranges restrict the
 714                  * value which can be set. Here only using top two bits
 715                  * effectively.
 716                  */
 717                 index = (epp >> 2) + 1;
 718         }
 719
 720         return index;
 721 }
 722
 723 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
 724 {
 725         int ret;
 726
 727         /*
 728          * Use the cached HWP Request MSR value, because in the active mode the
 729          * register itself may be updated by intel_pstate_hwp_boost_up() or
 730          * intel_pstate_hwp_boost_down() at any time.
 731          */
 732         u64 value = READ_ONCE(cpu->hwp_req_cached);
 733
 734         value &= ~GENMASK_ULL(31, 24);
 735         value |= (u64)epp << 24;
 736         /*
 737          * The only other updater of hwp_req_cached in the active mode,
 738          * intel_pstate_hwp_set(), is called under the same lock as this
 739          * function, so it cannot run in parallel with the update below.
 740          */
 741         WRITE_ONCE(cpu->hwp_req_cached, value);
 742         ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
 743         if (!ret)
 744                 cpu->epp_cached = epp;
 745
 746         return ret;
 747 }
 748
 749 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 750                                               int pref_index, bool use_raw,
 751                                               u32 raw_epp)
 752 {
 753         int epp = -EINVAL;
 754         int ret;
 755
 756         if (!pref_index)
 757                 epp = cpu_data->epp_default;
 758
 759         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 760                 if (use_raw)
 761                         epp = raw_epp;
 762                 else if (epp == -EINVAL)
 763                         epp = epp_values[pref_index];
 764
 765                 /*
 766                  * To avoid confusion, refuse to set EPP to any values different
 767                  * from 0 (performance) if the current policy is "performance",
 768                  * because those values would be overridden.
 769                  */
 770                 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 771                         return -EBUSY;
 772
 773                 ret = intel_pstate_set_epp(cpu_data, epp);
 774         } else {
 775                 if (epp == -EINVAL)
 776                         epp = (pref_index - 1) << 2;
 777                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 778         }
 779
 780         return ret;
 781 }
 782
 783 static ssize_t show_energy_performance_available_preferences(
 784                                 struct cpufreq_policy *policy, char *buf)
 785 {
 786         int i = 0;
 787         int ret = 0;
 788
 789         while (energy_perf_strings[i] != NULL)
 790                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 791
 792         ret += sprintf(&buf[ret], "\n");
 793
 794         return ret;
 795 }
 796
 797 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 798
 799 static struct cpufreq_driver intel_pstate;
 800
 801 static ssize_t store_energy_performance_preference(
 802                 struct cpufreq_policy *policy, const char *buf, size_t count)
 803 {
 804         struct cpudata *cpu = all_cpu_data[policy->cpu];
 805         char str_preference[21];
 806         bool raw = false;
 807         ssize_t ret;
 808         u32 epp = 0;
 809
 810         ret = sscanf(buf, "%20s", str_preference);
 811         if (ret != 1)
 812                 return -EINVAL;
 813
 814         ret = match_string(energy_perf_strings, -1, str_preference);
 815         if (ret < 0) {
 816                 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
 817                         return ret;
 818
 819                 ret = kstrtouint(buf, 10, &epp);
 820                 if (ret)
 821                         return ret;
 822
 823                 if (epp > 255)
 824                         return -EINVAL;
 825
 826                 raw = true;
 827         }
 828
 829         /*
 830          * This function runs with the policy R/W semaphore held, which
 831          * guarantees that the driver pointer will not change while it is
 832          * running.
 833          */
 834         if (!intel_pstate_driver)
 835                 return -EAGAIN;
 836
 837         mutex_lock(&intel_pstate_limits_lock);
 838
 839         if (intel_pstate_driver == &intel_pstate) {
 840                 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
 841         } else {
 842                 /*
 843                  * In the passive mode the governor needs to be stopped on the
 844                  * target CPU before the EPP update and restarted after it,
 845                  * which is super-heavy-weight, so make sure it is worth doing
 846                  * upfront.
 847                  */
 848                 if (!raw)
 849                         epp = ret ? epp_values[ret] : cpu->epp_default;
 850
 851                 if (cpu->epp_cached != epp) {
 852                         int err;
 853
 854                         cpufreq_stop_governor(policy);
 855                         ret = intel_pstate_set_epp(cpu, epp);
 856                         err = cpufreq_start_governor(policy);
 857                         if (!ret)
 858                                 ret = err;
 859                 } else {
 860                         ret = 0;
 861                 }
 862         }
 863
 864         mutex_unlock(&intel_pstate_limits_lock);
 865
 866         return ret ?: count;
 867 }
 868
 869 static ssize_t show_energy_performance_preference(
 870                                 struct cpufreq_policy *policy, char *buf)
 871 {
 872         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 873         int preference, raw_epp;
 874
 875         preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
 876         if (preference < 0)
 877                 return preference;
 878
 879         if (raw_epp)
 880                 return  sprintf(buf, "%d\n", raw_epp);
 881         else
 882                 return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 883 }
 884
 885 cpufreq_freq_attr_rw(energy_performance_preference);
 886
 887 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 888 {
 889         struct cpudata *cpu = all_cpu_data[policy->cpu];
 890         int ratio, freq;
 891
 892         ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
 893         if (ratio <= 0) {
 894                 u64 cap;
 895
 896                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 897                 ratio = HWP_GUARANTEED_PERF(cap);
 898         }
 899
 900         freq = ratio * cpu->pstate.scaling;
 901         if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
 902                 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
 903
 904         return sprintf(buf, "%d\n", freq);
 905 }
 906
 907 cpufreq_freq_attr_ro(base_frequency);
 908
 909 static struct freq_attr *hwp_cpufreq_attrs[] = {
 910         &energy_performance_preference,
 911         &energy_performance_available_preferences,
 912         &base_frequency,
 913         NULL,
 914 };
 915
 916 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
 917 {
 918         u64 cap;
 919
 920         rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
 921         WRITE_ONCE(cpu->hwp_cap_cached, cap);
 922         cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
 923         cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
 924 }
 925
 926 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
 927 {
 928         int scaling = cpu->pstate.scaling;
 929
 930         __intel_pstate_get_hwp_cap(cpu);
 931
 932         cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
 933         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
 934         if (scaling != cpu->pstate.perf_ctl_scaling) {
 935                 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 936
 937                 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
 938                                                  perf_ctl_scaling);
 939                 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
 940                                                    perf_ctl_scaling);
 941         }
 942 }
 943
 944 static void intel_pstate_hwp_set(unsigned int cpu)
 945 {
 946         struct cpudata *cpu_data = all_cpu_data[cpu];
 947         int max, min;
 948         u64 value;
 949         s16 epp;
 950
 951         max = cpu_data->max_perf_ratio;
 952         min = cpu_data->min_perf_ratio;
 953
 954         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 955                 min = max;
 956
 957         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 958
 959         value &= ~HWP_MIN_PERF(~0L);
 960         value |= HWP_MIN_PERF(min);
 961
 962         value &= ~HWP_MAX_PERF(~0L);
 963         value |= HWP_MAX_PERF(max);
 964
 965         if (cpu_data->epp_policy == cpu_data->policy)
 966                 goto skip_epp;
 967
 968         cpu_data->epp_policy = cpu_data->policy;
 969
 970         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 971                 epp = intel_pstate_get_epp(cpu_data, value);
 972                 cpu_data->epp_powersave = epp;
 973                 /* If EPP read was failed, then don't try to write */
 974                 if (epp < 0)
 975                         goto skip_epp;
 976
 977                 epp = 0;
 978         } else {
 979                 /* skip setting EPP, when saved value is invalid */
 980                 if (cpu_data->epp_powersave < 0)
 981                         goto skip_epp;
 982
 983                 /*
 984                  * No need to restore EPP when it is not zero. This
 985                  * means:
 986                  *  - Policy is not changed
 987                  *  - user has manually changed
 988                  *  - Error reading EPB
 989                  */
 990                 epp = intel_pstate_get_epp(cpu_data, value);
 991                 if (epp)
 992                         goto skip_epp;
 993
 994                 epp = cpu_data->epp_powersave;
 995         }
 996         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 997                 value &= ~GENMASK_ULL(31, 24);
 998                 value |= (u64)epp << 24;
 999         } else {
1000                 intel_pstate_set_epb(cpu, epp);
1001         }
1002 skip_epp:
1003         WRITE_ONCE(cpu_data->hwp_req_cached, value);
1004         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1005 }
1006
1007 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1008
1009 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1010 {
1011         u64 value = READ_ONCE(cpu->hwp_req_cached);
1012         int min_perf;
1013
1014         intel_pstate_disable_hwp_interrupt(cpu);
1015
1016         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1017                 /*
1018                  * In case the EPP has been set to "performance" by the
1019                  * active mode "performance" scaling algorithm, replace that
1020                  * temporary value with the cached EPP one.
1021                  */
1022                 value &= ~GENMASK_ULL(31, 24);
1023                 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1024                 /*
1025                  * However, make sure that EPP will be set to "performance" when
1026                  * the CPU is brought back online again and the "performance"
1027                  * scaling algorithm is still in effect.
1028                  */
1029                 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1030         }
1031
1032         /*
1033          * Clear the desired perf field in the cached HWP request value to
1034          * prevent nonzero desired values from being leaked into the active
1035          * mode.
1036          */
1037         value &= ~HWP_DESIRED_PERF(~0L);
1038         WRITE_ONCE(cpu->hwp_req_cached, value);
1039
1040         value &= ~GENMASK_ULL(31, 0);
1041         min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1042
1043         /* Set hwp_max = hwp_min */
1044         value |= HWP_MAX_PERF(min_perf);
1045         value |= HWP_MIN_PERF(min_perf);
1046
1047         /* Set EPP to min */
1048         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1049                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1050
1051         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1052 }
1053
1054 #define POWER_CTL_EE_ENABLE     1
1055 #define POWER_CTL_EE_DISABLE    2
1056
1057 static int power_ctl_ee_state;
1058
1059 static void set_power_ctl_ee_state(bool input)
1060 {
1061         u64 power_ctl;
1062
1063         mutex_lock(&intel_pstate_driver_lock);
1064         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1065         if (input) {
1066                 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1067                 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1068         } else {
1069                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1070                 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1071         }
1072         wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1073         mutex_unlock(&intel_pstate_driver_lock);
1074 }
1075
1076 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1077
1078 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1079 {
1080         intel_pstate_hwp_enable(cpu);
1081         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1082 }
1083
1084 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1085 {
1086         struct cpudata *cpu = all_cpu_data[policy->cpu];
1087
1088         pr_debug("CPU %d suspending\n", cpu->cpu);
1089
1090         cpu->suspended = true;
1091
1092         /* disable HWP interrupt and cancel any pending work */
1093         intel_pstate_disable_hwp_interrupt(cpu);
1094
1095         return 0;
1096 }
1097
1098 static int intel_pstate_resume(struct cpufreq_policy *policy)
1099 {
1100         struct cpudata *cpu = all_cpu_data[policy->cpu];
1101
1102         pr_debug("CPU %d resuming\n", cpu->cpu);
1103
1104         /* Only restore if the system default is changed */
1105         if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1106                 set_power_ctl_ee_state(true);
1107         else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1108                 set_power_ctl_ee_state(false);
1109
1110         if (cpu->suspended && hwp_active) {
1111                 mutex_lock(&intel_pstate_limits_lock);
1112
1113                 /* Re-enable HWP, because "online" has not done that. */
1114                 intel_pstate_hwp_reenable(cpu);
1115
1116                 mutex_unlock(&intel_pstate_limits_lock);
1117         }
1118
1119         cpu->suspended = false;
1120
1121         return 0;
1122 }
1123
1124 static void intel_pstate_update_policies(void)
1125 {
1126         int cpu;
1127
1128         for_each_possible_cpu(cpu)
1129                 cpufreq_update_policy(cpu);
1130 }
1131
1132 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1133                                            struct cpufreq_policy *policy)
1134 {
1135         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1136                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1137         refresh_frequency_limits(policy);
1138 }
1139
1140 static void intel_pstate_update_max_freq(unsigned int cpu)
1141 {
1142         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1143
1144         if (!policy)
1145                 return;
1146
1147         __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1148
1149         cpufreq_cpu_release(policy);
1150 }
1151
1152 static void intel_pstate_update_limits(unsigned int cpu)
1153 {
1154         mutex_lock(&intel_pstate_driver_lock);
1155
1156         update_turbo_state();
1157         /*
1158          * If turbo has been turned on or off globally, policy limits for
1159          * all CPUs need to be updated to reflect that.
1160          */
1161         if (global.turbo_disabled_mf != global.turbo_disabled) {
1162                 global.turbo_disabled_mf = global.turbo_disabled;
1163                 arch_set_max_freq_ratio(global.turbo_disabled);
1164                 for_each_possible_cpu(cpu)
1165                         intel_pstate_update_max_freq(cpu);
1166         } else {
1167                 cpufreq_update_policy(cpu);
1168         }
1169
1170         mutex_unlock(&intel_pstate_driver_lock);
1171 }
1172
1173 /************************** sysfs begin ************************/
1174 #define show_one(file_name, object)                                     \
1175         static ssize_t show_##file_name                                 \
1176         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
1177         {                                                               \
1178                 return sprintf(buf, "%u\n", global.object);             \
1179         }
1180
1181 static ssize_t intel_pstate_show_status(char *buf);
1182 static int intel_pstate_update_status(const char *buf, size_t size);
1183
1184 static ssize_t show_status(struct kobject *kobj,
1185                            struct kobj_attribute *attr, char *buf)
1186 {
1187         ssize_t ret;
1188
1189         mutex_lock(&intel_pstate_driver_lock);
1190         ret = intel_pstate_show_status(buf);
1191         mutex_unlock(&intel_pstate_driver_lock);
1192
1193         return ret;
1194 }
1195
1196 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1197                             const char *buf, size_t count)
1198 {
1199         char *p = memchr(buf, '\n', count);
1200         int ret;
1201
1202         mutex_lock(&intel_pstate_driver_lock);
1203         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1204         mutex_unlock(&intel_pstate_driver_lock);
1205
1206         return ret < 0 ? ret : count;
1207 }
1208
1209 static ssize_t show_turbo_pct(struct kobject *kobj,
1210                                 struct kobj_attribute *attr, char *buf)
1211 {
1212         struct cpudata *cpu;
1213         int total, no_turbo, turbo_pct;
1214         uint32_t turbo_fp;
1215
1216         mutex_lock(&intel_pstate_driver_lock);
1217
1218         if (!intel_pstate_driver) {
1219                 mutex_unlock(&intel_pstate_driver_lock);
1220                 return -EAGAIN;
1221         }
1222
1223         cpu = all_cpu_data[0];
1224
1225         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1226         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1227         turbo_fp = div_fp(no_turbo, total);
1228         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1229
1230         mutex_unlock(&intel_pstate_driver_lock);
1231
1232         return sprintf(buf, "%u\n", turbo_pct);
1233 }
1234
1235 static ssize_t show_num_pstates(struct kobject *kobj,
1236                                 struct kobj_attribute *attr, char *buf)
1237 {
1238         struct cpudata *cpu;
1239         int total;
1240
1241         mutex_lock(&intel_pstate_driver_lock);
1242
1243         if (!intel_pstate_driver) {
1244                 mutex_unlock(&intel_pstate_driver_lock);
1245                 return -EAGAIN;
1246         }
1247
1248         cpu = all_cpu_data[0];
1249         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1250
1251         mutex_unlock(&intel_pstate_driver_lock);
1252
1253         return sprintf(buf, "%u\n", total);
1254 }
1255
1256 static ssize_t show_no_turbo(struct kobject *kobj,
1257                              struct kobj_attribute *attr, char *buf)
1258 {
1259         ssize_t ret;
1260
1261         mutex_lock(&intel_pstate_driver_lock);
1262
1263         if (!intel_pstate_driver) {
1264                 mutex_unlock(&intel_pstate_driver_lock);
1265                 return -EAGAIN;
1266         }
1267
1268         update_turbo_state();
1269         if (global.turbo_disabled)
1270                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1271         else
1272                 ret = sprintf(buf, "%u\n", global.no_turbo);
1273
1274         mutex_unlock(&intel_pstate_driver_lock);
1275
1276         return ret;
1277 }
1278
1279 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1280                               const char *buf, size_t count)
1281 {
1282         unsigned int input;
1283         int ret;
1284
1285         ret = sscanf(buf, "%u", &input);
1286         if (ret != 1)
1287                 return -EINVAL;
1288
1289         mutex_lock(&intel_pstate_driver_lock);
1290
1291         if (!intel_pstate_driver) {
1292                 mutex_unlock(&intel_pstate_driver_lock);
1293                 return -EAGAIN;
1294         }
1295
1296         mutex_lock(&intel_pstate_limits_lock);
1297
1298         update_turbo_state();
1299         if (global.turbo_disabled) {
1300                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1301                 mutex_unlock(&intel_pstate_limits_lock);
1302                 mutex_unlock(&intel_pstate_driver_lock);
1303                 return -EPERM;
1304         }
1305
1306         global.no_turbo = clamp_t(int, input, 0, 1);
1307
1308         if (global.no_turbo) {
1309                 struct cpudata *cpu = all_cpu_data[0];
1310                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1311
1312                 /* Squash the global minimum into the permitted range. */
1313                 if (global.min_perf_pct > pct)
1314                         global.min_perf_pct = pct;
1315         }
1316
1317         mutex_unlock(&intel_pstate_limits_lock);
1318
1319         intel_pstate_update_policies();
1320         arch_set_max_freq_ratio(global.no_turbo);
1321
1322         mutex_unlock(&intel_pstate_driver_lock);
1323
1324         return count;
1325 }
1326
1327 static void update_qos_request(enum freq_qos_req_type type)
1328 {
1329         struct freq_qos_request *req;
1330         struct cpufreq_policy *policy;
1331         int i;
1332
1333         for_each_possible_cpu(i) {
1334                 struct cpudata *cpu = all_cpu_data[i];
1335                 unsigned int freq, perf_pct;
1336
1337                 policy = cpufreq_cpu_get(i);
1338                 if (!policy)
1339                         continue;
1340
1341                 req = policy->driver_data;
1342                 cpufreq_cpu_put(policy);
1343
1344                 if (!req)
1345                         continue;
1346
1347                 if (hwp_active)
1348                         intel_pstate_get_hwp_cap(cpu);
1349
1350                 if (type == FREQ_QOS_MIN) {
1351                         perf_pct = global.min_perf_pct;
1352                 } else {
1353                         req++;
1354                         perf_pct = global.max_perf_pct;
1355                 }
1356
1357                 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1358
1359                 if (freq_qos_update_request(req, freq) < 0)
1360                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1361         }
1362 }
1363
1364 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1365                                   const char *buf, size_t count)
1366 {
1367         unsigned int input;
1368         int ret;
1369
1370         ret = sscanf(buf, "%u", &input);
1371         if (ret != 1)
1372                 return -EINVAL;
1373
1374         mutex_lock(&intel_pstate_driver_lock);
1375
1376         if (!intel_pstate_driver) {
1377                 mutex_unlock(&intel_pstate_driver_lock);
1378                 return -EAGAIN;
1379         }
1380
1381         mutex_lock(&intel_pstate_limits_lock);
1382
1383         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1384
1385         mutex_unlock(&intel_pstate_limits_lock);
1386
1387         if (intel_pstate_driver == &intel_pstate)
1388                 intel_pstate_update_policies();
1389         else
1390                 update_qos_request(FREQ_QOS_MAX);
1391
1392         mutex_unlock(&intel_pstate_driver_lock);
1393
1394         return count;
1395 }
1396
1397 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1398                                   const char *buf, size_t count)
1399 {
1400         unsigned int input;
1401         int ret;
1402
1403         ret = sscanf(buf, "%u", &input);
1404         if (ret != 1)
1405                 return -EINVAL;
1406
1407         mutex_lock(&intel_pstate_driver_lock);
1408
1409         if (!intel_pstate_driver) {
1410                 mutex_unlock(&intel_pstate_driver_lock);
1411                 return -EAGAIN;
1412         }
1413
1414         mutex_lock(&intel_pstate_limits_lock);
1415
1416         global.min_perf_pct = clamp_t(int, input,
1417                                       min_perf_pct_min(), global.max_perf_pct);
1418
1419         mutex_unlock(&intel_pstate_limits_lock);
1420
1421         if (intel_pstate_driver == &intel_pstate)
1422                 intel_pstate_update_policies();
1423         else
1424                 update_qos_request(FREQ_QOS_MIN);
1425
1426         mutex_unlock(&intel_pstate_driver_lock);
1427
1428         return count;
1429 }
1430
1431 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1432                                 struct kobj_attribute *attr, char *buf)
1433 {
1434         return sprintf(buf, "%u\n", hwp_boost);
1435 }
1436
1437 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1438                                        struct kobj_attribute *b,
1439                                        const char *buf, size_t count)
1440 {
1441         unsigned int input;
1442         int ret;
1443
1444         ret = kstrtouint(buf, 10, &input);
1445         if (ret)
1446                 return ret;
1447
1448         mutex_lock(&intel_pstate_driver_lock);
1449         hwp_boost = !!input;
1450         intel_pstate_update_policies();
1451         mutex_unlock(&intel_pstate_driver_lock);
1452
1453         return count;
1454 }
1455
1456 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1457                                       char *buf)
1458 {
1459         u64 power_ctl;
1460         int enable;
1461
1462         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1463         enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1464         return sprintf(buf, "%d\n", !enable);
1465 }
1466
1467 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1468                                        const char *buf, size_t count)
1469 {
1470         bool input;
1471         int ret;
1472
1473         ret = kstrtobool(buf, &input);
1474         if (ret)
1475                 return ret;
1476
1477         set_power_ctl_ee_state(input);
1478
1479         return count;
1480 }
1481
1482 show_one(max_perf_pct, max_perf_pct);
1483 show_one(min_perf_pct, min_perf_pct);
1484
1485 define_one_global_rw(status);
1486 define_one_global_rw(no_turbo);
1487 define_one_global_rw(max_perf_pct);
1488 define_one_global_rw(min_perf_pct);
1489 define_one_global_ro(turbo_pct);
1490 define_one_global_ro(num_pstates);
1491 define_one_global_rw(hwp_dynamic_boost);
1492 define_one_global_rw(energy_efficiency);
1493
1494 static struct attribute *intel_pstate_attributes[] = {
1495         &status.attr,
1496         &no_turbo.attr,
1497         NULL
1498 };
1499
1500 static const struct attribute_group intel_pstate_attr_group = {
1501         .attrs = intel_pstate_attributes,
1502 };
1503
1504 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1505
1506 static struct kobject *intel_pstate_kobject;
1507
1508 static void __init intel_pstate_sysfs_expose_params(void)
1509 {
1510         struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1511         int rc;
1512
1513         if (dev_root) {
1514                 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1515                 put_device(dev_root);
1516         }
1517         if (WARN_ON(!intel_pstate_kobject))
1518                 return;
1519
1520         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1521         if (WARN_ON(rc))
1522                 return;
1523
1524         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1525                 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1526                 WARN_ON(rc);
1527
1528                 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1529                 WARN_ON(rc);
1530         }
1531
1532         /*
1533          * If per cpu limits are enforced there are no global limits, so
1534          * return without creating max/min_perf_pct attributes
1535          */
1536         if (per_cpu_limits)
1537                 return;
1538
1539         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1540         WARN_ON(rc);
1541
1542         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1543         WARN_ON(rc);
1544
1545         if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1546                 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1547                 WARN_ON(rc);
1548         }
1549 }
1550
1551 static void __init intel_pstate_sysfs_remove(void)
1552 {
1553         if (!intel_pstate_kobject)
1554                 return;
1555
1556         sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1557
1558         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1559                 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1560                 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1561         }
1562
1563         if (!per_cpu_limits) {
1564                 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1565                 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1566
1567                 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1568                         sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1569         }
1570
1571         kobject_put(intel_pstate_kobject);
1572 }
1573
1574 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1575 {
1576         int rc;
1577
1578         if (!hwp_active)
1579                 return;
1580
1581         rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1582         WARN_ON_ONCE(rc);
1583 }
1584
1585 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1586 {
1587         if (!hwp_active)
1588                 return;
1589
1590         sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1591 }
1592
1593 /************************** sysfs end ************************/
1594
1595 static void intel_pstate_notify_work(struct work_struct *work)
1596 {
1597         struct cpudata *cpudata =
1598                 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1599         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1600
1601         if (policy) {
1602                 intel_pstate_get_hwp_cap(cpudata);
1603                 __intel_pstate_update_max_freq(cpudata, policy);
1604
1605                 cpufreq_cpu_release(policy);
1606         }
1607
1608         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1609 }
1610
1611 static DEFINE_SPINLOCK(hwp_notify_lock);
1612 static cpumask_t hwp_intr_enable_mask;
1613
1614 void notify_hwp_interrupt(void)
1615 {
1616         unsigned int this_cpu = smp_processor_id();
1617         struct cpudata *cpudata;
1618         unsigned long flags;
1619         u64 value;
1620
1621         if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1622                 return;
1623
1624         rdmsrl_safe(MSR_HWP_STATUS, &value);
1625         if (!(value & 0x01))
1626                 return;
1627
1628         spin_lock_irqsave(&hwp_notify_lock, flags);
1629
1630         if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1631                 goto ack_intr;
1632
1633         /*
1634          * Currently we never free all_cpu_data. And we can't reach here
1635          * without this allocated. But for safety for future changes, added
1636          * check.
1637          */
1638         if (unlikely(!READ_ONCE(all_cpu_data)))
1639                 goto ack_intr;
1640
1641         /*
1642          * The free is done during cleanup, when cpufreq registry is failed.
1643          * We wouldn't be here if it fails on init or switch status. But for
1644          * future changes, added check.
1645          */
1646         cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1647         if (unlikely(!cpudata))
1648                 goto ack_intr;
1649
1650         schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1651
1652         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1653
1654         return;
1655
1656 ack_intr:
1657         wrmsrl_safe(MSR_HWP_STATUS, 0);
1658         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1659 }
1660
1661 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1662 {
1663         unsigned long flags;
1664
1665         if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1666                 return;
1667
1668         /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1669         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1670
1671         spin_lock_irqsave(&hwp_notify_lock, flags);
1672         if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1673                 cancel_delayed_work(&cpudata->hwp_notify_work);
1674         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1675 }
1676
1677 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1678 {
1679         /* Enable HWP notification interrupt for guaranteed performance change */
1680         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1681                 unsigned long flags;
1682
1683                 spin_lock_irqsave(&hwp_notify_lock, flags);
1684                 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1685                 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1686                 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1687
1688                 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1689                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1690                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1691         }
1692 }
1693
1694 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1695 {
1696         cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1697
1698         /*
1699          * If this CPU gen doesn't call for change in balance_perf
1700          * EPP return.
1701          */
1702         if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1703                 return;
1704
1705         /*
1706          * If the EPP is set by firmware, which means that firmware enabled HWP
1707          * - Is equal or less than 0x80 (default balance_perf EPP)
1708          * - But less performance oriented than performance EPP
1709          *   then use this as new balance_perf EPP.
1710          */
1711         if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1712             cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1713                 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1714                 return;
1715         }
1716
1717         /*
1718          * Use hard coded value per gen to update the balance_perf
1719          * and default EPP.
1720          */
1721         cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1722         intel_pstate_set_epp(cpudata, cpudata->epp_default);
1723 }
1724
1725 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1726 {
1727         /* First disable HWP notification interrupt till we activate again */
1728         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1729                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1730
1731         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1732
1733         intel_pstate_enable_hwp_interrupt(cpudata);
1734
1735         if (cpudata->epp_default >= 0)
1736                 return;
1737
1738         intel_pstate_update_epp_defaults(cpudata);
1739 }
1740
1741 static int atom_get_min_pstate(int not_used)
1742 {
1743         u64 value;
1744
1745         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1746         return (value >> 8) & 0x7F;
1747 }
1748
1749 static int atom_get_max_pstate(int not_used)
1750 {
1751         u64 value;
1752
1753         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1754         return (value >> 16) & 0x7F;
1755 }
1756
1757 static int atom_get_turbo_pstate(int not_used)
1758 {
1759         u64 value;
1760
1761         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1762         return value & 0x7F;
1763 }
1764
1765 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1766 {
1767         u64 val;
1768         int32_t vid_fp;
1769         u32 vid;
1770
1771         val = (u64)pstate << 8;
1772         if (global.no_turbo && !global.turbo_disabled)
1773                 val |= (u64)1 << 32;
1774
1775         vid_fp = cpudata->vid.min + mul_fp(
1776                 int_tofp(pstate - cpudata->pstate.min_pstate),
1777                 cpudata->vid.ratio);
1778
1779         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1780         vid = ceiling_fp(vid_fp);
1781
1782         if (pstate > cpudata->pstate.max_pstate)
1783                 vid = cpudata->vid.turbo;
1784
1785         return val | vid;
1786 }
1787
1788 static int silvermont_get_scaling(void)
1789 {
1790         u64 value;
1791         int i;
1792         /* Defined in Table 35-6 from SDM (Sept 2015) */
1793         static int silvermont_freq_table[] = {
1794                 83300, 100000, 133300, 116700, 80000};
1795
1796         rdmsrl(MSR_FSB_FREQ, value);
1797         i = value & 0x7;
1798         WARN_ON(i > 4);
1799
1800         return silvermont_freq_table[i];
1801 }
1802
1803 static int airmont_get_scaling(void)
1804 {
1805         u64 value;
1806         int i;
1807         /* Defined in Table 35-10 from SDM (Sept 2015) */
1808         static int airmont_freq_table[] = {
1809                 83300, 100000, 133300, 116700, 80000,
1810                 93300, 90000, 88900, 87500};
1811
1812         rdmsrl(MSR_FSB_FREQ, value);
1813         i = value & 0xF;
1814         WARN_ON(i > 8);
1815
1816         return airmont_freq_table[i];
1817 }
1818
1819 static void atom_get_vid(struct cpudata *cpudata)
1820 {
1821         u64 value;
1822
1823         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1824         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1825         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1826         cpudata->vid.ratio = div_fp(
1827                 cpudata->vid.max - cpudata->vid.min,
1828                 int_tofp(cpudata->pstate.max_pstate -
1829                         cpudata->pstate.min_pstate));
1830
1831         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1832         cpudata->vid.turbo = value & 0x7f;
1833 }
1834
1835 static int core_get_min_pstate(int cpu)
1836 {
1837         u64 value;
1838
1839         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1840         return (value >> 40) & 0xFF;
1841 }
1842
1843 static int core_get_max_pstate_physical(int cpu)
1844 {
1845         u64 value;
1846
1847         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1848         return (value >> 8) & 0xFF;
1849 }
1850
1851 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1852 {
1853         /* Check how many TDP levels present */
1854         if (plat_info & 0x600000000) {
1855                 u64 tdp_ctrl;
1856                 u64 tdp_ratio;
1857                 int tdp_msr;
1858                 int err;
1859
1860                 /* Get the TDP level (0, 1, 2) to get ratios */
1861                 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1862                 if (err)
1863                         return err;
1864
1865                 /* TDP MSR are continuous starting at 0x648 */
1866                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1867                 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1868                 if (err)
1869                         return err;
1870
1871                 /* For level 1 and 2, bits[23:16] contain the ratio */
1872                 if (tdp_ctrl & 0x03)
1873                         tdp_ratio >>= 16;
1874
1875                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1876                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1877
1878                 return (int)tdp_ratio;
1879         }
1880
1881         return -ENXIO;
1882 }
1883
1884 static int core_get_max_pstate(int cpu)
1885 {
1886         u64 tar;
1887         u64 plat_info;
1888         int max_pstate;
1889         int tdp_ratio;
1890         int err;
1891
1892         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1893         max_pstate = (plat_info >> 8) & 0xFF;
1894
1895         tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1896         if (tdp_ratio <= 0)
1897                 return max_pstate;
1898
1899         if (hwp_active) {
1900                 /* Turbo activation ratio is not used on HWP platforms */
1901                 return tdp_ratio;
1902         }
1903
1904         err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1905         if (!err) {
1906                 int tar_levels;
1907
1908                 /* Do some sanity checking for safety */
1909                 tar_levels = tar & 0xff;
1910                 if (tdp_ratio - 1 == tar_levels) {
1911                         max_pstate = tar_levels;
1912                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1913                 }
1914         }
1915
1916         return max_pstate;
1917 }
1918
1919 static int core_get_turbo_pstate(int cpu)
1920 {
1921         u64 value;
1922         int nont, ret;
1923
1924         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1925         nont = core_get_max_pstate(cpu);
1926         ret = (value) & 255;
1927         if (ret <= nont)
1928                 ret = nont;
1929         return ret;
1930 }
1931
1932 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1933 {
1934         u64 val;
1935
1936         val = (u64)pstate << 8;
1937         if (global.no_turbo && !global.turbo_disabled)
1938                 val |= (u64)1 << 32;
1939
1940         return val;
1941 }
1942
1943 static int knl_get_aperf_mperf_shift(void)
1944 {
1945         return 10;
1946 }
1947
1948 static int knl_get_turbo_pstate(int cpu)
1949 {
1950         u64 value;
1951         int nont, ret;
1952
1953         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1954         nont = core_get_max_pstate(cpu);
1955         ret = (((value) >> 8) & 0xFF);
1956         if (ret <= nont)
1957                 ret = nont;
1958         return ret;
1959 }
1960
1961 static void hybrid_get_type(void *data)
1962 {
1963         u8 *cpu_type = data;
1964
1965         *cpu_type = get_this_hybrid_cpu_type();
1966 }
1967
1968 static int hwp_get_cpu_scaling(int cpu)
1969 {
1970         u8 cpu_type = 0;
1971
1972         smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1973         /* P-cores have a smaller perf level-to-freqency scaling factor. */
1974         if (cpu_type == 0x40)
1975                 return HYBRID_SCALING_FACTOR;
1976
1977         /* Use default core scaling for E-cores */
1978         if (cpu_type == 0x20)
1979                 return core_get_scaling();
1980
1981         /*
1982          * If reached here, this system is either non-hybrid (like Tiger
1983          * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
1984          * no E cores (in which case CPUID for hybrid support is 0).
1985          *
1986          * The CPPC nominal_frequency field is 0 for non-hybrid systems,
1987          * so the default core scaling will be used for them.
1988          */
1989         return intel_pstate_cppc_get_scaling(cpu);
1990 }
1991
1992 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1993 {
1994         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1995         cpu->pstate.current_pstate = pstate;
1996         /*
1997          * Generally, there is no guarantee that this code will always run on
1998          * the CPU being updated, so force the register update to run on the
1999          * right CPU.
2000          */
2001         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2002                       pstate_funcs.get_val(cpu, pstate));
2003 }
2004
2005 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2006 {
2007         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2008 }
2009
2010 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2011 {
2012         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2013
2014         update_turbo_state();
2015         intel_pstate_set_pstate(cpu, pstate);
2016 }
2017
2018 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2019 {
2020         int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2021         int perf_ctl_scaling = pstate_funcs.get_scaling();
2022
2023         cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2024         cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2025         cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2026
2027         if (hwp_active && !hwp_mode_bdw) {
2028                 __intel_pstate_get_hwp_cap(cpu);
2029
2030                 if (pstate_funcs.get_cpu_scaling) {
2031                         cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2032                         if (cpu->pstate.scaling != perf_ctl_scaling)
2033                                 intel_pstate_hybrid_hwp_adjust(cpu);
2034                 } else {
2035                         cpu->pstate.scaling = perf_ctl_scaling;
2036                 }
2037         } else {
2038                 cpu->pstate.scaling = perf_ctl_scaling;
2039                 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2040                 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2041         }
2042
2043         if (cpu->pstate.scaling == perf_ctl_scaling) {
2044                 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2045                 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2046                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2047         }
2048
2049         if (pstate_funcs.get_aperf_mperf_shift)
2050                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2051
2052         if (pstate_funcs.get_vid)
2053                 pstate_funcs.get_vid(cpu);
2054
2055         intel_pstate_set_min_pstate(cpu);
2056 }
2057
2058 /*
2059  * Long hold time will keep high perf limits for long time,
2060  * which negatively impacts perf/watt for some workloads,
2061  * like specpower. 3ms is based on experiements on some
2062  * workoads.
2063  */
2064 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2065
2066 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2067 {
2068         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2069         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2070         u32 max_limit = (hwp_req & 0xff00) >> 8;
2071         u32 min_limit = (hwp_req & 0xff);
2072         u32 boost_level1;
2073
2074         /*
2075          * Cases to consider (User changes via sysfs or boot time):
2076          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2077          *      No boost, return.
2078          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2079          *     Should result in one level boost only for P0.
2080          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2081          *     Should result in two level boost:
2082          *         (min + p1)/2 and P1.
2083          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2084          *     Should result in three level boost:
2085          *        (min + p1)/2, P1 and P0.
2086          */
2087
2088         /* If max and min are equal or already at max, nothing to boost */
2089         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2090                 return;
2091
2092         if (!cpu->hwp_boost_min)
2093                 cpu->hwp_boost_min = min_limit;
2094
2095         /* level at half way mark between min and guranteed */
2096         boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2097
2098         if (cpu->hwp_boost_min < boost_level1)
2099                 cpu->hwp_boost_min = boost_level1;
2100         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2101                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2102         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2103                  max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2104                 cpu->hwp_boost_min = max_limit;
2105         else
2106                 return;
2107
2108         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2109         wrmsrl(MSR_HWP_REQUEST, hwp_req);
2110         cpu->last_update = cpu->sample.time;
2111 }
2112
2113 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2114 {
2115         if (cpu->hwp_boost_min) {
2116                 bool expired;
2117
2118                 /* Check if we are idle for hold time to boost down */
2119                 expired = time_after64(cpu->sample.time, cpu->last_update +
2120                                        hwp_boost_hold_time_ns);
2121                 if (expired) {
2122                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2123                         cpu->hwp_boost_min = 0;
2124                 }
2125         }
2126         cpu->last_update = cpu->sample.time;
2127 }
2128
2129 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2130                                                       u64 time)
2131 {
2132         cpu->sample.time = time;
2133
2134         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2135                 bool do_io = false;
2136
2137                 cpu->sched_flags = 0;
2138                 /*
2139                  * Set iowait_boost flag and update time. Since IO WAIT flag
2140                  * is set all the time, we can't just conclude that there is
2141                  * some IO bound activity is scheduled on this CPU with just
2142                  * one occurrence. If we receive at least two in two
2143                  * consecutive ticks, then we treat as boost candidate.
2144                  */
2145                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2146                         do_io = true;
2147
2148                 cpu->last_io_update = time;
2149
2150                 if (do_io)
2151                         intel_pstate_hwp_boost_up(cpu);
2152
2153         } else {
2154                 intel_pstate_hwp_boost_down(cpu);
2155         }
2156 }
2157
2158 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2159                                                 u64 time, unsigned int flags)
2160 {
2161         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2162
2163         cpu->sched_flags |= flags;
2164
2165         if (smp_processor_id() == cpu->cpu)
2166                 intel_pstate_update_util_hwp_local(cpu, time);
2167 }
2168
2169 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2170 {
2171         struct sample *sample = &cpu->sample;
2172
2173         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2174 }
2175
2176 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2177 {
2178         u64 aperf, mperf;
2179         unsigned long flags;
2180         u64 tsc;
2181
2182         local_irq_save(flags);
2183         rdmsrl(MSR_IA32_APERF, aperf);
2184         rdmsrl(MSR_IA32_MPERF, mperf);
2185         tsc = rdtsc();
2186         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2187                 local_irq_restore(flags);
2188                 return false;
2189         }
2190         local_irq_restore(flags);
2191
2192         cpu->last_sample_time = cpu->sample.time;
2193         cpu->sample.time = time;
2194         cpu->sample.aperf = aperf;
2195         cpu->sample.mperf = mperf;
2196         cpu->sample.tsc =  tsc;
2197         cpu->sample.aperf -= cpu->prev_aperf;
2198         cpu->sample.mperf -= cpu->prev_mperf;
2199         cpu->sample.tsc -= cpu->prev_tsc;
2200
2201         cpu->prev_aperf = aperf;
2202         cpu->prev_mperf = mperf;
2203         cpu->prev_tsc = tsc;
2204         /*
2205          * First time this function is invoked in a given cycle, all of the
2206          * previous sample data fields are equal to zero or stale and they must
2207          * be populated with meaningful numbers for things to work, so assume
2208          * that sample.time will always be reset before setting the utilization
2209          * update hook and make the caller skip the sample then.
2210          */
2211         if (cpu->last_sample_time) {
2212                 intel_pstate_calc_avg_perf(cpu);
2213                 return true;
2214         }
2215         return false;
2216 }
2217
2218 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2219 {
2220         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2221 }
2222
2223 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2224 {
2225         return mul_ext_fp(cpu->pstate.max_pstate_physical,
2226                           cpu->sample.core_avg_perf);
2227 }
2228
2229 static inline int32_t get_target_pstate(struct cpudata *cpu)
2230 {
2231         struct sample *sample = &cpu->sample;
2232         int32_t busy_frac;
2233         int target, avg_pstate;
2234
2235         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2236                            sample->tsc);
2237
2238         if (busy_frac < cpu->iowait_boost)
2239                 busy_frac = cpu->iowait_boost;
2240
2241         sample->busy_scaled = busy_frac * 100;
2242
2243         target = global.no_turbo || global.turbo_disabled ?
2244                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2245         target += target >> 2;
2246         target = mul_fp(target, busy_frac);
2247         if (target < cpu->pstate.min_pstate)
2248                 target = cpu->pstate.min_pstate;
2249
2250         /*
2251          * If the average P-state during the previous cycle was higher than the
2252          * current target, add 50% of the difference to the target to reduce
2253          * possible performance oscillations and offset possible performance
2254          * loss related to moving the workload from one CPU to another within
2255          * a package/module.
2256          */
2257         avg_pstate = get_avg_pstate(cpu);
2258         if (avg_pstate > target)
2259                 target += (avg_pstate - target) >> 1;
2260
2261         return target;
2262 }
2263
2264 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2265 {
2266         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2267         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2268
2269         return clamp_t(int, pstate, min_pstate, max_pstate);
2270 }
2271
2272 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2273 {
2274         if (pstate == cpu->pstate.current_pstate)
2275                 return;
2276
2277         cpu->pstate.current_pstate = pstate;
2278         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2279 }
2280
2281 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2282 {
2283         int from = cpu->pstate.current_pstate;
2284         struct sample *sample;
2285         int target_pstate;
2286
2287         update_turbo_state();
2288
2289         target_pstate = get_target_pstate(cpu);
2290         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2291         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2292         intel_pstate_update_pstate(cpu, target_pstate);
2293
2294         sample = &cpu->sample;
2295         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2296                 fp_toint(sample->busy_scaled),
2297                 from,
2298                 cpu->pstate.current_pstate,
2299                 sample->mperf,
2300                 sample->aperf,
2301                 sample->tsc,
2302                 get_avg_frequency(cpu),
2303                 fp_toint(cpu->iowait_boost * 100));
2304 }
2305
2306 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2307                                      unsigned int flags)
2308 {
2309         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2310         u64 delta_ns;
2311
2312         /* Don't allow remote callbacks */
2313         if (smp_processor_id() != cpu->cpu)
2314                 return;
2315
2316         delta_ns = time - cpu->last_update;
2317         if (flags & SCHED_CPUFREQ_IOWAIT) {
2318                 /* Start over if the CPU may have been idle. */
2319                 if (delta_ns > TICK_NSEC) {
2320                         cpu->iowait_boost = ONE_EIGHTH_FP;
2321                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2322                         cpu->iowait_boost <<= 1;
2323                         if (cpu->iowait_boost > int_tofp(1))
2324                                 cpu->iowait_boost = int_tofp(1);
2325                 } else {
2326                         cpu->iowait_boost = ONE_EIGHTH_FP;
2327                 }
2328         } else if (cpu->iowait_boost) {
2329                 /* Clear iowait_boost if the CPU may have been idle. */
2330                 if (delta_ns > TICK_NSEC)
2331                         cpu->iowait_boost = 0;
2332                 else
2333                         cpu->iowait_boost >>= 1;
2334         }
2335         cpu->last_update = time;
2336         delta_ns = time - cpu->sample.time;
2337         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2338                 return;
2339
2340         if (intel_pstate_sample(cpu, time))
2341                 intel_pstate_adjust_pstate(cpu);
2342 }
2343
2344 static struct pstate_funcs core_funcs = {
2345         .get_max = core_get_max_pstate,
2346         .get_max_physical = core_get_max_pstate_physical,
2347         .get_min = core_get_min_pstate,
2348         .get_turbo = core_get_turbo_pstate,
2349         .get_scaling = core_get_scaling,
2350         .get_val = core_get_val,
2351 };
2352
2353 static const struct pstate_funcs silvermont_funcs = {
2354         .get_max = atom_get_max_pstate,
2355         .get_max_physical = atom_get_max_pstate,
2356         .get_min = atom_get_min_pstate,
2357         .get_turbo = atom_get_turbo_pstate,
2358         .get_val = atom_get_val,
2359         .get_scaling = silvermont_get_scaling,
2360         .get_vid = atom_get_vid,
2361 };
2362
2363 static const struct pstate_funcs airmont_funcs = {
2364         .get_max = atom_get_max_pstate,
2365         .get_max_physical = atom_get_max_pstate,
2366         .get_min = atom_get_min_pstate,
2367         .get_turbo = atom_get_turbo_pstate,
2368         .get_val = atom_get_val,
2369         .get_scaling = airmont_get_scaling,
2370         .get_vid = atom_get_vid,
2371 };
2372
2373 static const struct pstate_funcs knl_funcs = {
2374         .get_max = core_get_max_pstate,
2375         .get_max_physical = core_get_max_pstate_physical,
2376         .get_min = core_get_min_pstate,
2377         .get_turbo = knl_get_turbo_pstate,
2378         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2379         .get_scaling = core_get_scaling,
2380         .get_val = core_get_val,
2381 };
2382
2383 #define X86_MATCH(model, policy)                                         \
2384         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2385                                            X86_FEATURE_APERFMPERF, &policy)
2386
2387 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2388         X86_MATCH(SANDYBRIDGE,          core_funcs),
2389         X86_MATCH(SANDYBRIDGE_X,        core_funcs),
2390         X86_MATCH(ATOM_SILVERMONT,      silvermont_funcs),
2391         X86_MATCH(IVYBRIDGE,            core_funcs),
2392         X86_MATCH(HASWELL,              core_funcs),
2393         X86_MATCH(BROADWELL,            core_funcs),
2394         X86_MATCH(IVYBRIDGE_X,          core_funcs),
2395         X86_MATCH(HASWELL_X,            core_funcs),
2396         X86_MATCH(HASWELL_L,            core_funcs),
2397         X86_MATCH(HASWELL_G,            core_funcs),
2398         X86_MATCH(BROADWELL_G,          core_funcs),
2399         X86_MATCH(ATOM_AIRMONT,         airmont_funcs),
2400         X86_MATCH(SKYLAKE_L,            core_funcs),
2401         X86_MATCH(BROADWELL_X,          core_funcs),
2402         X86_MATCH(SKYLAKE,              core_funcs),
2403         X86_MATCH(BROADWELL_D,          core_funcs),
2404         X86_MATCH(XEON_PHI_KNL,         knl_funcs),
2405         X86_MATCH(XEON_PHI_KNM,         knl_funcs),
2406         X86_MATCH(ATOM_GOLDMONT,        core_funcs),
2407         X86_MATCH(ATOM_GOLDMONT_PLUS,   core_funcs),
2408         X86_MATCH(SKYLAKE_X,            core_funcs),
2409         X86_MATCH(COMETLAKE,            core_funcs),
2410         X86_MATCH(ICELAKE_X,            core_funcs),
2411         X86_MATCH(TIGERLAKE,            core_funcs),
2412         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2413         {}
2414 };
2415 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2416
2417 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2418         X86_MATCH(BROADWELL_D,          core_funcs),
2419         X86_MATCH(BROADWELL_X,          core_funcs),
2420         X86_MATCH(SKYLAKE_X,            core_funcs),
2421         X86_MATCH(ICELAKE_X,            core_funcs),
2422         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2423         {}
2424 };
2425
2426 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2427         X86_MATCH(KABYLAKE,             core_funcs),
2428         {}
2429 };
2430
2431 static int intel_pstate_init_cpu(unsigned int cpunum)
2432 {
2433         struct cpudata *cpu;
2434
2435         cpu = all_cpu_data[cpunum];
2436
2437         if (!cpu) {
2438                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2439                 if (!cpu)
2440                         return -ENOMEM;
2441
2442                 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2443
2444                 cpu->cpu = cpunum;
2445
2446                 cpu->epp_default = -EINVAL;
2447
2448                 if (hwp_active) {
2449                         intel_pstate_hwp_enable(cpu);
2450
2451                         if (intel_pstate_acpi_pm_profile_server())
2452                                 hwp_boost = true;
2453                 }
2454         } else if (hwp_active) {
2455                 /*
2456                  * Re-enable HWP in case this happens after a resume from ACPI
2457                  * S3 if the CPU was offline during the whole system/resume
2458                  * cycle.
2459                  */
2460                 intel_pstate_hwp_reenable(cpu);
2461         }
2462
2463         cpu->epp_powersave = -EINVAL;
2464         cpu->epp_policy = 0;
2465
2466         intel_pstate_get_cpu_pstates(cpu);
2467
2468         pr_debug("controlling: cpu %d\n", cpunum);
2469
2470         return 0;
2471 }
2472
2473 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2474 {
2475         struct cpudata *cpu = all_cpu_data[cpu_num];
2476
2477         if (hwp_active && !hwp_boost)
2478                 return;
2479
2480         if (cpu->update_util_set)
2481                 return;
2482
2483         /* Prevent intel_pstate_update_util() from using stale data. */
2484         cpu->sample.time = 0;
2485         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2486                                      (hwp_active ?
2487                                       intel_pstate_update_util_hwp :
2488                                       intel_pstate_update_util));
2489         cpu->update_util_set = true;
2490 }
2491
2492 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2493 {
2494         struct cpudata *cpu_data = all_cpu_data[cpu];
2495
2496         if (!cpu_data->update_util_set)
2497                 return;
2498
2499         cpufreq_remove_update_util_hook(cpu);
2500         cpu_data->update_util_set = false;
2501         synchronize_rcu();
2502 }
2503
2504 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2505 {
2506         return global.turbo_disabled || global.no_turbo ?
2507                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2508 }
2509
2510 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2511                                             unsigned int policy_min,
2512                                             unsigned int policy_max)
2513 {
2514         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2515         int32_t max_policy_perf, min_policy_perf;
2516
2517         max_policy_perf = policy_max / perf_ctl_scaling;
2518         if (policy_max == policy_min) {
2519                 min_policy_perf = max_policy_perf;
2520         } else {
2521                 min_policy_perf = policy_min / perf_ctl_scaling;
2522                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2523                                           0, max_policy_perf);
2524         }
2525
2526         /*
2527          * HWP needs some special consideration, because HWP_REQUEST uses
2528          * abstract values to represent performance rather than pure ratios.
2529          */
2530         if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2531                 int scaling = cpu->pstate.scaling;
2532                 int freq;
2533
2534                 freq = max_policy_perf * perf_ctl_scaling;
2535                 max_policy_perf = DIV_ROUND_UP(freq, scaling);
2536                 freq = min_policy_perf * perf_ctl_scaling;
2537                 min_policy_perf = DIV_ROUND_UP(freq, scaling);
2538         }
2539
2540         pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2541                  cpu->cpu, min_policy_perf, max_policy_perf);
2542
2543         /* Normalize user input to [min_perf, max_perf] */
2544         if (per_cpu_limits) {
2545                 cpu->min_perf_ratio = min_policy_perf;
2546                 cpu->max_perf_ratio = max_policy_perf;
2547         } else {
2548                 int turbo_max = cpu->pstate.turbo_pstate;
2549                 int32_t global_min, global_max;
2550
2551                 /* Global limits are in percent of the maximum turbo P-state. */
2552                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2553                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2554                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2555
2556                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2557                          global_min, global_max);
2558
2559                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2560                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2561                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2562                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2563
2564                 /* Make sure min_perf <= max_perf */
2565                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2566                                           cpu->max_perf_ratio);
2567
2568         }
2569         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2570                  cpu->max_perf_ratio,
2571                  cpu->min_perf_ratio);
2572 }
2573
2574 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2575 {
2576         struct cpudata *cpu;
2577
2578         if (!policy->cpuinfo.max_freq)
2579                 return -ENODEV;
2580
2581         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2582                  policy->cpuinfo.max_freq, policy->max);
2583
2584         cpu = all_cpu_data[policy->cpu];
2585         cpu->policy = policy->policy;
2586
2587         mutex_lock(&intel_pstate_limits_lock);
2588
2589         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2590
2591         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2592                 /*
2593                  * NOHZ_FULL CPUs need this as the governor callback may not
2594                  * be invoked on them.
2595                  */
2596                 intel_pstate_clear_update_util_hook(policy->cpu);
2597                 intel_pstate_max_within_limits(cpu);
2598         } else {
2599                 intel_pstate_set_update_util_hook(policy->cpu);
2600         }
2601
2602         if (hwp_active) {
2603                 /*
2604                  * When hwp_boost was active before and dynamically it
2605                  * was turned off, in that case we need to clear the
2606                  * update util hook.
2607                  */
2608                 if (!hwp_boost)
2609                         intel_pstate_clear_update_util_hook(policy->cpu);
2610                 intel_pstate_hwp_set(policy->cpu);
2611         }
2612
2613         mutex_unlock(&intel_pstate_limits_lock);
2614
2615         return 0;
2616 }
2617
2618 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2619                                            struct cpufreq_policy_data *policy)
2620 {
2621         if (!hwp_active &&
2622             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2623             policy->max < policy->cpuinfo.max_freq &&
2624             policy->max > cpu->pstate.max_freq) {
2625                 pr_debug("policy->max > max non turbo frequency\n");
2626                 policy->max = policy->cpuinfo.max_freq;
2627         }
2628 }
2629
2630 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2631                                            struct cpufreq_policy_data *policy)
2632 {
2633         int max_freq;
2634
2635         update_turbo_state();
2636         if (hwp_active) {
2637                 intel_pstate_get_hwp_cap(cpu);
2638                 max_freq = global.no_turbo || global.turbo_disabled ?
2639                                 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2640         } else {
2641                 max_freq = intel_pstate_get_max_freq(cpu);
2642         }
2643         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2644
2645         intel_pstate_adjust_policy_max(cpu, policy);
2646 }
2647
2648 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2649 {
2650         intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2651
2652         return 0;
2653 }
2654
2655 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2656 {
2657         struct cpudata *cpu = all_cpu_data[policy->cpu];
2658
2659         pr_debug("CPU %d going offline\n", cpu->cpu);
2660
2661         if (cpu->suspended)
2662                 return 0;
2663
2664         /*
2665          * If the CPU is an SMT thread and it goes offline with the performance
2666          * settings different from the minimum, it will prevent its sibling
2667          * from getting to lower performance levels, so force the minimum
2668          * performance on CPU offline to prevent that from happening.
2669          */
2670         if (hwp_active)
2671                 intel_pstate_hwp_offline(cpu);
2672         else
2673                 intel_pstate_set_min_pstate(cpu);
2674
2675         intel_pstate_exit_perf_limits(policy);
2676
2677         return 0;
2678 }
2679
2680 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2681 {
2682         struct cpudata *cpu = all_cpu_data[policy->cpu];
2683
2684         pr_debug("CPU %d going online\n", cpu->cpu);
2685
2686         intel_pstate_init_acpi_perf_limits(policy);
2687
2688         if (hwp_active) {
2689                 /*
2690                  * Re-enable HWP and clear the "suspended" flag to let "resume"
2691                  * know that it need not do that.
2692                  */
2693                 intel_pstate_hwp_reenable(cpu);
2694                 cpu->suspended = false;
2695         }
2696
2697         return 0;
2698 }
2699
2700 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2701 {
2702         intel_pstate_clear_update_util_hook(policy->cpu);
2703
2704         return intel_cpufreq_cpu_offline(policy);
2705 }
2706
2707 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2708 {
2709         pr_debug("CPU %d exiting\n", policy->cpu);
2710
2711         policy->fast_switch_possible = false;
2712
2713         return 0;
2714 }
2715
2716 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2717 {
2718         struct cpudata *cpu;
2719         int rc;
2720
2721         rc = intel_pstate_init_cpu(policy->cpu);
2722         if (rc)
2723                 return rc;
2724
2725         cpu = all_cpu_data[policy->cpu];
2726
2727         cpu->max_perf_ratio = 0xFF;
2728         cpu->min_perf_ratio = 0;
2729
2730         /* cpuinfo and default policy values */
2731         policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2732         update_turbo_state();
2733         global.turbo_disabled_mf = global.turbo_disabled;
2734         policy->cpuinfo.max_freq = global.turbo_disabled ?
2735                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2736
2737         policy->min = policy->cpuinfo.min_freq;
2738         policy->max = policy->cpuinfo.max_freq;
2739
2740         intel_pstate_init_acpi_perf_limits(policy);
2741
2742         policy->fast_switch_possible = true;
2743
2744         return 0;
2745 }
2746
2747 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2748 {
2749         int ret = __intel_pstate_cpu_init(policy);
2750
2751         if (ret)
2752                 return ret;
2753
2754         /*
2755          * Set the policy to powersave to provide a valid fallback value in case
2756          * the default cpufreq governor is neither powersave nor performance.
2757          */
2758         policy->policy = CPUFREQ_POLICY_POWERSAVE;
2759
2760         if (hwp_active) {
2761                 struct cpudata *cpu = all_cpu_data[policy->cpu];
2762
2763                 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2764         }
2765
2766         return 0;
2767 }
2768
2769 static struct cpufreq_driver intel_pstate = {
2770         .flags          = CPUFREQ_CONST_LOOPS,
2771         .verify         = intel_pstate_verify_policy,
2772         .setpolicy      = intel_pstate_set_policy,
2773         .suspend        = intel_pstate_suspend,
2774         .resume         = intel_pstate_resume,
2775         .init           = intel_pstate_cpu_init,
2776         .exit           = intel_pstate_cpu_exit,
2777         .offline        = intel_pstate_cpu_offline,
2778         .online         = intel_pstate_cpu_online,
2779         .update_limits  = intel_pstate_update_limits,
2780         .name           = "intel_pstate",
2781 };
2782
2783 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2784 {
2785         struct cpudata *cpu = all_cpu_data[policy->cpu];
2786
2787         intel_pstate_verify_cpu_policy(cpu, policy);
2788         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2789
2790         return 0;
2791 }
2792
2793 /* Use of trace in passive mode:
2794  *
2795  * In passive mode the trace core_busy field (also known as the
2796  * performance field, and lablelled as such on the graphs; also known as
2797  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2798  * driver call was via the normal or fast switch path. Various graphs
2799  * output from the intel_pstate_tracer.py utility that include core_busy
2800  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2801  * so we use 10 to indicate the normal path through the driver, and
2802  * 90 to indicate the fast switch path through the driver.
2803  * The scaled_busy field is not used, and is set to 0.
2804  */
2805
2806 #define INTEL_PSTATE_TRACE_TARGET 10
2807 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2808
2809 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2810 {
2811         struct sample *sample;
2812
2813         if (!trace_pstate_sample_enabled())
2814                 return;
2815
2816         if (!intel_pstate_sample(cpu, ktime_get()))
2817                 return;
2818
2819         sample = &cpu->sample;
2820         trace_pstate_sample(trace_type,
2821                 0,
2822                 old_pstate,
2823                 cpu->pstate.current_pstate,
2824                 sample->mperf,
2825                 sample->aperf,
2826                 sample->tsc,
2827                 get_avg_frequency(cpu),
2828                 fp_toint(cpu->iowait_boost * 100));
2829 }
2830
2831 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2832                                      u32 desired, bool fast_switch)
2833 {
2834         u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2835
2836         value &= ~HWP_MIN_PERF(~0L);
2837         value |= HWP_MIN_PERF(min);
2838
2839         value &= ~HWP_MAX_PERF(~0L);
2840         value |= HWP_MAX_PERF(max);
2841
2842         value &= ~HWP_DESIRED_PERF(~0L);
2843         value |= HWP_DESIRED_PERF(desired);
2844
2845         if (value == prev)
2846                 return;
2847
2848         WRITE_ONCE(cpu->hwp_req_cached, value);
2849         if (fast_switch)
2850                 wrmsrl(MSR_HWP_REQUEST, value);
2851         else
2852                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2853 }
2854
2855 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2856                                           u32 target_pstate, bool fast_switch)
2857 {
2858         if (fast_switch)
2859                 wrmsrl(MSR_IA32_PERF_CTL,
2860                        pstate_funcs.get_val(cpu, target_pstate));
2861         else
2862                 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2863                               pstate_funcs.get_val(cpu, target_pstate));
2864 }
2865
2866 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2867                                        int target_pstate, bool fast_switch)
2868 {
2869         struct cpudata *cpu = all_cpu_data[policy->cpu];
2870         int old_pstate = cpu->pstate.current_pstate;
2871
2872         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2873         if (hwp_active) {
2874                 int max_pstate = policy->strict_target ?
2875                                         target_pstate : cpu->max_perf_ratio;
2876
2877                 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2878                                          fast_switch);
2879         } else if (target_pstate != old_pstate) {
2880                 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2881         }
2882
2883         cpu->pstate.current_pstate = target_pstate;
2884
2885         intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2886                             INTEL_PSTATE_TRACE_TARGET, old_pstate);
2887
2888         return target_pstate;
2889 }
2890
2891 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2892                                 unsigned int target_freq,
2893                                 unsigned int relation)
2894 {
2895         struct cpudata *cpu = all_cpu_data[policy->cpu];
2896         struct cpufreq_freqs freqs;
2897         int target_pstate;
2898
2899         update_turbo_state();
2900
2901         freqs.old = policy->cur;
2902         freqs.new = target_freq;
2903
2904         cpufreq_freq_transition_begin(policy, &freqs);
2905
2906         switch (relation) {
2907         case CPUFREQ_RELATION_L:
2908                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2909                 break;
2910         case CPUFREQ_RELATION_H:
2911                 target_pstate = freqs.new / cpu->pstate.scaling;
2912                 break;
2913         default:
2914                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2915                 break;
2916         }
2917
2918         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2919
2920         freqs.new = target_pstate * cpu->pstate.scaling;
2921
2922         cpufreq_freq_transition_end(policy, &freqs, false);
2923
2924         return 0;
2925 }
2926
2927 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2928                                               unsigned int target_freq)
2929 {
2930         struct cpudata *cpu = all_cpu_data[policy->cpu];
2931         int target_pstate;
2932
2933         update_turbo_state();
2934
2935         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2936
2937         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2938
2939         return target_pstate * cpu->pstate.scaling;
2940 }
2941
2942 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2943                                       unsigned long min_perf,
2944                                       unsigned long target_perf,
2945                                       unsigned long capacity)
2946 {
2947         struct cpudata *cpu = all_cpu_data[cpunum];
2948         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2949         int old_pstate = cpu->pstate.current_pstate;
2950         int cap_pstate, min_pstate, max_pstate, target_pstate;
2951
2952         update_turbo_state();
2953         cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2954                                              HWP_HIGHEST_PERF(hwp_cap);
2955
2956         /* Optimization: Avoid unnecessary divisions. */
2957
2958         target_pstate = cap_pstate;
2959         if (target_perf < capacity)
2960                 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2961
2962         min_pstate = cap_pstate;
2963         if (min_perf < capacity)
2964                 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2965
2966         if (min_pstate < cpu->pstate.min_pstate)
2967                 min_pstate = cpu->pstate.min_pstate;
2968
2969         if (min_pstate < cpu->min_perf_ratio)
2970                 min_pstate = cpu->min_perf_ratio;
2971
2972         max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2973         if (max_pstate < min_pstate)
2974                 max_pstate = min_pstate;
2975
2976         target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2977
2978         intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2979
2980         cpu->pstate.current_pstate = target_pstate;
2981         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2982 }
2983
2984 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2985 {
2986         struct freq_qos_request *req;
2987         struct cpudata *cpu;
2988         struct device *dev;
2989         int ret, freq;
2990
2991         dev = get_cpu_device(policy->cpu);
2992         if (!dev)
2993                 return -ENODEV;
2994
2995         ret = __intel_pstate_cpu_init(policy);
2996         if (ret)
2997                 return ret;
2998
2999         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3000         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3001         policy->cur = policy->cpuinfo.min_freq;
3002
3003         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3004         if (!req) {
3005                 ret = -ENOMEM;
3006                 goto pstate_exit;
3007         }
3008
3009         cpu = all_cpu_data[policy->cpu];
3010
3011         if (hwp_active) {
3012                 u64 value;
3013
3014                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3015
3016                 intel_pstate_get_hwp_cap(cpu);
3017
3018                 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3019                 WRITE_ONCE(cpu->hwp_req_cached, value);
3020
3021                 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3022         } else {
3023                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3024         }
3025
3026         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3027
3028         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3029                                    freq);
3030         if (ret < 0) {
3031                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3032                 goto free_req;
3033         }
3034
3035         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3036
3037         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3038                                    freq);
3039         if (ret < 0) {
3040                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3041                 goto remove_min_req;
3042         }
3043
3044         policy->driver_data = req;
3045
3046         return 0;
3047
3048 remove_min_req:
3049         freq_qos_remove_request(req);
3050 free_req:
3051         kfree(req);
3052 pstate_exit:
3053         intel_pstate_exit_perf_limits(policy);
3054
3055         return ret;
3056 }
3057
3058 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3059 {
3060         struct freq_qos_request *req;
3061
3062         req = policy->driver_data;
3063
3064         freq_qos_remove_request(req + 1);
3065         freq_qos_remove_request(req);
3066         kfree(req);
3067
3068         return intel_pstate_cpu_exit(policy);
3069 }
3070
3071 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3072 {
3073         intel_pstate_suspend(policy);
3074
3075         if (hwp_active) {
3076                 struct cpudata *cpu = all_cpu_data[policy->cpu];
3077                 u64 value = READ_ONCE(cpu->hwp_req_cached);
3078
3079                 /*
3080                  * Clear the desired perf field in MSR_HWP_REQUEST in case
3081                  * intel_cpufreq_adjust_perf() is in use and the last value
3082                  * written by it may not be suitable.
3083                  */
3084                 value &= ~HWP_DESIRED_PERF(~0L);
3085                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3086                 WRITE_ONCE(cpu->hwp_req_cached, value);
3087         }
3088
3089         return 0;
3090 }
3091
3092 static struct cpufreq_driver intel_cpufreq = {
3093         .flags          = CPUFREQ_CONST_LOOPS,
3094         .verify         = intel_cpufreq_verify_policy,
3095         .target         = intel_cpufreq_target,
3096         .fast_switch    = intel_cpufreq_fast_switch,
3097         .init           = intel_cpufreq_cpu_init,
3098         .exit           = intel_cpufreq_cpu_exit,
3099         .offline        = intel_cpufreq_cpu_offline,
3100         .online         = intel_pstate_cpu_online,
3101         .suspend        = intel_cpufreq_suspend,
3102         .resume         = intel_pstate_resume,
3103         .update_limits  = intel_pstate_update_limits,
3104         .name           = "intel_cpufreq",
3105 };
3106
3107 static struct cpufreq_driver *default_driver;
3108
3109 static void intel_pstate_driver_cleanup(void)
3110 {
3111         unsigned int cpu;
3112
3113         cpus_read_lock();
3114         for_each_online_cpu(cpu) {
3115                 if (all_cpu_data[cpu]) {
3116                         if (intel_pstate_driver == &intel_pstate)
3117                                 intel_pstate_clear_update_util_hook(cpu);
3118
3119                         spin_lock(&hwp_notify_lock);
3120                         kfree(all_cpu_data[cpu]);
3121                         WRITE_ONCE(all_cpu_data[cpu], NULL);
3122                         spin_unlock(&hwp_notify_lock);
3123                 }
3124         }
3125         cpus_read_unlock();
3126
3127         intel_pstate_driver = NULL;
3128 }
3129
3130 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3131 {
3132         int ret;
3133
3134         if (driver == &intel_pstate)
3135                 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3136
3137         memset(&global, 0, sizeof(global));
3138         global.max_perf_pct = 100;
3139
3140         intel_pstate_driver = driver;
3141         ret = cpufreq_register_driver(intel_pstate_driver);
3142         if (ret) {
3143                 intel_pstate_driver_cleanup();
3144                 return ret;
3145         }
3146
3147         global.min_perf_pct = min_perf_pct_min();
3148
3149         return 0;
3150 }
3151
3152 static ssize_t intel_pstate_show_status(char *buf)
3153 {
3154         if (!intel_pstate_driver)
3155                 return sprintf(buf, "off\n");
3156
3157         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3158                                         "active" : "passive");
3159 }
3160
3161 static int intel_pstate_update_status(const char *buf, size_t size)
3162 {
3163         if (size == 3 && !strncmp(buf, "off", size)) {
3164                 if (!intel_pstate_driver)
3165                         return -EINVAL;
3166
3167                 if (hwp_active)
3168                         return -EBUSY;
3169
3170                 cpufreq_unregister_driver(intel_pstate_driver);
3171                 intel_pstate_driver_cleanup();
3172                 return 0;
3173         }
3174
3175         if (size == 6 && !strncmp(buf, "active", size)) {
3176                 if (intel_pstate_driver) {
3177                         if (intel_pstate_driver == &intel_pstate)
3178                                 return 0;
3179
3180                         cpufreq_unregister_driver(intel_pstate_driver);
3181                 }
3182
3183                 return intel_pstate_register_driver(&intel_pstate);
3184         }
3185
3186         if (size == 7 && !strncmp(buf, "passive", size)) {
3187                 if (intel_pstate_driver) {
3188                         if (intel_pstate_driver == &intel_cpufreq)
3189                                 return 0;
3190
3191                         cpufreq_unregister_driver(intel_pstate_driver);
3192                         intel_pstate_sysfs_hide_hwp_dynamic_boost();
3193                 }
3194
3195                 return intel_pstate_register_driver(&intel_cpufreq);
3196         }
3197
3198         return -EINVAL;
3199 }
3200
3201 static int no_load __initdata;
3202 static int no_hwp __initdata;
3203 static int hwp_only __initdata;
3204 static unsigned int force_load __initdata;
3205
3206 static int __init intel_pstate_msrs_not_valid(void)
3207 {
3208         if (!pstate_funcs.get_max(0) ||
3209             !pstate_funcs.get_min(0) ||
3210             !pstate_funcs.get_turbo(0))
3211                 return -ENODEV;
3212
3213         return 0;
3214 }
3215
3216 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3217 {
3218         pstate_funcs.get_max   = funcs->get_max;
3219         pstate_funcs.get_max_physical = funcs->get_max_physical;
3220         pstate_funcs.get_min   = funcs->get_min;
3221         pstate_funcs.get_turbo = funcs->get_turbo;
3222         pstate_funcs.get_scaling = funcs->get_scaling;
3223         pstate_funcs.get_val   = funcs->get_val;
3224         pstate_funcs.get_vid   = funcs->get_vid;
3225         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3226 }
3227
3228 #ifdef CONFIG_ACPI
3229
3230 static bool __init intel_pstate_no_acpi_pss(void)
3231 {
3232         int i;
3233
3234         for_each_possible_cpu(i) {
3235                 acpi_status status;
3236                 union acpi_object *pss;
3237                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3238                 struct acpi_processor *pr = per_cpu(processors, i);
3239
3240                 if (!pr)
3241                         continue;
3242
3243                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3244                 if (ACPI_FAILURE(status))
3245                         continue;
3246
3247                 pss = buffer.pointer;
3248                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3249                         kfree(pss);
3250                         return false;
3251                 }
3252
3253                 kfree(pss);
3254         }
3255
3256         pr_debug("ACPI _PSS not found\n");
3257         return true;
3258 }
3259
3260 static bool __init intel_pstate_no_acpi_pcch(void)
3261 {
3262         acpi_status status;
3263         acpi_handle handle;
3264
3265         status = acpi_get_handle(NULL, "\\_SB", &handle);
3266         if (ACPI_FAILURE(status))
3267                 goto not_found;
3268
3269         if (acpi_has_method(handle, "PCCH"))
3270                 return false;
3271
3272 not_found:
3273         pr_debug("ACPI PCCH not found\n");
3274         return true;
3275 }
3276
3277 static bool __init intel_pstate_has_acpi_ppc(void)
3278 {
3279         int i;
3280
3281         for_each_possible_cpu(i) {
3282                 struct acpi_processor *pr = per_cpu(processors, i);
3283
3284                 if (!pr)
3285                         continue;
3286                 if (acpi_has_method(pr->handle, "_PPC"))
3287                         return true;
3288         }
3289         pr_debug("ACPI _PPC not found\n");
3290         return false;
3291 }
3292
3293 enum {
3294         PSS,
3295         PPC,
3296 };
3297
3298 /* Hardware vendor-specific info that has its own power management modes */
3299 static struct acpi_platform_list plat_info[] __initdata = {
3300         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3301         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3302         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3303         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3304         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3305         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3306         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3307         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3308         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3309         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3310         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3311         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3312         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3313         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3314         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3315         { } /* End */
3316 };
3317
3318 #define BITMASK_OOB     (BIT(8) | BIT(18))
3319
3320 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3321 {
3322         const struct x86_cpu_id *id;
3323         u64 misc_pwr;
3324         int idx;
3325
3326         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3327         if (id) {
3328                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3329                 if (misc_pwr & BITMASK_OOB) {
3330                         pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3331                         pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3332                         return true;
3333                 }
3334         }
3335
3336         idx = acpi_match_platform_list(plat_info);
3337         if (idx < 0)
3338                 return false;
3339
3340         switch (plat_info[idx].data) {
3341         case PSS:
3342                 if (!intel_pstate_no_acpi_pss())
3343                         return false;
3344
3345                 return intel_pstate_no_acpi_pcch();
3346         case PPC:
3347                 return intel_pstate_has_acpi_ppc() && !force_load;
3348         }
3349
3350         return false;
3351 }
3352
3353 static void intel_pstate_request_control_from_smm(void)
3354 {
3355         /*
3356          * It may be unsafe to request P-states control from SMM if _PPC support
3357          * has not been enabled.
3358          */
3359         if (acpi_ppc)
3360                 acpi_processor_pstate_control();
3361 }
3362 #else /* CONFIG_ACPI not enabled */
3363 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3364 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3365 static inline void intel_pstate_request_control_from_smm(void) {}
3366 #endif /* CONFIG_ACPI */
3367
3368 #define INTEL_PSTATE_HWP_BROADWELL      0x01
3369
3370 #define X86_MATCH_HWP(model, hwp_mode)                                  \
3371         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3372                                            X86_FEATURE_HWP, hwp_mode)
3373
3374 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3375         X86_MATCH_HWP(BROADWELL_X,      INTEL_PSTATE_HWP_BROADWELL),
3376         X86_MATCH_HWP(BROADWELL_D,      INTEL_PSTATE_HWP_BROADWELL),
3377         X86_MATCH_HWP(ANY,              0),
3378         {}
3379 };
3380
3381 static bool intel_pstate_hwp_is_enabled(void)
3382 {
3383         u64 value;
3384
3385         rdmsrl(MSR_PM_ENABLE, value);
3386         return !!(value & 0x1);
3387 }
3388
3389 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3390         /*
3391          * Set EPP value as 102, this is the max suggested EPP
3392          * which can result in one core turbo frequency for
3393          * AlderLake Mobile CPUs.
3394          */
3395         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3396         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3397         {}
3398 };
3399
3400 static int __init intel_pstate_init(void)
3401 {
3402         static struct cpudata **_all_cpu_data;
3403         const struct x86_cpu_id *id;
3404         int rc;
3405
3406         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3407                 return -ENODEV;
3408
3409         id = x86_match_cpu(hwp_support_ids);
3410         if (id) {
3411                 hwp_forced = intel_pstate_hwp_is_enabled();
3412
3413                 if (hwp_forced)
3414                         pr_info("HWP enabled by BIOS\n");
3415                 else if (no_load)
3416                         return -ENODEV;
3417
3418                 copy_cpu_funcs(&core_funcs);
3419                 /*
3420                  * Avoid enabling HWP for processors without EPP support,
3421                  * because that means incomplete HWP implementation which is a
3422                  * corner case and supporting it is generally problematic.
3423                  *
3424                  * If HWP is enabled already, though, there is no choice but to
3425                  * deal with it.
3426                  */
3427                 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3428                         WRITE_ONCE(hwp_active, 1);
3429                         hwp_mode_bdw = id->driver_data;
3430                         intel_pstate.attr = hwp_cpufreq_attrs;
3431                         intel_cpufreq.attr = hwp_cpufreq_attrs;
3432                         intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3433                         intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3434                         if (!default_driver)
3435                                 default_driver = &intel_pstate;
3436
3437                         pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3438
3439                         goto hwp_cpu_matched;
3440                 }
3441                 pr_info("HWP not enabled\n");
3442         } else {
3443                 if (no_load)
3444                         return -ENODEV;
3445
3446                 id = x86_match_cpu(intel_pstate_cpu_ids);
3447                 if (!id) {
3448                         pr_info("CPU model not supported\n");
3449                         return -ENODEV;
3450                 }
3451
3452                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3453         }
3454
3455         if (intel_pstate_msrs_not_valid()) {
3456                 pr_info("Invalid MSRs\n");
3457                 return -ENODEV;
3458         }
3459         /* Without HWP start in the passive mode. */
3460         if (!default_driver)
3461                 default_driver = &intel_cpufreq;
3462
3463 hwp_cpu_matched:
3464         /*
3465          * The Intel pstate driver will be ignored if the platform
3466          * firmware has its own power management modes.
3467          */
3468         if (intel_pstate_platform_pwr_mgmt_exists()) {
3469                 pr_info("P-states controlled by the platform\n");
3470                 return -ENODEV;
3471         }
3472
3473         if (!hwp_active && hwp_only)
3474                 return -ENOTSUPP;
3475
3476         pr_info("Intel P-state driver initializing\n");
3477
3478         _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3479         if (!_all_cpu_data)
3480                 return -ENOMEM;
3481
3482         WRITE_ONCE(all_cpu_data, _all_cpu_data);
3483
3484         intel_pstate_request_control_from_smm();
3485
3486         intel_pstate_sysfs_expose_params();
3487
3488         if (hwp_active) {
3489                 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3490
3491                 if (id)
3492                         epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3493         }
3494
3495         mutex_lock(&intel_pstate_driver_lock);
3496         rc = intel_pstate_register_driver(default_driver);
3497         mutex_unlock(&intel_pstate_driver_lock);
3498         if (rc) {
3499                 intel_pstate_sysfs_remove();
3500                 return rc;
3501         }
3502
3503         if (hwp_active) {
3504                 const struct x86_cpu_id *id;
3505
3506                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3507                 if (id) {
3508                         set_power_ctl_ee_state(false);
3509                         pr_info("Disabling energy efficiency optimization\n");
3510                 }
3511
3512                 pr_info("HWP enabled\n");
3513         } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3514                 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3515         }
3516
3517         return 0;
3518 }
3519 device_initcall(intel_pstate_init);
3520
3521 static int __init intel_pstate_setup(char *str)
3522 {
3523         if (!str)
3524                 return -EINVAL;
3525
3526         if (!strcmp(str, "disable"))
3527                 no_load = 1;
3528         else if (!strcmp(str, "active"))
3529                 default_driver = &intel_pstate;
3530         else if (!strcmp(str, "passive"))
3531                 default_driver = &intel_cpufreq;
3532
3533         if (!strcmp(str, "no_hwp"))
3534                 no_hwp = 1;
3535
3536         if (!strcmp(str, "force"))
3537                 force_load = 1;
3538         if (!strcmp(str, "hwp_only"))
3539                 hwp_only = 1;
3540         if (!strcmp(str, "per_cpu_perf_limits"))
3541                 per_cpu_limits = true;
3542
3543 #ifdef CONFIG_ACPI
3544         if (!strcmp(str, "support_acpi_ppc"))
3545                 acpi_ppc = true;
3546 #endif
3547
3548         return 0;
3549 }
3550 early_param("intel_pstate", intel_pstate_setup);
3551
3552 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3553 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");