drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/cpufreq.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  41 #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL      (50 * NSEC_PER_MSEC)
  42
  43 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  44 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  45
  46 #ifdef CONFIG_ACPI
  47 #include <acpi/processor.h>
  48 #include <acpi/cppc_acpi.h>
  49 #endif
  50
  51 #define FRAC_BITS 8
  52 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  53 #define fp_toint(X) ((X) >> FRAC_BITS)
  54
  55 #define EXT_BITS 6
  56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  59
  60 static inline int32_t mul_fp(int32_t x, int32_t y)
  61 {
  62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  63 }
  64
  65 static inline int32_t div_fp(s64 x, s64 y)
  66 {
  67         return div64_s64((int64_t)x << FRAC_BITS, y);
  68 }
  69
  70 static inline int ceiling_fp(int32_t x)
  71 {
  72         int mask, ret;
  73
  74         ret = fp_toint(x);
  75         mask = (1 << FRAC_BITS) - 1;
  76         if (x & mask)
  77                 ret += 1;
  78         return ret;
  79 }
  80
  81 static inline int32_t percent_fp(int percent)
  82 {
  83         return div_fp(percent, 100);
  84 }
  85
  86 static inline u64 mul_ext_fp(u64 x, u64 y)
  87 {
  88         return (x * y) >> EXT_FRAC_BITS;
  89 }
  90
  91 static inline u64 div_ext_fp(u64 x, u64 y)
  92 {
  93         return div64_u64(x << EXT_FRAC_BITS, y);
  94 }
  95
  96 static inline int32_t percent_ext_fp(int percent)
  97 {
  98         return div_ext_fp(percent, 100);
  99 }
 100
 101 /**
 102  * struct sample -      Store performance sample
 103  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 104  *                      performance during last sample period
 105  * @busy_scaled:        Scaled busy value which is used to calculate next
 106  *                      P state. This can be different than core_avg_perf
 107  *                      to account for cpu idle period
 108  * @aperf:              Difference of actual performance frequency clock count
 109  *                      read from APERF MSR between last and current sample
 110  * @mperf:              Difference of maximum performance frequency clock count
 111  *                      read from MPERF MSR between last and current sample
 112  * @tsc:                Difference of time stamp counter between last and
 113  *                      current sample
 114  * @time:               Current time from scheduler
 115  *
 116  * This structure is used in the cpudata structure to store performance sample
 117  * data for choosing next P State.
 118  */
 119 struct sample {
 120         int32_t core_avg_perf;
 121         int32_t busy_scaled;
 122         u64 aperf;
 123         u64 mperf;
 124         u64 tsc;
 125         u64 time;
 126 };
 127
 128 /**
 129  * struct pstate_data - Store P state data
 130  * @current_pstate:     Current requested P state
 131  * @min_pstate:         Min P state possible for this platform
 132  * @max_pstate:         Max P state possible for this platform
 133  * @max_pstate_physical:This is physical Max P state for a processor
 134  *                      This can be higher than the max_pstate which can
 135  *                      be limited by platform thermal design power limits
 136  * @scaling:            Scaling factor to  convert frequency to cpufreq
 137  *                      frequency units
 138  * @turbo_pstate:       Max Turbo P state possible for this platform
 139  * @max_freq:           @max_pstate frequency in cpufreq units
 140  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 141  *
 142  * Stores the per cpu model P state limits and current P state.
 143  */
 144 struct pstate_data {
 145         int     current_pstate;
 146         int     min_pstate;
 147         int     max_pstate;
 148         int     max_pstate_physical;
 149         int     scaling;
 150         int     turbo_pstate;
 151         unsigned int max_freq;
 152         unsigned int turbo_freq;
 153 };
 154
 155 /**
 156  * struct vid_data -    Stores voltage information data
 157  * @min:                VID data for this platform corresponding to
 158  *                      the lowest P state
 159  * @max:                VID data corresponding to the highest P State.
 160  * @turbo:              VID data for turbo P state
 161  * @ratio:              Ratio of (vid max - vid min) /
 162  *                      (max P state - Min P State)
 163  *
 164  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 165  * This data is used in Atom platforms, where in addition to target P state,
 166  * the voltage data needs to be specified to select next P State.
 167  */
 168 struct vid_data {
 169         int min;
 170         int max;
 171         int turbo;
 172         int32_t ratio;
 173 };
 174
 175 /**
 176  * struct _pid -        Stores PID data
 177  * @setpoint:           Target set point for busyness or performance
 178  * @integral:           Storage for accumulated error values
 179  * @p_gain:             PID proportional gain
 180  * @i_gain:             PID integral gain
 181  * @d_gain:             PID derivative gain
 182  * @deadband:           PID deadband
 183  * @last_err:           Last error storage for integral part of PID calculation
 184  *
 185  * Stores PID coefficients and last error for PID controller.
 186  */
 187 struct _pid {
 188         int setpoint;
 189         int32_t integral;
 190         int32_t p_gain;
 191         int32_t i_gain;
 192         int32_t d_gain;
 193         int deadband;
 194         int32_t last_err;
 195 };
 196
 197 /**
 198  * struct global_params - Global parameters, mostly tunable via sysfs.
 199  * @no_turbo:           Whether or not to use turbo P-states.
 200  * @turbo_disabled:     Whethet or not turbo P-states are available at all,
 201  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 202  *                      not the maximum reported turbo P-state is different from
 203  *                      the maximum reported non-turbo one.
 204  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 205  *                      P-state capacity.
 206  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 207  *                      P-state capacity.
 208  */
 209 struct global_params {
 210         bool no_turbo;
 211         bool turbo_disabled;
 212         int max_perf_pct;
 213         int min_perf_pct;
 214 };
 215
 216 /**
 217  * struct cpudata -     Per CPU instance data storage
 218  * @cpu:                CPU number for this instance data
 219  * @policy:             CPUFreq policy value
 220  * @update_util:        CPUFreq utility callback information
 221  * @update_util_set:    CPUFreq utility callback is set
 222  * @iowait_boost:       iowait-related boost fraction
 223  * @last_update:        Time of the last update.
 224  * @pstate:             Stores P state limits for this CPU
 225  * @vid:                Stores VID limits for this CPU
 226  * @pid:                Stores PID parameters for this CPU
 227  * @last_sample_time:   Last Sample time
 228  * @prev_aperf:         Last APERF value read from APERF MSR
 229  * @prev_mperf:         Last MPERF value read from MPERF MSR
 230  * @prev_tsc:           Last timestamp counter (TSC) value
 231  * @prev_cummulative_iowait: IO Wait time difference from last and
 232  *                      current sample
 233  * @sample:             Storage for storing last Sample data
 234  * @min_perf:           Minimum capacity limit as a fraction of the maximum
 235  *                      turbo P-state capacity.
 236  * @max_perf:           Maximum capacity limit as a fraction of the maximum
 237  *                      turbo P-state capacity.
 238  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 239  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 240  * @epp_powersave:      Last saved HWP energy performance preference
 241  *                      (EPP) or energy performance bias (EPB),
 242  *                      when policy switched to performance
 243  * @epp_policy:         Last saved policy used to set EPP/EPB
 244  * @epp_default:        Power on default HWP energy performance
 245  *                      preference/bias
 246  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 247  *                      operation
 248  *
 249  * This structure stores per CPU instance data for all CPUs.
 250  */
 251 struct cpudata {
 252         int cpu;
 253
 254         unsigned int policy;
 255         struct update_util_data update_util;
 256         bool   update_util_set;
 257
 258         struct pstate_data pstate;
 259         struct vid_data vid;
 260         struct _pid pid;
 261
 262         u64     last_update;
 263         u64     last_sample_time;
 264         u64     prev_aperf;
 265         u64     prev_mperf;
 266         u64     prev_tsc;
 267         u64     prev_cummulative_iowait;
 268         struct sample sample;
 269         int32_t min_perf;
 270         int32_t max_perf;
 271 #ifdef CONFIG_ACPI
 272         struct acpi_processor_performance acpi_perf_data;
 273         bool valid_pss_table;
 274 #endif
 275         unsigned int iowait_boost;
 276         s16 epp_powersave;
 277         s16 epp_policy;
 278         s16 epp_default;
 279         s16 epp_saved;
 280 };
 281
 282 static struct cpudata **all_cpu_data;
 283
 284 /**
 285  * struct pstate_adjust_policy - Stores static PID configuration data
 286  * @sample_rate_ms:     PID calculation sample rate in ms
 287  * @sample_rate_ns:     Sample rate calculation in ns
 288  * @deadband:           PID deadband
 289  * @setpoint:           PID Setpoint
 290  * @p_gain_pct:         PID proportional gain
 291  * @i_gain_pct:         PID integral gain
 292  * @d_gain_pct:         PID derivative gain
 293  *
 294  * Stores per CPU model static PID configuration data.
 295  */
 296 struct pstate_adjust_policy {
 297         int sample_rate_ms;
 298         s64 sample_rate_ns;
 299         int deadband;
 300         int setpoint;
 301         int p_gain_pct;
 302         int d_gain_pct;
 303         int i_gain_pct;
 304 };
 305
 306 /**
 307  * struct pstate_funcs - Per CPU model specific callbacks
 308  * @get_max:            Callback to get maximum non turbo effective P state
 309  * @get_max_physical:   Callback to get maximum non turbo physical P state
 310  * @get_min:            Callback to get minimum P state
 311  * @get_turbo:          Callback to get turbo P state
 312  * @get_scaling:        Callback to get frequency scaling factor
 313  * @get_val:            Callback to convert P state to actual MSR write value
 314  * @get_vid:            Callback to get VID data for Atom platforms
 315  * @update_util:        Active mode utilization update callback.
 316  *
 317  * Core and Atom CPU models have different way to get P State limits. This
 318  * structure is used to store those callbacks.
 319  */
 320 struct pstate_funcs {
 321         int (*get_max)(void);
 322         int (*get_max_physical)(void);
 323         int (*get_min)(void);
 324         int (*get_turbo)(void);
 325         int (*get_scaling)(void);
 326         u64 (*get_val)(struct cpudata*, int pstate);
 327         void (*get_vid)(struct cpudata *);
 328         void (*update_util)(struct update_util_data *data, u64 time,
 329                             unsigned int flags);
 330 };
 331
 332 static struct pstate_funcs pstate_funcs __read_mostly;
 333 static struct pstate_adjust_policy pid_params __read_mostly = {
 334         .sample_rate_ms = 10,
 335         .sample_rate_ns = 10 * NSEC_PER_MSEC,
 336         .deadband = 0,
 337         .setpoint = 97,
 338         .p_gain_pct = 20,
 339         .d_gain_pct = 0,
 340         .i_gain_pct = 0,
 341 };
 342
 343 static int hwp_active __read_mostly;
 344 static bool per_cpu_limits __read_mostly;
 345
 346 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 347
 348 #ifdef CONFIG_ACPI
 349 static bool acpi_ppc;
 350 #endif
 351
 352 static struct global_params global;
 353
 354 static DEFINE_MUTEX(intel_pstate_driver_lock);
 355 static DEFINE_MUTEX(intel_pstate_limits_lock);
 356
 357 #ifdef CONFIG_ACPI
 358
 359 static bool intel_pstate_get_ppc_enable_status(void)
 360 {
 361         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 362             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 363                 return true;
 364
 365         return acpi_ppc;
 366 }
 367
 368 #ifdef CONFIG_ACPI_CPPC_LIB
 369
 370 /* The work item is needed to avoid CPU hotplug locking issues */
 371 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 372 {
 373         sched_set_itmt_support();
 374 }
 375
 376 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 377
 378 static void intel_pstate_set_itmt_prio(int cpu)
 379 {
 380         struct cppc_perf_caps cppc_perf;
 381         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 382         int ret;
 383
 384         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 385         if (ret)
 386                 return;
 387
 388         /*
 389          * The priorities can be set regardless of whether or not
 390          * sched_set_itmt_support(true) has been called and it is valid to
 391          * update them at any time after it has been called.
 392          */
 393         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 394
 395         if (max_highest_perf <= min_highest_perf) {
 396                 if (cppc_perf.highest_perf > max_highest_perf)
 397                         max_highest_perf = cppc_perf.highest_perf;
 398
 399                 if (cppc_perf.highest_perf < min_highest_perf)
 400                         min_highest_perf = cppc_perf.highest_perf;
 401
 402                 if (max_highest_perf > min_highest_perf) {
 403                         /*
 404                          * This code can be run during CPU online under the
 405                          * CPU hotplug locks, so sched_set_itmt_support()
 406                          * cannot be called from here.  Queue up a work item
 407                          * to invoke it.
 408                          */
 409                         schedule_work(&sched_itmt_work);
 410                 }
 411         }
 412 }
 413 #else
 414 static void intel_pstate_set_itmt_prio(int cpu)
 415 {
 416 }
 417 #endif
 418
 419 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 420 {
 421         struct cpudata *cpu;
 422         int ret;
 423         int i;
 424
 425         if (hwp_active) {
 426                 intel_pstate_set_itmt_prio(policy->cpu);
 427                 return;
 428         }
 429
 430         if (!intel_pstate_get_ppc_enable_status())
 431                 return;
 432
 433         cpu = all_cpu_data[policy->cpu];
 434
 435         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 436                                                   policy->cpu);
 437         if (ret)
 438                 return;
 439
 440         /*
 441          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 442          * guarantee that the states returned by it map to the states in our
 443          * list directly.
 444          */
 445         if (cpu->acpi_perf_data.control_register.space_id !=
 446                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 447                 goto err;
 448
 449         /*
 450          * If there is only one entry _PSS, simply ignore _PSS and continue as
 451          * usual without taking _PSS into account
 452          */
 453         if (cpu->acpi_perf_data.state_count < 2)
 454                 goto err;
 455
 456         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 457         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 458                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 459                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 460                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 461                          (u32) cpu->acpi_perf_data.states[i].power,
 462                          (u32) cpu->acpi_perf_data.states[i].control);
 463         }
 464
 465         /*
 466          * The _PSS table doesn't contain whole turbo frequency range.
 467          * This just contains +1 MHZ above the max non turbo frequency,
 468          * with control value corresponding to max turbo ratio. But
 469          * when cpufreq set policy is called, it will call with this
 470          * max frequency, which will cause a reduced performance as
 471          * this driver uses real max turbo frequency as the max
 472          * frequency. So correct this frequency in _PSS table to
 473          * correct max turbo frequency based on the turbo state.
 474          * Also need to convert to MHz as _PSS freq is in MHz.
 475          */
 476         if (!global.turbo_disabled)
 477                 cpu->acpi_perf_data.states[0].core_frequency =
 478                                         policy->cpuinfo.max_freq / 1000;
 479         cpu->valid_pss_table = true;
 480         pr_debug("_PPC limits will be enforced\n");
 481
 482         return;
 483
 484  err:
 485         cpu->valid_pss_table = false;
 486         acpi_processor_unregister_performance(policy->cpu);
 487 }
 488
 489 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 490 {
 491         struct cpudata *cpu;
 492
 493         cpu = all_cpu_data[policy->cpu];
 494         if (!cpu->valid_pss_table)
 495                 return;
 496
 497         acpi_processor_unregister_performance(policy->cpu);
 498 }
 499 #else
 500 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 501 {
 502 }
 503
 504 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 505 {
 506 }
 507 #endif
 508
 509 static signed int pid_calc(struct _pid *pid, int32_t busy)
 510 {
 511         signed int result;
 512         int32_t pterm, dterm, fp_error;
 513         int32_t integral_limit;
 514
 515         fp_error = pid->setpoint - busy;
 516
 517         if (abs(fp_error) <= pid->deadband)
 518                 return 0;
 519
 520         pterm = mul_fp(pid->p_gain, fp_error);
 521
 522         pid->integral += fp_error;
 523
 524         /*
 525          * We limit the integral here so that it will never
 526          * get higher than 30.  This prevents it from becoming
 527          * too large an input over long periods of time and allows
 528          * it to get factored out sooner.
 529          *
 530          * The value of 30 was chosen through experimentation.
 531          */
 532         integral_limit = int_tofp(30);
 533         if (pid->integral > integral_limit)
 534                 pid->integral = integral_limit;
 535         if (pid->integral < -integral_limit)
 536                 pid->integral = -integral_limit;
 537
 538         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 539         pid->last_err = fp_error;
 540
 541         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 542         result = result + (1 << (FRAC_BITS-1));
 543         return (signed int)fp_toint(result);
 544 }
 545
 546 static inline void intel_pstate_pid_reset(struct cpudata *cpu)
 547 {
 548         struct _pid *pid = &cpu->pid;
 549
 550         pid->p_gain = percent_fp(pid_params.p_gain_pct);
 551         pid->d_gain = percent_fp(pid_params.d_gain_pct);
 552         pid->i_gain = percent_fp(pid_params.i_gain_pct);
 553         pid->setpoint = int_tofp(pid_params.setpoint);
 554         pid->last_err  = pid->setpoint - int_tofp(100);
 555         pid->deadband  = int_tofp(pid_params.deadband);
 556         pid->integral  = 0;
 557 }
 558
 559 static inline void update_turbo_state(void)
 560 {
 561         u64 misc_en;
 562         struct cpudata *cpu;
 563
 564         cpu = all_cpu_data[0];
 565         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 566         global.turbo_disabled =
 567                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 568                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 569 }
 570
 571 static int min_perf_pct_min(void)
 572 {
 573         struct cpudata *cpu = all_cpu_data[0];
 574
 575         return DIV_ROUND_UP(cpu->pstate.min_pstate * 100,
 576                             cpu->pstate.turbo_pstate);
 577 }
 578
 579 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 580 {
 581         u64 epb;
 582         int ret;
 583
 584         if (!static_cpu_has(X86_FEATURE_EPB))
 585                 return -ENXIO;
 586
 587         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 588         if (ret)
 589                 return (s16)ret;
 590
 591         return (s16)(epb & 0x0f);
 592 }
 593
 594 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 595 {
 596         s16 epp;
 597
 598         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 599                 /*
 600                  * When hwp_req_data is 0, means that caller didn't read
 601                  * MSR_HWP_REQUEST, so need to read and get EPP.
 602                  */
 603                 if (!hwp_req_data) {
 604                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 605                                             &hwp_req_data);
 606                         if (epp)
 607                                 return epp;
 608                 }
 609                 epp = (hwp_req_data >> 24) & 0xff;
 610         } else {
 611                 /* When there is no EPP present, HWP uses EPB settings */
 612                 epp = intel_pstate_get_epb(cpu_data);
 613         }
 614
 615         return epp;
 616 }
 617
 618 static int intel_pstate_set_epb(int cpu, s16 pref)
 619 {
 620         u64 epb;
 621         int ret;
 622
 623         if (!static_cpu_has(X86_FEATURE_EPB))
 624                 return -ENXIO;
 625
 626         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 627         if (ret)
 628                 return ret;
 629
 630         epb = (epb & ~0x0f) | pref;
 631         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 632
 633         return 0;
 634 }
 635
 636 /*
 637  * EPP/EPB display strings corresponding to EPP index in the
 638  * energy_perf_strings[]
 639  *      index           String
 640  *-------------------------------------
 641  *      0               default
 642  *      1               performance
 643  *      2               balance_performance
 644  *      3               balance_power
 645  *      4               power
 646  */
 647 static const char * const energy_perf_strings[] = {
 648         "default",
 649         "performance",
 650         "balance_performance",
 651         "balance_power",
 652         "power",
 653         NULL
 654 };
 655 static const unsigned int epp_values[] = {
 656         HWP_EPP_PERFORMANCE,
 657         HWP_EPP_BALANCE_PERFORMANCE,
 658         HWP_EPP_BALANCE_POWERSAVE,
 659         HWP_EPP_POWERSAVE
 660 };
 661
 662 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 663 {
 664         s16 epp;
 665         int index = -EINVAL;
 666
 667         epp = intel_pstate_get_epp(cpu_data, 0);
 668         if (epp < 0)
 669                 return epp;
 670
 671         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 672                 if (epp == HWP_EPP_PERFORMANCE)
 673                         return 1;
 674                 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
 675                         return 2;
 676                 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
 677                         return 3;
 678                 else
 679                         return 4;
 680         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 681                 /*
 682                  * Range:
 683                  *      0x00-0x03       :       Performance
 684                  *      0x04-0x07       :       Balance performance
 685                  *      0x08-0x0B       :       Balance power
 686                  *      0x0C-0x0F       :       Power
 687                  * The EPB is a 4 bit value, but our ranges restrict the
 688                  * value which can be set. Here only using top two bits
 689                  * effectively.
 690                  */
 691                 index = (epp >> 2) + 1;
 692         }
 693
 694         return index;
 695 }
 696
 697 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 698                                               int pref_index)
 699 {
 700         int epp = -EINVAL;
 701         int ret;
 702
 703         if (!pref_index)
 704                 epp = cpu_data->epp_default;
 705
 706         mutex_lock(&intel_pstate_limits_lock);
 707
 708         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 709                 u64 value;
 710
 711                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 712                 if (ret)
 713                         goto return_pref;
 714
 715                 value &= ~GENMASK_ULL(31, 24);
 716
 717                 if (epp == -EINVAL)
 718                         epp = epp_values[pref_index - 1];
 719
 720                 value |= (u64)epp << 24;
 721                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 722         } else {
 723                 if (epp == -EINVAL)
 724                         epp = (pref_index - 1) << 2;
 725                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 726         }
 727 return_pref:
 728         mutex_unlock(&intel_pstate_limits_lock);
 729
 730         return ret;
 731 }
 732
 733 static ssize_t show_energy_performance_available_preferences(
 734                                 struct cpufreq_policy *policy, char *buf)
 735 {
 736         int i = 0;
 737         int ret = 0;
 738
 739         while (energy_perf_strings[i] != NULL)
 740                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 741
 742         ret += sprintf(&buf[ret], "\n");
 743
 744         return ret;
 745 }
 746
 747 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 748
 749 static ssize_t store_energy_performance_preference(
 750                 struct cpufreq_policy *policy, const char *buf, size_t count)
 751 {
 752         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 753         char str_preference[21];
 754         int ret, i = 0;
 755
 756         ret = sscanf(buf, "%20s", str_preference);
 757         if (ret != 1)
 758                 return -EINVAL;
 759
 760         while (energy_perf_strings[i] != NULL) {
 761                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 762                         intel_pstate_set_energy_pref_index(cpu_data, i);
 763                         return count;
 764                 }
 765                 ++i;
 766         }
 767
 768         return -EINVAL;
 769 }
 770
 771 static ssize_t show_energy_performance_preference(
 772                                 struct cpufreq_policy *policy, char *buf)
 773 {
 774         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 775         int preference;
 776
 777         preference = intel_pstate_get_energy_pref_index(cpu_data);
 778         if (preference < 0)
 779                 return preference;
 780
 781         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 782 }
 783
 784 cpufreq_freq_attr_rw(energy_performance_preference);
 785
 786 static struct freq_attr *hwp_cpufreq_attrs[] = {
 787         &energy_performance_preference,
 788         &energy_performance_available_preferences,
 789         NULL,
 790 };
 791
 792 static void intel_pstate_hwp_set(unsigned int cpu)
 793 {
 794         struct cpudata *cpu_data = all_cpu_data[cpu];
 795         int min, hw_min, max, hw_max;
 796         u64 value, cap;
 797         s16 epp;
 798
 799         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 800         hw_min = HWP_LOWEST_PERF(cap);
 801         if (global.no_turbo)
 802                 hw_max = HWP_GUARANTEED_PERF(cap);
 803         else
 804                 hw_max = HWP_HIGHEST_PERF(cap);
 805
 806         max = fp_ext_toint(hw_max * cpu_data->max_perf);
 807         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 808                 min = max;
 809         else
 810                 min = fp_ext_toint(hw_max * cpu_data->min_perf);
 811
 812         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 813
 814         value &= ~HWP_MIN_PERF(~0L);
 815         value |= HWP_MIN_PERF(min);
 816
 817         value &= ~HWP_MAX_PERF(~0L);
 818         value |= HWP_MAX_PERF(max);
 819
 820         if (cpu_data->epp_policy == cpu_data->policy)
 821                 goto skip_epp;
 822
 823         cpu_data->epp_policy = cpu_data->policy;
 824
 825         if (cpu_data->epp_saved >= 0) {
 826                 epp = cpu_data->epp_saved;
 827                 cpu_data->epp_saved = -EINVAL;
 828                 goto update_epp;
 829         }
 830
 831         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 832                 epp = intel_pstate_get_epp(cpu_data, value);
 833                 cpu_data->epp_powersave = epp;
 834                 /* If EPP read was failed, then don't try to write */
 835                 if (epp < 0)
 836                         goto skip_epp;
 837
 838                 epp = 0;
 839         } else {
 840                 /* skip setting EPP, when saved value is invalid */
 841                 if (cpu_data->epp_powersave < 0)
 842                         goto skip_epp;
 843
 844                 /*
 845                  * No need to restore EPP when it is not zero. This
 846                  * means:
 847                  *  - Policy is not changed
 848                  *  - user has manually changed
 849                  *  - Error reading EPB
 850                  */
 851                 epp = intel_pstate_get_epp(cpu_data, value);
 852                 if (epp)
 853                         goto skip_epp;
 854
 855                 epp = cpu_data->epp_powersave;
 856         }
 857 update_epp:
 858         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 859                 value &= ~GENMASK_ULL(31, 24);
 860                 value |= (u64)epp << 24;
 861         } else {
 862                 intel_pstate_set_epb(cpu, epp);
 863         }
 864 skip_epp:
 865         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 866 }
 867
 868 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 869 {
 870         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 871
 872         if (!hwp_active)
 873                 return 0;
 874
 875         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 876
 877         return 0;
 878 }
 879
 880 static int intel_pstate_resume(struct cpufreq_policy *policy)
 881 {
 882         if (!hwp_active)
 883                 return 0;
 884
 885         mutex_lock(&intel_pstate_limits_lock);
 886
 887         all_cpu_data[policy->cpu]->epp_policy = 0;
 888         intel_pstate_hwp_set(policy->cpu);
 889
 890         mutex_unlock(&intel_pstate_limits_lock);
 891
 892         return 0;
 893 }
 894
 895 static void intel_pstate_update_policies(void)
 896 {
 897         int cpu;
 898
 899         for_each_possible_cpu(cpu)
 900                 cpufreq_update_policy(cpu);
 901 }
 902
 903 /************************** debugfs begin ************************/
 904 static int pid_param_set(void *data, u64 val)
 905 {
 906         unsigned int cpu;
 907
 908         *(u32 *)data = val;
 909         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
 910         for_each_possible_cpu(cpu)
 911                 if (all_cpu_data[cpu])
 912                         intel_pstate_pid_reset(all_cpu_data[cpu]);
 913
 914         return 0;
 915 }
 916
 917 static int pid_param_get(void *data, u64 *val)
 918 {
 919         *val = *(u32 *)data;
 920         return 0;
 921 }
 922 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 923
 924 static struct dentry *debugfs_parent;
 925
 926 struct pid_param {
 927         char *name;
 928         void *value;
 929         struct dentry *dentry;
 930 };
 931
 932 static struct pid_param pid_files[] = {
 933         {"sample_rate_ms", &pid_params.sample_rate_ms, },
 934         {"d_gain_pct", &pid_params.d_gain_pct, },
 935         {"i_gain_pct", &pid_params.i_gain_pct, },
 936         {"deadband", &pid_params.deadband, },
 937         {"setpoint", &pid_params.setpoint, },
 938         {"p_gain_pct", &pid_params.p_gain_pct, },
 939         {NULL, NULL, }
 940 };
 941
 942 static void intel_pstate_debug_expose_params(void)
 943 {
 944         int i;
 945
 946         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 947         if (IS_ERR_OR_NULL(debugfs_parent))
 948                 return;
 949
 950         for (i = 0; pid_files[i].name; i++) {
 951                 struct dentry *dentry;
 952
 953                 dentry = debugfs_create_file(pid_files[i].name, 0660,
 954                                              debugfs_parent, pid_files[i].value,
 955                                              &fops_pid_param);
 956                 if (!IS_ERR(dentry))
 957                         pid_files[i].dentry = dentry;
 958         }
 959 }
 960
 961 static void intel_pstate_debug_hide_params(void)
 962 {
 963         int i;
 964
 965         if (IS_ERR_OR_NULL(debugfs_parent))
 966                 return;
 967
 968         for (i = 0; pid_files[i].name; i++) {
 969                 debugfs_remove(pid_files[i].dentry);
 970                 pid_files[i].dentry = NULL;
 971         }
 972
 973         debugfs_remove(debugfs_parent);
 974         debugfs_parent = NULL;
 975 }
 976
 977 /************************** debugfs end ************************/
 978
 979 /************************** sysfs begin ************************/
 980 #define show_one(file_name, object)                                     \
 981         static ssize_t show_##file_name                                 \
 982         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 983         {                                                               \
 984                 return sprintf(buf, "%u\n", global.object);             \
 985         }
 986
 987 static ssize_t intel_pstate_show_status(char *buf);
 988 static int intel_pstate_update_status(const char *buf, size_t size);
 989
 990 static ssize_t show_status(struct kobject *kobj,
 991                            struct attribute *attr, char *buf)
 992 {
 993         ssize_t ret;
 994
 995         mutex_lock(&intel_pstate_driver_lock);
 996         ret = intel_pstate_show_status(buf);
 997         mutex_unlock(&intel_pstate_driver_lock);
 998
 999         return ret;
1000 }
1001
1002 static ssize_t store_status(struct kobject *a, struct attribute *b,
1003                             const char *buf, size_t count)
1004 {
1005         char *p = memchr(buf, '\n', count);
1006         int ret;
1007
1008         mutex_lock(&intel_pstate_driver_lock);
1009         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1010         mutex_unlock(&intel_pstate_driver_lock);
1011
1012         return ret < 0 ? ret : count;
1013 }
1014
1015 static ssize_t show_turbo_pct(struct kobject *kobj,
1016                                 struct attribute *attr, char *buf)
1017 {
1018         struct cpudata *cpu;
1019         int total, no_turbo, turbo_pct;
1020         uint32_t turbo_fp;
1021
1022         mutex_lock(&intel_pstate_driver_lock);
1023
1024         if (!intel_pstate_driver) {
1025                 mutex_unlock(&intel_pstate_driver_lock);
1026                 return -EAGAIN;
1027         }
1028
1029         cpu = all_cpu_data[0];
1030
1031         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1032         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1033         turbo_fp = div_fp(no_turbo, total);
1034         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1035
1036         mutex_unlock(&intel_pstate_driver_lock);
1037
1038         return sprintf(buf, "%u\n", turbo_pct);
1039 }
1040
1041 static ssize_t show_num_pstates(struct kobject *kobj,
1042                                 struct attribute *attr, char *buf)
1043 {
1044         struct cpudata *cpu;
1045         int total;
1046
1047         mutex_lock(&intel_pstate_driver_lock);
1048
1049         if (!intel_pstate_driver) {
1050                 mutex_unlock(&intel_pstate_driver_lock);
1051                 return -EAGAIN;
1052         }
1053
1054         cpu = all_cpu_data[0];
1055         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1056
1057         mutex_unlock(&intel_pstate_driver_lock);
1058
1059         return sprintf(buf, "%u\n", total);
1060 }
1061
1062 static ssize_t show_no_turbo(struct kobject *kobj,
1063                              struct attribute *attr, char *buf)
1064 {
1065         ssize_t ret;
1066
1067         mutex_lock(&intel_pstate_driver_lock);
1068
1069         if (!intel_pstate_driver) {
1070                 mutex_unlock(&intel_pstate_driver_lock);
1071                 return -EAGAIN;
1072         }
1073
1074         update_turbo_state();
1075         if (global.turbo_disabled)
1076                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1077         else
1078                 ret = sprintf(buf, "%u\n", global.no_turbo);
1079
1080         mutex_unlock(&intel_pstate_driver_lock);
1081
1082         return ret;
1083 }
1084
1085 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1086                               const char *buf, size_t count)
1087 {
1088         unsigned int input;
1089         int ret;
1090
1091         ret = sscanf(buf, "%u", &input);
1092         if (ret != 1)
1093                 return -EINVAL;
1094
1095         mutex_lock(&intel_pstate_driver_lock);
1096
1097         if (!intel_pstate_driver) {
1098                 mutex_unlock(&intel_pstate_driver_lock);
1099                 return -EAGAIN;
1100         }
1101
1102         mutex_lock(&intel_pstate_limits_lock);
1103
1104         update_turbo_state();
1105         if (global.turbo_disabled) {
1106                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1107                 mutex_unlock(&intel_pstate_limits_lock);
1108                 mutex_unlock(&intel_pstate_driver_lock);
1109                 return -EPERM;
1110         }
1111
1112         global.no_turbo = clamp_t(int, input, 0, 1);
1113
1114         if (global.no_turbo) {
1115                 struct cpudata *cpu = all_cpu_data[0];
1116                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1117
1118                 /* Squash the global minimum into the permitted range. */
1119                 if (global.min_perf_pct > pct)
1120                         global.min_perf_pct = pct;
1121         }
1122
1123         mutex_unlock(&intel_pstate_limits_lock);
1124
1125         intel_pstate_update_policies();
1126
1127         mutex_unlock(&intel_pstate_driver_lock);
1128
1129         return count;
1130 }
1131
1132 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1133                                   const char *buf, size_t count)
1134 {
1135         unsigned int input;
1136         int ret;
1137
1138         ret = sscanf(buf, "%u", &input);
1139         if (ret != 1)
1140                 return -EINVAL;
1141
1142         mutex_lock(&intel_pstate_driver_lock);
1143
1144         if (!intel_pstate_driver) {
1145                 mutex_unlock(&intel_pstate_driver_lock);
1146                 return -EAGAIN;
1147         }
1148
1149         mutex_lock(&intel_pstate_limits_lock);
1150
1151         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1152
1153         mutex_unlock(&intel_pstate_limits_lock);
1154
1155         intel_pstate_update_policies();
1156
1157         mutex_unlock(&intel_pstate_driver_lock);
1158
1159         return count;
1160 }
1161
1162 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1163                                   const char *buf, size_t count)
1164 {
1165         unsigned int input;
1166         int ret;
1167
1168         ret = sscanf(buf, "%u", &input);
1169         if (ret != 1)
1170                 return -EINVAL;
1171
1172         mutex_lock(&intel_pstate_driver_lock);
1173
1174         if (!intel_pstate_driver) {
1175                 mutex_unlock(&intel_pstate_driver_lock);
1176                 return -EAGAIN;
1177         }
1178
1179         mutex_lock(&intel_pstate_limits_lock);
1180
1181         global.min_perf_pct = clamp_t(int, input,
1182                                       min_perf_pct_min(), global.max_perf_pct);
1183
1184         mutex_unlock(&intel_pstate_limits_lock);
1185
1186         intel_pstate_update_policies();
1187
1188         mutex_unlock(&intel_pstate_driver_lock);
1189
1190         return count;
1191 }
1192
1193 show_one(max_perf_pct, max_perf_pct);
1194 show_one(min_perf_pct, min_perf_pct);
1195
1196 define_one_global_rw(status);
1197 define_one_global_rw(no_turbo);
1198 define_one_global_rw(max_perf_pct);
1199 define_one_global_rw(min_perf_pct);
1200 define_one_global_ro(turbo_pct);
1201 define_one_global_ro(num_pstates);
1202
1203 static struct attribute *intel_pstate_attributes[] = {
1204         &status.attr,
1205         &no_turbo.attr,
1206         &turbo_pct.attr,
1207         &num_pstates.attr,
1208         NULL
1209 };
1210
1211 static struct attribute_group intel_pstate_attr_group = {
1212         .attrs = intel_pstate_attributes,
1213 };
1214
1215 static void __init intel_pstate_sysfs_expose_params(void)
1216 {
1217         struct kobject *intel_pstate_kobject;
1218         int rc;
1219
1220         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1221                                                 &cpu_subsys.dev_root->kobj);
1222         if (WARN_ON(!intel_pstate_kobject))
1223                 return;
1224
1225         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1226         if (WARN_ON(rc))
1227                 return;
1228
1229         /*
1230          * If per cpu limits are enforced there are no global limits, so
1231          * return without creating max/min_perf_pct attributes
1232          */
1233         if (per_cpu_limits)
1234                 return;
1235
1236         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1237         WARN_ON(rc);
1238
1239         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1240         WARN_ON(rc);
1241
1242 }
1243 /************************** sysfs end ************************/
1244
1245 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1246 {
1247         /* First disable HWP notification interrupt as we don't process them */
1248         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1249                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1250
1251         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1252         cpudata->epp_policy = 0;
1253         if (cpudata->epp_default == -EINVAL)
1254                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1255 }
1256
1257 #define MSR_IA32_POWER_CTL_BIT_EE       19
1258
1259 /* Disable energy efficiency optimization */
1260 static void intel_pstate_disable_ee(int cpu)
1261 {
1262         u64 power_ctl;
1263         int ret;
1264
1265         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1266         if (ret)
1267                 return;
1268
1269         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1270                 pr_info("Disabling energy efficiency optimization\n");
1271                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1272                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1273         }
1274 }
1275
1276 static int atom_get_min_pstate(void)
1277 {
1278         u64 value;
1279
1280         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1281         return (value >> 8) & 0x7F;
1282 }
1283
1284 static int atom_get_max_pstate(void)
1285 {
1286         u64 value;
1287
1288         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1289         return (value >> 16) & 0x7F;
1290 }
1291
1292 static int atom_get_turbo_pstate(void)
1293 {
1294         u64 value;
1295
1296         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1297         return value & 0x7F;
1298 }
1299
1300 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1301 {
1302         u64 val;
1303         int32_t vid_fp;
1304         u32 vid;
1305
1306         val = (u64)pstate << 8;
1307         if (global.no_turbo && !global.turbo_disabled)
1308                 val |= (u64)1 << 32;
1309
1310         vid_fp = cpudata->vid.min + mul_fp(
1311                 int_tofp(pstate - cpudata->pstate.min_pstate),
1312                 cpudata->vid.ratio);
1313
1314         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1315         vid = ceiling_fp(vid_fp);
1316
1317         if (pstate > cpudata->pstate.max_pstate)
1318                 vid = cpudata->vid.turbo;
1319
1320         return val | vid;
1321 }
1322
1323 static int silvermont_get_scaling(void)
1324 {
1325         u64 value;
1326         int i;
1327         /* Defined in Table 35-6 from SDM (Sept 2015) */
1328         static int silvermont_freq_table[] = {
1329                 83300, 100000, 133300, 116700, 80000};
1330
1331         rdmsrl(MSR_FSB_FREQ, value);
1332         i = value & 0x7;
1333         WARN_ON(i > 4);
1334
1335         return silvermont_freq_table[i];
1336 }
1337
1338 static int airmont_get_scaling(void)
1339 {
1340         u64 value;
1341         int i;
1342         /* Defined in Table 35-10 from SDM (Sept 2015) */
1343         static int airmont_freq_table[] = {
1344                 83300, 100000, 133300, 116700, 80000,
1345                 93300, 90000, 88900, 87500};
1346
1347         rdmsrl(MSR_FSB_FREQ, value);
1348         i = value & 0xF;
1349         WARN_ON(i > 8);
1350
1351         return airmont_freq_table[i];
1352 }
1353
1354 static void atom_get_vid(struct cpudata *cpudata)
1355 {
1356         u64 value;
1357
1358         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1359         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1360         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1361         cpudata->vid.ratio = div_fp(
1362                 cpudata->vid.max - cpudata->vid.min,
1363                 int_tofp(cpudata->pstate.max_pstate -
1364                         cpudata->pstate.min_pstate));
1365
1366         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1367         cpudata->vid.turbo = value & 0x7f;
1368 }
1369
1370 static int core_get_min_pstate(void)
1371 {
1372         u64 value;
1373
1374         rdmsrl(MSR_PLATFORM_INFO, value);
1375         return (value >> 40) & 0xFF;
1376 }
1377
1378 static int core_get_max_pstate_physical(void)
1379 {
1380         u64 value;
1381
1382         rdmsrl(MSR_PLATFORM_INFO, value);
1383         return (value >> 8) & 0xFF;
1384 }
1385
1386 static int core_get_tdp_ratio(u64 plat_info)
1387 {
1388         /* Check how many TDP levels present */
1389         if (plat_info & 0x600000000) {
1390                 u64 tdp_ctrl;
1391                 u64 tdp_ratio;
1392                 int tdp_msr;
1393                 int err;
1394
1395                 /* Get the TDP level (0, 1, 2) to get ratios */
1396                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1397                 if (err)
1398                         return err;
1399
1400                 /* TDP MSR are continuous starting at 0x648 */
1401                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1402                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1403                 if (err)
1404                         return err;
1405
1406                 /* For level 1 and 2, bits[23:16] contain the ratio */
1407                 if (tdp_ctrl & 0x03)
1408                         tdp_ratio >>= 16;
1409
1410                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1411                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1412
1413                 return (int)tdp_ratio;
1414         }
1415
1416         return -ENXIO;
1417 }
1418
1419 static int core_get_max_pstate(void)
1420 {
1421         u64 tar;
1422         u64 plat_info;
1423         int max_pstate;
1424         int tdp_ratio;
1425         int err;
1426
1427         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1428         max_pstate = (plat_info >> 8) & 0xFF;
1429
1430         tdp_ratio = core_get_tdp_ratio(plat_info);
1431         if (tdp_ratio <= 0)
1432                 return max_pstate;
1433
1434         if (hwp_active) {
1435                 /* Turbo activation ratio is not used on HWP platforms */
1436                 return tdp_ratio;
1437         }
1438
1439         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1440         if (!err) {
1441                 int tar_levels;
1442
1443                 /* Do some sanity checking for safety */
1444                 tar_levels = tar & 0xff;
1445                 if (tdp_ratio - 1 == tar_levels) {
1446                         max_pstate = tar_levels;
1447                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1448                 }
1449         }
1450
1451         return max_pstate;
1452 }
1453
1454 static int core_get_turbo_pstate(void)
1455 {
1456         u64 value;
1457         int nont, ret;
1458
1459         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1460         nont = core_get_max_pstate();
1461         ret = (value) & 255;
1462         if (ret <= nont)
1463                 ret = nont;
1464         return ret;
1465 }
1466
1467 static inline int core_get_scaling(void)
1468 {
1469         return 100000;
1470 }
1471
1472 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1473 {
1474         u64 val;
1475
1476         val = (u64)pstate << 8;
1477         if (global.no_turbo && !global.turbo_disabled)
1478                 val |= (u64)1 << 32;
1479
1480         return val;
1481 }
1482
1483 static int knl_get_turbo_pstate(void)
1484 {
1485         u64 value;
1486         int nont, ret;
1487
1488         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1489         nont = core_get_max_pstate();
1490         ret = (((value) >> 8) & 0xFF);
1491         if (ret <= nont)
1492                 ret = nont;
1493         return ret;
1494 }
1495
1496 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1497 {
1498         return global.no_turbo || global.turbo_disabled ?
1499                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1500 }
1501
1502 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1503 {
1504         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1505         cpu->pstate.current_pstate = pstate;
1506         /*
1507          * Generally, there is no guarantee that this code will always run on
1508          * the CPU being updated, so force the register update to run on the
1509          * right CPU.
1510          */
1511         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1512                       pstate_funcs.get_val(cpu, pstate));
1513 }
1514
1515 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1516 {
1517         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1518 }
1519
1520 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1521 {
1522         int pstate;
1523
1524         update_turbo_state();
1525         pstate = intel_pstate_get_base_pstate(cpu);
1526         pstate = max(cpu->pstate.min_pstate,
1527                      fp_ext_toint(pstate * cpu->max_perf));
1528         intel_pstate_set_pstate(cpu, pstate);
1529 }
1530
1531 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1532 {
1533         cpu->pstate.min_pstate = pstate_funcs.get_min();
1534         cpu->pstate.max_pstate = pstate_funcs.get_max();
1535         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1536         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1537         cpu->pstate.scaling = pstate_funcs.get_scaling();
1538         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1539         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1540
1541         if (pstate_funcs.get_vid)
1542                 pstate_funcs.get_vid(cpu);
1543
1544         intel_pstate_set_min_pstate(cpu);
1545 }
1546
1547 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1548 {
1549         struct sample *sample = &cpu->sample;
1550
1551         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1552 }
1553
1554 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1555 {
1556         u64 aperf, mperf;
1557         unsigned long flags;
1558         u64 tsc;
1559
1560         local_irq_save(flags);
1561         rdmsrl(MSR_IA32_APERF, aperf);
1562         rdmsrl(MSR_IA32_MPERF, mperf);
1563         tsc = rdtsc();
1564         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1565                 local_irq_restore(flags);
1566                 return false;
1567         }
1568         local_irq_restore(flags);
1569
1570         cpu->last_sample_time = cpu->sample.time;
1571         cpu->sample.time = time;
1572         cpu->sample.aperf = aperf;
1573         cpu->sample.mperf = mperf;
1574         cpu->sample.tsc =  tsc;
1575         cpu->sample.aperf -= cpu->prev_aperf;
1576         cpu->sample.mperf -= cpu->prev_mperf;
1577         cpu->sample.tsc -= cpu->prev_tsc;
1578
1579         cpu->prev_aperf = aperf;
1580         cpu->prev_mperf = mperf;
1581         cpu->prev_tsc = tsc;
1582         /*
1583          * First time this function is invoked in a given cycle, all of the
1584          * previous sample data fields are equal to zero or stale and they must
1585          * be populated with meaningful numbers for things to work, so assume
1586          * that sample.time will always be reset before setting the utilization
1587          * update hook and make the caller skip the sample then.
1588          */
1589         if (cpu->last_sample_time) {
1590                 intel_pstate_calc_avg_perf(cpu);
1591                 return true;
1592         }
1593         return false;
1594 }
1595
1596 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1597 {
1598         return mul_ext_fp(cpu->sample.core_avg_perf,
1599                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1600 }
1601
1602 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1603 {
1604         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1605                           cpu->sample.core_avg_perf);
1606 }
1607
1608 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1609 {
1610         struct sample *sample = &cpu->sample;
1611         int32_t busy_frac, boost;
1612         int target, avg_pstate;
1613
1614         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1615                 return cpu->pstate.turbo_pstate;
1616
1617         busy_frac = div_fp(sample->mperf, sample->tsc);
1618
1619         boost = cpu->iowait_boost;
1620         cpu->iowait_boost >>= 1;
1621
1622         if (busy_frac < boost)
1623                 busy_frac = boost;
1624
1625         sample->busy_scaled = busy_frac * 100;
1626
1627         target = global.no_turbo || global.turbo_disabled ?
1628                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1629         target += target >> 2;
1630         target = mul_fp(target, busy_frac);
1631         if (target < cpu->pstate.min_pstate)
1632                 target = cpu->pstate.min_pstate;
1633
1634         /*
1635          * If the average P-state during the previous cycle was higher than the
1636          * current target, add 50% of the difference to the target to reduce
1637          * possible performance oscillations and offset possible performance
1638          * loss related to moving the workload from one CPU to another within
1639          * a package/module.
1640          */
1641         avg_pstate = get_avg_pstate(cpu);
1642         if (avg_pstate > target)
1643                 target += (avg_pstate - target) >> 1;
1644
1645         return target;
1646 }
1647
1648 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1649 {
1650         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1651         u64 duration_ns;
1652
1653         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE)
1654                 return cpu->pstate.turbo_pstate;
1655
1656         /*
1657          * perf_scaled is the ratio of the average P-state during the last
1658          * sampling period to the P-state requested last time (in percent).
1659          *
1660          * That measures the system's response to the previous P-state
1661          * selection.
1662          */
1663         max_pstate = cpu->pstate.max_pstate_physical;
1664         current_pstate = cpu->pstate.current_pstate;
1665         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1666                                div_fp(100 * max_pstate, current_pstate));
1667
1668         /*
1669          * Since our utilization update callback will not run unless we are
1670          * in C0, check if the actual elapsed time is significantly greater (3x)
1671          * than our sample interval.  If it is, then we were idle for a long
1672          * enough period of time to adjust our performance metric.
1673          */
1674         duration_ns = cpu->sample.time - cpu->last_sample_time;
1675         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1676                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1677                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1678         } else {
1679                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1680                 if (sample_ratio < int_tofp(1))
1681                         perf_scaled = 0;
1682         }
1683
1684         cpu->sample.busy_scaled = perf_scaled;
1685         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1686 }
1687
1688 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1689 {
1690         int max_pstate = intel_pstate_get_base_pstate(cpu);
1691         int min_pstate;
1692
1693         min_pstate = max(cpu->pstate.min_pstate,
1694                          fp_ext_toint(max_pstate * cpu->min_perf));
1695         max_pstate = max(min_pstate, fp_ext_toint(max_pstate * cpu->max_perf));
1696         return clamp_t(int, pstate, min_pstate, max_pstate);
1697 }
1698
1699 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1700 {
1701         if (pstate == cpu->pstate.current_pstate)
1702                 return;
1703
1704         cpu->pstate.current_pstate = pstate;
1705         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1706 }
1707
1708 static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
1709 {
1710         int from = cpu->pstate.current_pstate;
1711         struct sample *sample;
1712
1713         update_turbo_state();
1714
1715         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1716         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1717         intel_pstate_update_pstate(cpu, target_pstate);
1718
1719         sample = &cpu->sample;
1720         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1721                 fp_toint(sample->busy_scaled),
1722                 from,
1723                 cpu->pstate.current_pstate,
1724                 sample->mperf,
1725                 sample->aperf,
1726                 sample->tsc,
1727                 get_avg_frequency(cpu),
1728                 fp_toint(cpu->iowait_boost * 100));
1729 }
1730
1731 static void intel_pstate_update_util_hwp(struct update_util_data *data,
1732                                          u64 time, unsigned int flags)
1733 {
1734         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1735         u64 delta_ns = time - cpu->sample.time;
1736
1737         if ((s64)delta_ns >= INTEL_PSTATE_HWP_SAMPLING_INTERVAL)
1738                 intel_pstate_sample(cpu, time);
1739 }
1740
1741 static void intel_pstate_update_util_pid(struct update_util_data *data,
1742                                          u64 time, unsigned int flags)
1743 {
1744         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1745         u64 delta_ns = time - cpu->sample.time;
1746
1747         if ((s64)delta_ns < pid_params.sample_rate_ns)
1748                 return;
1749
1750         if (intel_pstate_sample(cpu, time)) {
1751                 int target_pstate;
1752
1753                 target_pstate = get_target_pstate_use_performance(cpu);
1754                 intel_pstate_adjust_pstate(cpu, target_pstate);
1755         }
1756 }
1757
1758 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1759                                      unsigned int flags)
1760 {
1761         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1762         u64 delta_ns;
1763
1764         if (flags & SCHED_CPUFREQ_IOWAIT) {
1765                 cpu->iowait_boost = int_tofp(1);
1766         } else if (cpu->iowait_boost) {
1767                 /* Clear iowait_boost if the CPU may have been idle. */
1768                 delta_ns = time - cpu->last_update;
1769                 if (delta_ns > TICK_NSEC)
1770                         cpu->iowait_boost = 0;
1771         }
1772         cpu->last_update = time;
1773         delta_ns = time - cpu->sample.time;
1774         if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1775                 return;
1776
1777         if (intel_pstate_sample(cpu, time)) {
1778                 int target_pstate;
1779
1780                 target_pstate = get_target_pstate_use_cpu_load(cpu);
1781                 intel_pstate_adjust_pstate(cpu, target_pstate);
1782         }
1783 }
1784
1785 static struct pstate_funcs core_funcs = {
1786         .get_max = core_get_max_pstate,
1787         .get_max_physical = core_get_max_pstate_physical,
1788         .get_min = core_get_min_pstate,
1789         .get_turbo = core_get_turbo_pstate,
1790         .get_scaling = core_get_scaling,
1791         .get_val = core_get_val,
1792         .update_util = intel_pstate_update_util_pid,
1793 };
1794
1795 static const struct pstate_funcs silvermont_funcs = {
1796         .get_max = atom_get_max_pstate,
1797         .get_max_physical = atom_get_max_pstate,
1798         .get_min = atom_get_min_pstate,
1799         .get_turbo = atom_get_turbo_pstate,
1800         .get_val = atom_get_val,
1801         .get_scaling = silvermont_get_scaling,
1802         .get_vid = atom_get_vid,
1803         .update_util = intel_pstate_update_util,
1804 };
1805
1806 static const struct pstate_funcs airmont_funcs = {
1807         .get_max = atom_get_max_pstate,
1808         .get_max_physical = atom_get_max_pstate,
1809         .get_min = atom_get_min_pstate,
1810         .get_turbo = atom_get_turbo_pstate,
1811         .get_val = atom_get_val,
1812         .get_scaling = airmont_get_scaling,
1813         .get_vid = atom_get_vid,
1814         .update_util = intel_pstate_update_util,
1815 };
1816
1817 static const struct pstate_funcs knl_funcs = {
1818         .get_max = core_get_max_pstate,
1819         .get_max_physical = core_get_max_pstate_physical,
1820         .get_min = core_get_min_pstate,
1821         .get_turbo = knl_get_turbo_pstate,
1822         .get_scaling = core_get_scaling,
1823         .get_val = core_get_val,
1824         .update_util = intel_pstate_update_util_pid,
1825 };
1826
1827 static const struct pstate_funcs bxt_funcs = {
1828         .get_max = core_get_max_pstate,
1829         .get_max_physical = core_get_max_pstate_physical,
1830         .get_min = core_get_min_pstate,
1831         .get_turbo = core_get_turbo_pstate,
1832         .get_scaling = core_get_scaling,
1833         .get_val = core_get_val,
1834         .update_util = intel_pstate_update_util,
1835 };
1836
1837 #define ICPU(model, policy) \
1838         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1839                         (unsigned long)&policy }
1840
1841 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1842         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_funcs),
1843         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_funcs),
1844         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_funcs),
1845         ICPU(INTEL_FAM6_IVYBRIDGE,              core_funcs),
1846         ICPU(INTEL_FAM6_HASWELL_CORE,           core_funcs),
1847         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_funcs),
1848         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_funcs),
1849         ICPU(INTEL_FAM6_HASWELL_X,              core_funcs),
1850         ICPU(INTEL_FAM6_HASWELL_ULT,            core_funcs),
1851         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_funcs),
1852         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_funcs),
1853         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_funcs),
1854         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_funcs),
1855         ICPU(INTEL_FAM6_BROADWELL_X,            core_funcs),
1856         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_funcs),
1857         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_funcs),
1858         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_funcs),
1859         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_funcs),
1860         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_funcs),
1861         ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE,       bxt_funcs),
1862         {}
1863 };
1864 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1865
1866 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1867         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1868         ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1869         ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1870         {}
1871 };
1872
1873 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1874         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1875         {}
1876 };
1877
1878 static bool pid_in_use(void);
1879
1880 static int intel_pstate_init_cpu(unsigned int cpunum)
1881 {
1882         struct cpudata *cpu;
1883
1884         cpu = all_cpu_data[cpunum];
1885
1886         if (!cpu) {
1887                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1888                 if (!cpu)
1889                         return -ENOMEM;
1890
1891                 all_cpu_data[cpunum] = cpu;
1892
1893                 cpu->epp_default = -EINVAL;
1894                 cpu->epp_powersave = -EINVAL;
1895                 cpu->epp_saved = -EINVAL;
1896         }
1897
1898         cpu = all_cpu_data[cpunum];
1899
1900         cpu->cpu = cpunum;
1901
1902         if (hwp_active) {
1903                 const struct x86_cpu_id *id;
1904
1905                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1906                 if (id)
1907                         intel_pstate_disable_ee(cpunum);
1908
1909                 intel_pstate_hwp_enable(cpu);
1910         } else if (pid_in_use()) {
1911                 intel_pstate_pid_reset(cpu);
1912         }
1913
1914         intel_pstate_get_cpu_pstates(cpu);
1915
1916         pr_debug("controlling: cpu %d\n", cpunum);
1917
1918         return 0;
1919 }
1920
1921 static unsigned int intel_pstate_get(unsigned int cpu_num)
1922 {
1923         struct cpudata *cpu = all_cpu_data[cpu_num];
1924
1925         return cpu ? get_avg_frequency(cpu) : 0;
1926 }
1927
1928 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1929 {
1930         struct cpudata *cpu = all_cpu_data[cpu_num];
1931
1932         if (cpu->update_util_set)
1933                 return;
1934
1935         /* Prevent intel_pstate_update_util() from using stale data. */
1936         cpu->sample.time = 0;
1937         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1938                                      pstate_funcs.update_util);
1939         cpu->update_util_set = true;
1940 }
1941
1942 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1943 {
1944         struct cpudata *cpu_data = all_cpu_data[cpu];
1945
1946         if (!cpu_data->update_util_set)
1947                 return;
1948
1949         cpufreq_remove_update_util_hook(cpu);
1950         cpu_data->update_util_set = false;
1951         synchronize_sched();
1952 }
1953
1954 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1955 {
1956         return global.turbo_disabled || global.no_turbo ?
1957                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1958 }
1959
1960 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1961                                             struct cpudata *cpu)
1962 {
1963         int max_freq = intel_pstate_get_max_freq(cpu);
1964         int32_t max_policy_perf, min_policy_perf;
1965
1966         max_policy_perf = div_ext_fp(policy->max, max_freq);
1967         max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1));
1968         if (policy->max == policy->min) {
1969                 min_policy_perf = max_policy_perf;
1970         } else {
1971                 min_policy_perf = div_ext_fp(policy->min, max_freq);
1972                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1973                                           0, max_policy_perf);
1974         }
1975
1976         /* Normalize user input to [min_perf, max_perf] */
1977         if (per_cpu_limits) {
1978                 cpu->min_perf = min_policy_perf;
1979                 cpu->max_perf = max_policy_perf;
1980         } else {
1981                 int32_t global_min, global_max;
1982
1983                 /* Global limits are in percent of the maximum turbo P-state. */
1984                 global_max = percent_ext_fp(global.max_perf_pct);
1985                 global_min = percent_ext_fp(global.min_perf_pct);
1986                 if (max_freq != cpu->pstate.turbo_freq) {
1987                         int32_t turbo_factor;
1988
1989                         turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate,
1990                                                   cpu->pstate.max_pstate);
1991                         global_min = mul_ext_fp(global_min, turbo_factor);
1992                         global_max = mul_ext_fp(global_max, turbo_factor);
1993                 }
1994                 global_min = clamp_t(int32_t, global_min, 0, global_max);
1995
1996                 cpu->min_perf = max(min_policy_perf, global_min);
1997                 cpu->min_perf = min(cpu->min_perf, max_policy_perf);
1998                 cpu->max_perf = min(max_policy_perf, global_max);
1999                 cpu->max_perf = max(min_policy_perf, cpu->max_perf);
2000
2001                 /* Make sure min_perf <= max_perf */
2002                 cpu->min_perf = min(cpu->min_perf, cpu->max_perf);
2003         }
2004
2005         cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS);
2006         cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS);
2007
2008         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2009                  fp_ext_toint(cpu->max_perf * 100),
2010                  fp_ext_toint(cpu->min_perf * 100));
2011 }
2012
2013 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2014 {
2015         struct cpudata *cpu;
2016
2017         if (!policy->cpuinfo.max_freq)
2018                 return -ENODEV;
2019
2020         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2021                  policy->cpuinfo.max_freq, policy->max);
2022
2023         cpu = all_cpu_data[policy->cpu];
2024         cpu->policy = policy->policy;
2025
2026         mutex_lock(&intel_pstate_limits_lock);
2027
2028         intel_pstate_update_perf_limits(policy, cpu);
2029
2030         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2031                 /*
2032                  * NOHZ_FULL CPUs need this as the governor callback may not
2033                  * be invoked on them.
2034                  */
2035                 intel_pstate_clear_update_util_hook(policy->cpu);
2036                 intel_pstate_max_within_limits(cpu);
2037         }
2038
2039         intel_pstate_set_update_util_hook(policy->cpu);
2040
2041         if (hwp_active)
2042                 intel_pstate_hwp_set(policy->cpu);
2043
2044         mutex_unlock(&intel_pstate_limits_lock);
2045
2046         return 0;
2047 }
2048
2049 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2050                                          struct cpudata *cpu)
2051 {
2052         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2053             policy->max < policy->cpuinfo.max_freq &&
2054             policy->max > cpu->pstate.max_freq) {
2055                 pr_debug("policy->max > max non turbo frequency\n");
2056                 policy->max = policy->cpuinfo.max_freq;
2057         }
2058 }
2059
2060 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2061 {
2062         struct cpudata *cpu = all_cpu_data[policy->cpu];
2063
2064         update_turbo_state();
2065         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2066                                      intel_pstate_get_max_freq(cpu));
2067
2068         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2069             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2070                 return -EINVAL;
2071
2072         intel_pstate_adjust_policy_max(policy, cpu);
2073
2074         return 0;
2075 }
2076
2077 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2078 {
2079         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2080 }
2081
2082 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2083 {
2084         pr_debug("CPU %d exiting\n", policy->cpu);
2085
2086         intel_pstate_clear_update_util_hook(policy->cpu);
2087         if (hwp_active)
2088                 intel_pstate_hwp_save_state(policy);
2089         else
2090                 intel_cpufreq_stop_cpu(policy);
2091 }
2092
2093 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2094 {
2095         intel_pstate_exit_perf_limits(policy);
2096
2097         policy->fast_switch_possible = false;
2098
2099         return 0;
2100 }
2101
2102 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2103 {
2104         struct cpudata *cpu;
2105         int rc;
2106
2107         rc = intel_pstate_init_cpu(policy->cpu);
2108         if (rc)
2109                 return rc;
2110
2111         cpu = all_cpu_data[policy->cpu];
2112
2113         cpu->max_perf = int_ext_tofp(1);
2114         cpu->min_perf = 0;
2115
2116         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2117         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2118
2119         /* cpuinfo and default policy values */
2120         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2121         update_turbo_state();
2122         policy->cpuinfo.max_freq = global.turbo_disabled ?
2123                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2124         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2125
2126         intel_pstate_init_acpi_perf_limits(policy);
2127         cpumask_set_cpu(policy->cpu, policy->cpus);
2128
2129         policy->fast_switch_possible = true;
2130
2131         return 0;
2132 }
2133
2134 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2135 {
2136         int ret = __intel_pstate_cpu_init(policy);
2137
2138         if (ret)
2139                 return ret;
2140
2141         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2142         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2143                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2144         else
2145                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2146
2147         return 0;
2148 }
2149
2150 static struct cpufreq_driver intel_pstate = {
2151         .flags          = CPUFREQ_CONST_LOOPS,
2152         .verify         = intel_pstate_verify_policy,
2153         .setpolicy      = intel_pstate_set_policy,
2154         .suspend        = intel_pstate_hwp_save_state,
2155         .resume         = intel_pstate_resume,
2156         .get            = intel_pstate_get,
2157         .init           = intel_pstate_cpu_init,
2158         .exit           = intel_pstate_cpu_exit,
2159         .stop_cpu       = intel_pstate_stop_cpu,
2160         .name           = "intel_pstate",
2161 };
2162
2163 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2164 {
2165         struct cpudata *cpu = all_cpu_data[policy->cpu];
2166
2167         update_turbo_state();
2168         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2169                                      intel_pstate_get_max_freq(cpu));
2170
2171         intel_pstate_adjust_policy_max(policy, cpu);
2172
2173         intel_pstate_update_perf_limits(policy, cpu);
2174
2175         return 0;
2176 }
2177
2178 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2179                                 unsigned int target_freq,
2180                                 unsigned int relation)
2181 {
2182         struct cpudata *cpu = all_cpu_data[policy->cpu];
2183         struct cpufreq_freqs freqs;
2184         int target_pstate;
2185
2186         update_turbo_state();
2187
2188         freqs.old = policy->cur;
2189         freqs.new = target_freq;
2190
2191         cpufreq_freq_transition_begin(policy, &freqs);
2192         switch (relation) {
2193         case CPUFREQ_RELATION_L:
2194                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2195                 break;
2196         case CPUFREQ_RELATION_H:
2197                 target_pstate = freqs.new / cpu->pstate.scaling;
2198                 break;
2199         default:
2200                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2201                 break;
2202         }
2203         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2204         if (target_pstate != cpu->pstate.current_pstate) {
2205                 cpu->pstate.current_pstate = target_pstate;
2206                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2207                               pstate_funcs.get_val(cpu, target_pstate));
2208         }
2209         freqs.new = target_pstate * cpu->pstate.scaling;
2210         cpufreq_freq_transition_end(policy, &freqs, false);
2211
2212         return 0;
2213 }
2214
2215 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2216                                               unsigned int target_freq)
2217 {
2218         struct cpudata *cpu = all_cpu_data[policy->cpu];
2219         int target_pstate;
2220
2221         update_turbo_state();
2222
2223         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2224         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2225         intel_pstate_update_pstate(cpu, target_pstate);
2226         return target_pstate * cpu->pstate.scaling;
2227 }
2228
2229 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2230 {
2231         int ret = __intel_pstate_cpu_init(policy);
2232
2233         if (ret)
2234                 return ret;
2235
2236         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2237         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2238         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2239         policy->cur = policy->cpuinfo.min_freq;
2240
2241         return 0;
2242 }
2243
2244 static struct cpufreq_driver intel_cpufreq = {
2245         .flags          = CPUFREQ_CONST_LOOPS,
2246         .verify         = intel_cpufreq_verify_policy,
2247         .target         = intel_cpufreq_target,
2248         .fast_switch    = intel_cpufreq_fast_switch,
2249         .init           = intel_cpufreq_cpu_init,
2250         .exit           = intel_pstate_cpu_exit,
2251         .stop_cpu       = intel_cpufreq_stop_cpu,
2252         .name           = "intel_cpufreq",
2253 };
2254
2255 static struct cpufreq_driver *default_driver = &intel_pstate;
2256
2257 static bool pid_in_use(void)
2258 {
2259         return intel_pstate_driver == &intel_pstate &&
2260                 pstate_funcs.update_util == intel_pstate_update_util_pid;
2261 }
2262
2263 static void intel_pstate_driver_cleanup(void)
2264 {
2265         unsigned int cpu;
2266
2267         get_online_cpus();
2268         for_each_online_cpu(cpu) {
2269                 if (all_cpu_data[cpu]) {
2270                         if (intel_pstate_driver == &intel_pstate)
2271                                 intel_pstate_clear_update_util_hook(cpu);
2272
2273                         kfree(all_cpu_data[cpu]);
2274                         all_cpu_data[cpu] = NULL;
2275                 }
2276         }
2277         put_online_cpus();
2278         intel_pstate_driver = NULL;
2279 }
2280
2281 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2282 {
2283         int ret;
2284
2285         memset(&global, 0, sizeof(global));
2286         global.max_perf_pct = 100;
2287
2288         intel_pstate_driver = driver;
2289         ret = cpufreq_register_driver(intel_pstate_driver);
2290         if (ret) {
2291                 intel_pstate_driver_cleanup();
2292                 return ret;
2293         }
2294
2295         global.min_perf_pct = min_perf_pct_min();
2296
2297         if (pid_in_use())
2298                 intel_pstate_debug_expose_params();
2299
2300         return 0;
2301 }
2302
2303 static int intel_pstate_unregister_driver(void)
2304 {
2305         if (hwp_active)
2306                 return -EBUSY;
2307
2308         if (pid_in_use())
2309                 intel_pstate_debug_hide_params();
2310
2311         cpufreq_unregister_driver(intel_pstate_driver);
2312         intel_pstate_driver_cleanup();
2313
2314         return 0;
2315 }
2316
2317 static ssize_t intel_pstate_show_status(char *buf)
2318 {
2319         if (!intel_pstate_driver)
2320                 return sprintf(buf, "off\n");
2321
2322         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2323                                         "active" : "passive");
2324 }
2325
2326 static int intel_pstate_update_status(const char *buf, size_t size)
2327 {
2328         int ret;
2329
2330         if (size == 3 && !strncmp(buf, "off", size))
2331                 return intel_pstate_driver ?
2332                         intel_pstate_unregister_driver() : -EINVAL;
2333
2334         if (size == 6 && !strncmp(buf, "active", size)) {
2335                 if (intel_pstate_driver) {
2336                         if (intel_pstate_driver == &intel_pstate)
2337                                 return 0;
2338
2339                         ret = intel_pstate_unregister_driver();
2340                         if (ret)
2341                                 return ret;
2342                 }
2343
2344                 return intel_pstate_register_driver(&intel_pstate);
2345         }
2346
2347         if (size == 7 && !strncmp(buf, "passive", size)) {
2348                 if (intel_pstate_driver) {
2349                         if (intel_pstate_driver == &intel_cpufreq)
2350                                 return 0;
2351
2352                         ret = intel_pstate_unregister_driver();
2353                         if (ret)
2354                                 return ret;
2355                 }
2356
2357                 return intel_pstate_register_driver(&intel_cpufreq);
2358         }
2359
2360         return -EINVAL;
2361 }
2362
2363 static int no_load __initdata;
2364 static int no_hwp __initdata;
2365 static int hwp_only __initdata;
2366 static unsigned int force_load __initdata;
2367
2368 static int __init intel_pstate_msrs_not_valid(void)
2369 {
2370         if (!pstate_funcs.get_max() ||
2371             !pstate_funcs.get_min() ||
2372             !pstate_funcs.get_turbo())
2373                 return -ENODEV;
2374
2375         return 0;
2376 }
2377
2378 #ifdef CONFIG_ACPI
2379 static void intel_pstate_use_acpi_profile(void)
2380 {
2381         switch (acpi_gbl_FADT.preferred_profile) {
2382         case PM_MOBILE:
2383         case PM_TABLET:
2384         case PM_APPLIANCE_PC:
2385         case PM_DESKTOP:
2386         case PM_WORKSTATION:
2387                 pstate_funcs.update_util = intel_pstate_update_util;
2388         }
2389 }
2390 #else
2391 static void intel_pstate_use_acpi_profile(void)
2392 {
2393 }
2394 #endif
2395
2396 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2397 {
2398         pstate_funcs.get_max   = funcs->get_max;
2399         pstate_funcs.get_max_physical = funcs->get_max_physical;
2400         pstate_funcs.get_min   = funcs->get_min;
2401         pstate_funcs.get_turbo = funcs->get_turbo;
2402         pstate_funcs.get_scaling = funcs->get_scaling;
2403         pstate_funcs.get_val   = funcs->get_val;
2404         pstate_funcs.get_vid   = funcs->get_vid;
2405         pstate_funcs.update_util = funcs->update_util;
2406
2407         intel_pstate_use_acpi_profile();
2408 }
2409
2410 #ifdef CONFIG_ACPI
2411
2412 static bool __init intel_pstate_no_acpi_pss(void)
2413 {
2414         int i;
2415
2416         for_each_possible_cpu(i) {
2417                 acpi_status status;
2418                 union acpi_object *pss;
2419                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2420                 struct acpi_processor *pr = per_cpu(processors, i);
2421
2422                 if (!pr)
2423                         continue;
2424
2425                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2426                 if (ACPI_FAILURE(status))
2427                         continue;
2428
2429                 pss = buffer.pointer;
2430                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2431                         kfree(pss);
2432                         return false;
2433                 }
2434
2435                 kfree(pss);
2436         }
2437
2438         return true;
2439 }
2440
2441 static bool __init intel_pstate_has_acpi_ppc(void)
2442 {
2443         int i;
2444
2445         for_each_possible_cpu(i) {
2446                 struct acpi_processor *pr = per_cpu(processors, i);
2447
2448                 if (!pr)
2449                         continue;
2450                 if (acpi_has_method(pr->handle, "_PPC"))
2451                         return true;
2452         }
2453         return false;
2454 }
2455
2456 enum {
2457         PSS,
2458         PPC,
2459 };
2460
2461 struct hw_vendor_info {
2462         u16  valid;
2463         char oem_id[ACPI_OEM_ID_SIZE];
2464         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2465         int  oem_pwr_table;
2466 };
2467
2468 /* Hardware vendor-specific info that has its own power management modes */
2469 static struct hw_vendor_info vendor_info[] __initdata = {
2470         {1, "HP    ", "ProLiant", PSS},
2471         {1, "ORACLE", "X4-2    ", PPC},
2472         {1, "ORACLE", "X4-2L   ", PPC},
2473         {1, "ORACLE", "X4-2B   ", PPC},
2474         {1, "ORACLE", "X3-2    ", PPC},
2475         {1, "ORACLE", "X3-2L   ", PPC},
2476         {1, "ORACLE", "X3-2B   ", PPC},
2477         {1, "ORACLE", "X4470M2 ", PPC},
2478         {1, "ORACLE", "X4270M3 ", PPC},
2479         {1, "ORACLE", "X4270M2 ", PPC},
2480         {1, "ORACLE", "X4170M2 ", PPC},
2481         {1, "ORACLE", "X4170 M3", PPC},
2482         {1, "ORACLE", "X4275 M3", PPC},
2483         {1, "ORACLE", "X6-2    ", PPC},
2484         {1, "ORACLE", "Sudbury ", PPC},
2485         {0, "", ""},
2486 };
2487
2488 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2489 {
2490         struct acpi_table_header hdr;
2491         struct hw_vendor_info *v_info;
2492         const struct x86_cpu_id *id;
2493         u64 misc_pwr;
2494
2495         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2496         if (id) {
2497                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2498                 if ( misc_pwr & (1 << 8))
2499                         return true;
2500         }
2501
2502         if (acpi_disabled ||
2503             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2504                 return false;
2505
2506         for (v_info = vendor_info; v_info->valid; v_info++) {
2507                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2508                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2509                                                 ACPI_OEM_TABLE_ID_SIZE))
2510                         switch (v_info->oem_pwr_table) {
2511                         case PSS:
2512                                 return intel_pstate_no_acpi_pss();
2513                         case PPC:
2514                                 return intel_pstate_has_acpi_ppc() &&
2515                                         (!force_load);
2516                         }
2517         }
2518
2519         return false;
2520 }
2521
2522 static void intel_pstate_request_control_from_smm(void)
2523 {
2524         /*
2525          * It may be unsafe to request P-states control from SMM if _PPC support
2526          * has not been enabled.
2527          */
2528         if (acpi_ppc)
2529                 acpi_processor_pstate_control();
2530 }
2531 #else /* CONFIG_ACPI not enabled */
2532 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2533 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2534 static inline void intel_pstate_request_control_from_smm(void) {}
2535 #endif /* CONFIG_ACPI */
2536
2537 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2538         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2539         {}
2540 };
2541
2542 static int __init intel_pstate_init(void)
2543 {
2544         int rc;
2545
2546         if (no_load)
2547                 return -ENODEV;
2548
2549         if (x86_match_cpu(hwp_support_ids)) {
2550                 copy_cpu_funcs(&core_funcs);
2551                 if (no_hwp) {
2552                         pstate_funcs.update_util = intel_pstate_update_util;
2553                 } else {
2554                         hwp_active++;
2555                         intel_pstate.attr = hwp_cpufreq_attrs;
2556                         pstate_funcs.update_util = intel_pstate_update_util_hwp;
2557                         goto hwp_cpu_matched;
2558                 }
2559         } else {
2560                 const struct x86_cpu_id *id;
2561
2562                 id = x86_match_cpu(intel_pstate_cpu_ids);
2563                 if (!id)
2564                         return -ENODEV;
2565
2566                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2567         }
2568
2569         if (intel_pstate_msrs_not_valid())
2570                 return -ENODEV;
2571
2572 hwp_cpu_matched:
2573         /*
2574          * The Intel pstate driver will be ignored if the platform
2575          * firmware has its own power management modes.
2576          */
2577         if (intel_pstate_platform_pwr_mgmt_exists())
2578                 return -ENODEV;
2579
2580         if (!hwp_active && hwp_only)
2581                 return -ENOTSUPP;
2582
2583         pr_info("Intel P-state driver initializing\n");
2584
2585         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2586         if (!all_cpu_data)
2587                 return -ENOMEM;
2588
2589         intel_pstate_request_control_from_smm();
2590
2591         intel_pstate_sysfs_expose_params();
2592
2593         mutex_lock(&intel_pstate_driver_lock);
2594         rc = intel_pstate_register_driver(default_driver);
2595         mutex_unlock(&intel_pstate_driver_lock);
2596         if (rc)
2597                 return rc;
2598
2599         if (hwp_active)
2600                 pr_info("HWP enabled\n");
2601
2602         return 0;
2603 }
2604 device_initcall(intel_pstate_init);
2605
2606 static int __init intel_pstate_setup(char *str)
2607 {
2608         if (!str)
2609                 return -EINVAL;
2610
2611         if (!strcmp(str, "disable")) {
2612                 no_load = 1;
2613         } else if (!strcmp(str, "passive")) {
2614                 pr_info("Passive mode enabled\n");
2615                 default_driver = &intel_cpufreq;
2616                 no_hwp = 1;
2617         }
2618         if (!strcmp(str, "no_hwp")) {
2619                 pr_info("HWP disabled\n");
2620                 no_hwp = 1;
2621         }
2622         if (!strcmp(str, "force"))
2623                 force_load = 1;
2624         if (!strcmp(str, "hwp_only"))
2625                 hwp_only = 1;
2626         if (!strcmp(str, "per_cpu_perf_limits"))
2627                 per_cpu_limits = true;
2628
2629 #ifdef CONFIG_ACPI
2630         if (!strcmp(str, "support_acpi_ppc"))
2631                 acpi_ppc = true;
2632 #endif
2633
2634         return 0;
2635 }
2636 early_param("intel_pstate", intel_pstate_setup);
2637
2638 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2639 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2640 MODULE_LICENSE("GPL");