drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/cpu.h>
  31 #include <asm/div64.h>
  32 #include <asm/msr.h>
  33 #include <asm/cpu_device_id.h>
  34 #include <asm/cpufeature.h>
  35 #include <asm/intel-family.h>
  36 #include "../drivers/thermal/intel/thermal_interrupt.h"
  37
  38 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP      5000
  42 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  43
  44 #ifdef CONFIG_ACPI
  45 #include <acpi/processor.h>
  46 #include <acpi/cppc_acpi.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  54
  55 #define EXT_BITS 6
  56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  59
  60 static inline int32_t mul_fp(int32_t x, int32_t y)
  61 {
  62         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  63 }
  64
  65 static inline int32_t div_fp(s64 x, s64 y)
  66 {
  67         return div64_s64((int64_t)x << FRAC_BITS, y);
  68 }
  69
  70 static inline int ceiling_fp(int32_t x)
  71 {
  72         int mask, ret;
  73
  74         ret = fp_toint(x);
  75         mask = (1 << FRAC_BITS) - 1;
  76         if (x & mask)
  77                 ret += 1;
  78         return ret;
  79 }
  80
  81 static inline u64 mul_ext_fp(u64 x, u64 y)
  82 {
  83         return (x * y) >> EXT_FRAC_BITS;
  84 }
  85
  86 static inline u64 div_ext_fp(u64 x, u64 y)
  87 {
  88         return div64_u64(x << EXT_FRAC_BITS, y);
  89 }
  90
  91 /**
  92  * struct sample -      Store performance sample
  93  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  94  *                      performance during last sample period
  95  * @busy_scaled:        Scaled busy value which is used to calculate next
  96  *                      P state. This can be different than core_avg_perf
  97  *                      to account for cpu idle period
  98  * @aperf:              Difference of actual performance frequency clock count
  99  *                      read from APERF MSR between last and current sample
 100  * @mperf:              Difference of maximum performance frequency clock count
 101  *                      read from MPERF MSR between last and current sample
 102  * @tsc:                Difference of time stamp counter between last and
 103  *                      current sample
 104  * @time:               Current time from scheduler
 105  *
 106  * This structure is used in the cpudata structure to store performance sample
 107  * data for choosing next P State.
 108  */
 109 struct sample {
 110         int32_t core_avg_perf;
 111         int32_t busy_scaled;
 112         u64 aperf;
 113         u64 mperf;
 114         u64 tsc;
 115         u64 time;
 116 };
 117
 118 /**
 119  * struct pstate_data - Store P state data
 120  * @current_pstate:     Current requested P state
 121  * @min_pstate:         Min P state possible for this platform
 122  * @max_pstate:         Max P state possible for this platform
 123  * @max_pstate_physical:This is physical Max P state for a processor
 124  *                      This can be higher than the max_pstate which can
 125  *                      be limited by platform thermal design power limits
 126  * @perf_ctl_scaling:   PERF_CTL P-state to frequency scaling factor
 127  * @scaling:            Scaling factor between performance and frequency
 128  * @turbo_pstate:       Max Turbo P state possible for this platform
 129  * @min_freq:           @min_pstate frequency in cpufreq units
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     perf_ctl_scaling;
 141         int     scaling;
 142         int     turbo_pstate;
 143         unsigned int min_freq;
 144         unsigned int max_freq;
 145         unsigned int turbo_freq;
 146 };
 147
 148 /**
 149  * struct vid_data -    Stores voltage information data
 150  * @min:                VID data for this platform corresponding to
 151  *                      the lowest P state
 152  * @max:                VID data corresponding to the highest P State.
 153  * @turbo:              VID data for turbo P state
 154  * @ratio:              Ratio of (vid max - vid min) /
 155  *                      (max P state - Min P State)
 156  *
 157  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 158  * This data is used in Atom platforms, where in addition to target P state,
 159  * the voltage data needs to be specified to select next P State.
 160  */
 161 struct vid_data {
 162         int min;
 163         int max;
 164         int turbo;
 165         int32_t ratio;
 166 };
 167
 168 /**
 169  * struct global_params - Global parameters, mostly tunable via sysfs.
 170  * @no_turbo:           Whether or not to use turbo P-states.
 171  * @turbo_disabled:     Whether or not turbo P-states are available at all,
 172  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 173  *                      not the maximum reported turbo P-state is different from
 174  *                      the maximum reported non-turbo one.
 175  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 176  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 177  *                      P-state capacity.
 178  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 179  *                      P-state capacity.
 180  */
 181 struct global_params {
 182         bool no_turbo;
 183         bool turbo_disabled;
 184         bool turbo_disabled_mf;
 185         int max_perf_pct;
 186         int min_perf_pct;
 187 };
 188
 189 /**
 190  * struct cpudata -     Per CPU instance data storage
 191  * @cpu:                CPU number for this instance data
 192  * @policy:             CPUFreq policy value
 193  * @update_util:        CPUFreq utility callback information
 194  * @update_util_set:    CPUFreq utility callback is set
 195  * @iowait_boost:       iowait-related boost fraction
 196  * @last_update:        Time of the last update.
 197  * @pstate:             Stores P state limits for this CPU
 198  * @vid:                Stores VID limits for this CPU
 199  * @last_sample_time:   Last Sample time
 200  * @aperf_mperf_shift:  APERF vs MPERF counting frequency difference
 201  * @prev_aperf:         Last APERF value read from APERF MSR
 202  * @prev_mperf:         Last MPERF value read from MPERF MSR
 203  * @prev_tsc:           Last timestamp counter (TSC) value
 204  * @prev_cummulative_iowait: IO Wait time difference from last and
 205  *                      current sample
 206  * @sample:             Storage for storing last Sample data
 207  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 208  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 209  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 210  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 211  * @epp_powersave:      Last saved HWP energy performance preference
 212  *                      (EPP) or energy performance bias (EPB),
 213  *                      when policy switched to performance
 214  * @epp_policy:         Last saved policy used to set EPP/EPB
 215  * @epp_default:        Power on default HWP energy performance
 216  *                      preference/bias
 217  * @epp_cached          Cached HWP energy-performance preference value
 218  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 219  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 220  * @last_io_update:     Last time when IO wake flag was set
 221  * @sched_flags:        Store scheduler flags for possible cross CPU update
 222  * @hwp_boost_min:      Last HWP boosted min performance
 223  * @suspended:          Whether or not the driver has been suspended.
 224  * @hwp_notify_work:    workqueue for HWP notifications.
 225  *
 226  * This structure stores per CPU instance data for all CPUs.
 227  */
 228 struct cpudata {
 229         int cpu;
 230
 231         unsigned int policy;
 232         struct update_util_data update_util;
 233         bool   update_util_set;
 234
 235         struct pstate_data pstate;
 236         struct vid_data vid;
 237
 238         u64     last_update;
 239         u64     last_sample_time;
 240         u64     aperf_mperf_shift;
 241         u64     prev_aperf;
 242         u64     prev_mperf;
 243         u64     prev_tsc;
 244         u64     prev_cummulative_iowait;
 245         struct sample sample;
 246         int32_t min_perf_ratio;
 247         int32_t max_perf_ratio;
 248 #ifdef CONFIG_ACPI
 249         struct acpi_processor_performance acpi_perf_data;
 250         bool valid_pss_table;
 251 #endif
 252         unsigned int iowait_boost;
 253         s16 epp_powersave;
 254         s16 epp_policy;
 255         s16 epp_default;
 256         s16 epp_cached;
 257         u64 hwp_req_cached;
 258         u64 hwp_cap_cached;
 259         u64 last_io_update;
 260         unsigned int sched_flags;
 261         u32 hwp_boost_min;
 262         bool suspended;
 263         struct delayed_work hwp_notify_work;
 264 };
 265
 266 static struct cpudata **all_cpu_data;
 267
 268 /**
 269  * struct pstate_funcs - Per CPU model specific callbacks
 270  * @get_max:            Callback to get maximum non turbo effective P state
 271  * @get_max_physical:   Callback to get maximum non turbo physical P state
 272  * @get_min:            Callback to get minimum P state
 273  * @get_turbo:          Callback to get turbo P state
 274  * @get_scaling:        Callback to get frequency scaling factor
 275  * @get_cpu_scaling:    Get frequency scaling factor for a given cpu
 276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(int cpu);
 285         int (*get_max_physical)(int cpu);
 286         int (*get_min)(int cpu);
 287         int (*get_turbo)(int cpu);
 288         int (*get_scaling)(void);
 289         int (*get_cpu_scaling)(int cpu);
 290         int (*get_aperf_mperf_shift)(void);
 291         u64 (*get_val)(struct cpudata*, int pstate);
 292         void (*get_vid)(struct cpudata *);
 293 };
 294
 295 static struct pstate_funcs pstate_funcs __read_mostly;
 296
 297 static int hwp_active __read_mostly;
 298 static int hwp_mode_bdw __read_mostly;
 299 static bool per_cpu_limits __read_mostly;
 300 static bool hwp_boost __read_mostly;
 301 static bool hwp_forced __read_mostly;
 302
 303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 304
 305 #ifdef CONFIG_ACPI
 306 static bool acpi_ppc;
 307 #endif
 308
 309 static struct global_params global;
 310
 311 static DEFINE_MUTEX(intel_pstate_driver_lock);
 312 static DEFINE_MUTEX(intel_pstate_limits_lock);
 313
 314 #ifdef CONFIG_ACPI
 315
 316 static bool intel_pstate_acpi_pm_profile_server(void)
 317 {
 318         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 319             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 320                 return true;
 321
 322         return false;
 323 }
 324
 325 static bool intel_pstate_get_ppc_enable_status(void)
 326 {
 327         if (intel_pstate_acpi_pm_profile_server())
 328                 return true;
 329
 330         return acpi_ppc;
 331 }
 332
 333 #ifdef CONFIG_ACPI_CPPC_LIB
 334
 335 /* The work item is needed to avoid CPU hotplug locking issues */
 336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 337 {
 338         sched_set_itmt_support();
 339 }
 340
 341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 342
 343 #define CPPC_MAX_PERF   U8_MAX
 344
 345 static void intel_pstate_set_itmt_prio(int cpu)
 346 {
 347         struct cppc_perf_caps cppc_perf;
 348         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 349         int ret;
 350
 351         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 352         if (ret)
 353                 return;
 354
 355         /*
 356          * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
 357          * In this case we can't use CPPC.highest_perf to enable ITMT.
 358          * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
 359          */
 360         if (cppc_perf.highest_perf == CPPC_MAX_PERF)
 361                 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
 362
 363         /*
 364          * The priorities can be set regardless of whether or not
 365          * sched_set_itmt_support(true) has been called and it is valid to
 366          * update them at any time after it has been called.
 367          */
 368         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 369
 370         if (max_highest_perf <= min_highest_perf) {
 371                 if (cppc_perf.highest_perf > max_highest_perf)
 372                         max_highest_perf = cppc_perf.highest_perf;
 373
 374                 if (cppc_perf.highest_perf < min_highest_perf)
 375                         min_highest_perf = cppc_perf.highest_perf;
 376
 377                 if (max_highest_perf > min_highest_perf) {
 378                         /*
 379                          * This code can be run during CPU online under the
 380                          * CPU hotplug locks, so sched_set_itmt_support()
 381                          * cannot be called from here.  Queue up a work item
 382                          * to invoke it.
 383                          */
 384                         schedule_work(&sched_itmt_work);
 385                 }
 386         }
 387 }
 388
 389 static int intel_pstate_get_cppc_guaranteed(int cpu)
 390 {
 391         struct cppc_perf_caps cppc_perf;
 392         int ret;
 393
 394         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 395         if (ret)
 396                 return ret;
 397
 398         if (cppc_perf.guaranteed_perf)
 399                 return cppc_perf.guaranteed_perf;
 400
 401         return cppc_perf.nominal_perf;
 402 }
 403 #else /* CONFIG_ACPI_CPPC_LIB */
 404 static inline void intel_pstate_set_itmt_prio(int cpu)
 405 {
 406 }
 407 #endif /* CONFIG_ACPI_CPPC_LIB */
 408
 409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 410 {
 411         struct cpudata *cpu;
 412         int ret;
 413         int i;
 414
 415         if (hwp_active) {
 416                 intel_pstate_set_itmt_prio(policy->cpu);
 417                 return;
 418         }
 419
 420         if (!intel_pstate_get_ppc_enable_status())
 421                 return;
 422
 423         cpu = all_cpu_data[policy->cpu];
 424
 425         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 426                                                   policy->cpu);
 427         if (ret)
 428                 return;
 429
 430         /*
 431          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 432          * guarantee that the states returned by it map to the states in our
 433          * list directly.
 434          */
 435         if (cpu->acpi_perf_data.control_register.space_id !=
 436                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 437                 goto err;
 438
 439         /*
 440          * If there is only one entry _PSS, simply ignore _PSS and continue as
 441          * usual without taking _PSS into account
 442          */
 443         if (cpu->acpi_perf_data.state_count < 2)
 444                 goto err;
 445
 446         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 447         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 448                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 449                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 450                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 451                          (u32) cpu->acpi_perf_data.states[i].power,
 452                          (u32) cpu->acpi_perf_data.states[i].control);
 453         }
 454
 455         cpu->valid_pss_table = true;
 456         pr_debug("_PPC limits will be enforced\n");
 457
 458         return;
 459
 460  err:
 461         cpu->valid_pss_table = false;
 462         acpi_processor_unregister_performance(policy->cpu);
 463 }
 464
 465 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 466 {
 467         struct cpudata *cpu;
 468
 469         cpu = all_cpu_data[policy->cpu];
 470         if (!cpu->valid_pss_table)
 471                 return;
 472
 473         acpi_processor_unregister_performance(policy->cpu);
 474 }
 475 #else /* CONFIG_ACPI */
 476 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 477 {
 478 }
 479
 480 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 481 {
 482 }
 483
 484 static inline bool intel_pstate_acpi_pm_profile_server(void)
 485 {
 486         return false;
 487 }
 488 #endif /* CONFIG_ACPI */
 489
 490 #ifndef CONFIG_ACPI_CPPC_LIB
 491 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
 492 {
 493         return -ENOTSUPP;
 494 }
 495 #endif /* CONFIG_ACPI_CPPC_LIB */
 496
 497 /**
 498  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
 499  * @cpu: Target CPU.
 500  *
 501  * On hybrid processors, HWP may expose more performance levels than there are
 502  * P-states accessible through the PERF_CTL interface.  If that happens, the
 503  * scaling factor between HWP performance levels and CPU frequency will be less
 504  * than the scaling factor between P-state values and CPU frequency.
 505  *
 506  * In that case, adjust the CPU parameters used in computations accordingly.
 507  */
 508 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
 509 {
 510         int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
 511         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 512         int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
 513         int scaling = cpu->pstate.scaling;
 514
 515         pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
 516         pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
 517         pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
 518         pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
 519         pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
 520         pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
 521
 522         cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
 523                                            perf_ctl_scaling);
 524         cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
 525                                          perf_ctl_scaling);
 526
 527         cpu->pstate.max_pstate_physical =
 528                         DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling,
 529                                      scaling);
 530
 531         cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
 532         /*
 533          * Cast the min P-state value retrieved via pstate_funcs.get_min() to
 534          * the effective range of HWP performance levels.
 535          */
 536         cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling);
 537 }
 538
 539 static inline void update_turbo_state(void)
 540 {
 541         u64 misc_en;
 542         struct cpudata *cpu;
 543
 544         cpu = all_cpu_data[0];
 545         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 546         global.turbo_disabled =
 547                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 548                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 549 }
 550
 551 static int min_perf_pct_min(void)
 552 {
 553         struct cpudata *cpu = all_cpu_data[0];
 554         int turbo_pstate = cpu->pstate.turbo_pstate;
 555
 556         return turbo_pstate ?
 557                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 558 }
 559
 560 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 561 {
 562         u64 epb;
 563         int ret;
 564
 565         if (!boot_cpu_has(X86_FEATURE_EPB))
 566                 return -ENXIO;
 567
 568         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 569         if (ret)
 570                 return (s16)ret;
 571
 572         return (s16)(epb & 0x0f);
 573 }
 574
 575 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 576 {
 577         s16 epp;
 578
 579         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 580                 /*
 581                  * When hwp_req_data is 0, means that caller didn't read
 582                  * MSR_HWP_REQUEST, so need to read and get EPP.
 583                  */
 584                 if (!hwp_req_data) {
 585                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 586                                             &hwp_req_data);
 587                         if (epp)
 588                                 return epp;
 589                 }
 590                 epp = (hwp_req_data >> 24) & 0xff;
 591         } else {
 592                 /* When there is no EPP present, HWP uses EPB settings */
 593                 epp = intel_pstate_get_epb(cpu_data);
 594         }
 595
 596         return epp;
 597 }
 598
 599 static int intel_pstate_set_epb(int cpu, s16 pref)
 600 {
 601         u64 epb;
 602         int ret;
 603
 604         if (!boot_cpu_has(X86_FEATURE_EPB))
 605                 return -ENXIO;
 606
 607         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 608         if (ret)
 609                 return ret;
 610
 611         epb = (epb & ~0x0f) | pref;
 612         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 613
 614         return 0;
 615 }
 616
 617 /*
 618  * EPP/EPB display strings corresponding to EPP index in the
 619  * energy_perf_strings[]
 620  *      index           String
 621  *-------------------------------------
 622  *      0               default
 623  *      1               performance
 624  *      2               balance_performance
 625  *      3               balance_power
 626  *      4               power
 627  */
 628
 629 enum energy_perf_value_index {
 630         EPP_INDEX_DEFAULT = 0,
 631         EPP_INDEX_PERFORMANCE,
 632         EPP_INDEX_BALANCE_PERFORMANCE,
 633         EPP_INDEX_BALANCE_POWERSAVE,
 634         EPP_INDEX_POWERSAVE,
 635 };
 636
 637 static const char * const energy_perf_strings[] = {
 638         [EPP_INDEX_DEFAULT] = "default",
 639         [EPP_INDEX_PERFORMANCE] = "performance",
 640         [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
 641         [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
 642         [EPP_INDEX_POWERSAVE] = "power",
 643         NULL
 644 };
 645 static unsigned int epp_values[] = {
 646         [EPP_INDEX_DEFAULT] = 0, /* Unused index */
 647         [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
 648         [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
 649         [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
 650         [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
 651 };
 652
 653 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
 654 {
 655         s16 epp;
 656         int index = -EINVAL;
 657
 658         *raw_epp = 0;
 659         epp = intel_pstate_get_epp(cpu_data, 0);
 660         if (epp < 0)
 661                 return epp;
 662
 663         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 664                 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
 665                         return EPP_INDEX_PERFORMANCE;
 666                 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
 667                         return EPP_INDEX_BALANCE_PERFORMANCE;
 668                 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
 669                         return EPP_INDEX_BALANCE_POWERSAVE;
 670                 if (epp == epp_values[EPP_INDEX_POWERSAVE])
 671                         return EPP_INDEX_POWERSAVE;
 672                 *raw_epp = epp;
 673                 return 0;
 674         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 675                 /*
 676                  * Range:
 677                  *      0x00-0x03       :       Performance
 678                  *      0x04-0x07       :       Balance performance
 679                  *      0x08-0x0B       :       Balance power
 680                  *      0x0C-0x0F       :       Power
 681                  * The EPB is a 4 bit value, but our ranges restrict the
 682                  * value which can be set. Here only using top two bits
 683                  * effectively.
 684                  */
 685                 index = (epp >> 2) + 1;
 686         }
 687
 688         return index;
 689 }
 690
 691 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
 692 {
 693         int ret;
 694
 695         /*
 696          * Use the cached HWP Request MSR value, because in the active mode the
 697          * register itself may be updated by intel_pstate_hwp_boost_up() or
 698          * intel_pstate_hwp_boost_down() at any time.
 699          */
 700         u64 value = READ_ONCE(cpu->hwp_req_cached);
 701
 702         value &= ~GENMASK_ULL(31, 24);
 703         value |= (u64)epp << 24;
 704         /*
 705          * The only other updater of hwp_req_cached in the active mode,
 706          * intel_pstate_hwp_set(), is called under the same lock as this
 707          * function, so it cannot run in parallel with the update below.
 708          */
 709         WRITE_ONCE(cpu->hwp_req_cached, value);
 710         ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
 711         if (!ret)
 712                 cpu->epp_cached = epp;
 713
 714         return ret;
 715 }
 716
 717 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 718                                               int pref_index, bool use_raw,
 719                                               u32 raw_epp)
 720 {
 721         int epp = -EINVAL;
 722         int ret;
 723
 724         if (!pref_index)
 725                 epp = cpu_data->epp_default;
 726
 727         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 728                 if (use_raw)
 729                         epp = raw_epp;
 730                 else if (epp == -EINVAL)
 731                         epp = epp_values[pref_index];
 732
 733                 /*
 734                  * To avoid confusion, refuse to set EPP to any values different
 735                  * from 0 (performance) if the current policy is "performance",
 736                  * because those values would be overridden.
 737                  */
 738                 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 739                         return -EBUSY;
 740
 741                 ret = intel_pstate_set_epp(cpu_data, epp);
 742         } else {
 743                 if (epp == -EINVAL)
 744                         epp = (pref_index - 1) << 2;
 745                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 746         }
 747
 748         return ret;
 749 }
 750
 751 static ssize_t show_energy_performance_available_preferences(
 752                                 struct cpufreq_policy *policy, char *buf)
 753 {
 754         int i = 0;
 755         int ret = 0;
 756
 757         while (energy_perf_strings[i] != NULL)
 758                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 759
 760         ret += sprintf(&buf[ret], "\n");
 761
 762         return ret;
 763 }
 764
 765 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 766
 767 static struct cpufreq_driver intel_pstate;
 768
 769 static ssize_t store_energy_performance_preference(
 770                 struct cpufreq_policy *policy, const char *buf, size_t count)
 771 {
 772         struct cpudata *cpu = all_cpu_data[policy->cpu];
 773         char str_preference[21];
 774         bool raw = false;
 775         ssize_t ret;
 776         u32 epp = 0;
 777
 778         ret = sscanf(buf, "%20s", str_preference);
 779         if (ret != 1)
 780                 return -EINVAL;
 781
 782         ret = match_string(energy_perf_strings, -1, str_preference);
 783         if (ret < 0) {
 784                 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
 785                         return ret;
 786
 787                 ret = kstrtouint(buf, 10, &epp);
 788                 if (ret)
 789                         return ret;
 790
 791                 if (epp > 255)
 792                         return -EINVAL;
 793
 794                 raw = true;
 795         }
 796
 797         /*
 798          * This function runs with the policy R/W semaphore held, which
 799          * guarantees that the driver pointer will not change while it is
 800          * running.
 801          */
 802         if (!intel_pstate_driver)
 803                 return -EAGAIN;
 804
 805         mutex_lock(&intel_pstate_limits_lock);
 806
 807         if (intel_pstate_driver == &intel_pstate) {
 808                 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
 809         } else {
 810                 /*
 811                  * In the passive mode the governor needs to be stopped on the
 812                  * target CPU before the EPP update and restarted after it,
 813                  * which is super-heavy-weight, so make sure it is worth doing
 814                  * upfront.
 815                  */
 816                 if (!raw)
 817                         epp = ret ? epp_values[ret] : cpu->epp_default;
 818
 819                 if (cpu->epp_cached != epp) {
 820                         int err;
 821
 822                         cpufreq_stop_governor(policy);
 823                         ret = intel_pstate_set_epp(cpu, epp);
 824                         err = cpufreq_start_governor(policy);
 825                         if (!ret)
 826                                 ret = err;
 827                 }
 828         }
 829
 830         mutex_unlock(&intel_pstate_limits_lock);
 831
 832         return ret ?: count;
 833 }
 834
 835 static ssize_t show_energy_performance_preference(
 836                                 struct cpufreq_policy *policy, char *buf)
 837 {
 838         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 839         int preference, raw_epp;
 840
 841         preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
 842         if (preference < 0)
 843                 return preference;
 844
 845         if (raw_epp)
 846                 return  sprintf(buf, "%d\n", raw_epp);
 847         else
 848                 return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 849 }
 850
 851 cpufreq_freq_attr_rw(energy_performance_preference);
 852
 853 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 854 {
 855         struct cpudata *cpu = all_cpu_data[policy->cpu];
 856         int ratio, freq;
 857
 858         ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
 859         if (ratio <= 0) {
 860                 u64 cap;
 861
 862                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 863                 ratio = HWP_GUARANTEED_PERF(cap);
 864         }
 865
 866         freq = ratio * cpu->pstate.scaling;
 867         if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
 868                 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
 869
 870         return sprintf(buf, "%d\n", freq);
 871 }
 872
 873 cpufreq_freq_attr_ro(base_frequency);
 874
 875 static struct freq_attr *hwp_cpufreq_attrs[] = {
 876         &energy_performance_preference,
 877         &energy_performance_available_preferences,
 878         &base_frequency,
 879         NULL,
 880 };
 881
 882 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
 883 {
 884         u64 cap;
 885
 886         rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
 887         WRITE_ONCE(cpu->hwp_cap_cached, cap);
 888         cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
 889         cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
 890 }
 891
 892 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
 893 {
 894         int scaling = cpu->pstate.scaling;
 895
 896         __intel_pstate_get_hwp_cap(cpu);
 897
 898         cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
 899         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
 900         if (scaling != cpu->pstate.perf_ctl_scaling) {
 901                 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 902
 903                 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
 904                                                  perf_ctl_scaling);
 905                 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
 906                                                    perf_ctl_scaling);
 907         }
 908 }
 909
 910 static void intel_pstate_hwp_set(unsigned int cpu)
 911 {
 912         struct cpudata *cpu_data = all_cpu_data[cpu];
 913         int max, min;
 914         u64 value;
 915         s16 epp;
 916
 917         max = cpu_data->max_perf_ratio;
 918         min = cpu_data->min_perf_ratio;
 919
 920         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 921                 min = max;
 922
 923         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 924
 925         value &= ~HWP_MIN_PERF(~0L);
 926         value |= HWP_MIN_PERF(min);
 927
 928         value &= ~HWP_MAX_PERF(~0L);
 929         value |= HWP_MAX_PERF(max);
 930
 931         if (cpu_data->epp_policy == cpu_data->policy)
 932                 goto skip_epp;
 933
 934         cpu_data->epp_policy = cpu_data->policy;
 935
 936         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 937                 epp = intel_pstate_get_epp(cpu_data, value);
 938                 cpu_data->epp_powersave = epp;
 939                 /* If EPP read was failed, then don't try to write */
 940                 if (epp < 0)
 941                         goto skip_epp;
 942
 943                 epp = 0;
 944         } else {
 945                 /* skip setting EPP, when saved value is invalid */
 946                 if (cpu_data->epp_powersave < 0)
 947                         goto skip_epp;
 948
 949                 /*
 950                  * No need to restore EPP when it is not zero. This
 951                  * means:
 952                  *  - Policy is not changed
 953                  *  - user has manually changed
 954                  *  - Error reading EPB
 955                  */
 956                 epp = intel_pstate_get_epp(cpu_data, value);
 957                 if (epp)
 958                         goto skip_epp;
 959
 960                 epp = cpu_data->epp_powersave;
 961         }
 962         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 963                 value &= ~GENMASK_ULL(31, 24);
 964                 value |= (u64)epp << 24;
 965         } else {
 966                 intel_pstate_set_epb(cpu, epp);
 967         }
 968 skip_epp:
 969         WRITE_ONCE(cpu_data->hwp_req_cached, value);
 970         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 971 }
 972
 973 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
 974
 975 static void intel_pstate_hwp_offline(struct cpudata *cpu)
 976 {
 977         u64 value = READ_ONCE(cpu->hwp_req_cached);
 978         int min_perf;
 979
 980         intel_pstate_disable_hwp_interrupt(cpu);
 981
 982         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 983                 /*
 984                  * In case the EPP has been set to "performance" by the
 985                  * active mode "performance" scaling algorithm, replace that
 986                  * temporary value with the cached EPP one.
 987                  */
 988                 value &= ~GENMASK_ULL(31, 24);
 989                 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
 990                 /*
 991                  * However, make sure that EPP will be set to "performance" when
 992                  * the CPU is brought back online again and the "performance"
 993                  * scaling algorithm is still in effect.
 994                  */
 995                 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
 996         }
 997
 998         /*
 999          * Clear the desired perf field in the cached HWP request value to
1000          * prevent nonzero desired values from being leaked into the active
1001          * mode.
1002          */
1003         value &= ~HWP_DESIRED_PERF(~0L);
1004         WRITE_ONCE(cpu->hwp_req_cached, value);
1005
1006         value &= ~GENMASK_ULL(31, 0);
1007         min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1008
1009         /* Set hwp_max = hwp_min */
1010         value |= HWP_MAX_PERF(min_perf);
1011         value |= HWP_MIN_PERF(min_perf);
1012
1013         /* Set EPP to min */
1014         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1015                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1016
1017         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1018 }
1019
1020 #define POWER_CTL_EE_ENABLE     1
1021 #define POWER_CTL_EE_DISABLE    2
1022
1023 static int power_ctl_ee_state;
1024
1025 static void set_power_ctl_ee_state(bool input)
1026 {
1027         u64 power_ctl;
1028
1029         mutex_lock(&intel_pstate_driver_lock);
1030         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1031         if (input) {
1032                 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1033                 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1034         } else {
1035                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1036                 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1037         }
1038         wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1039         mutex_unlock(&intel_pstate_driver_lock);
1040 }
1041
1042 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1043
1044 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1045 {
1046         intel_pstate_hwp_enable(cpu);
1047         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1048 }
1049
1050 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1051 {
1052         struct cpudata *cpu = all_cpu_data[policy->cpu];
1053
1054         pr_debug("CPU %d suspending\n", cpu->cpu);
1055
1056         cpu->suspended = true;
1057
1058         /* disable HWP interrupt and cancel any pending work */
1059         intel_pstate_disable_hwp_interrupt(cpu);
1060
1061         return 0;
1062 }
1063
1064 static int intel_pstate_resume(struct cpufreq_policy *policy)
1065 {
1066         struct cpudata *cpu = all_cpu_data[policy->cpu];
1067
1068         pr_debug("CPU %d resuming\n", cpu->cpu);
1069
1070         /* Only restore if the system default is changed */
1071         if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1072                 set_power_ctl_ee_state(true);
1073         else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1074                 set_power_ctl_ee_state(false);
1075
1076         if (cpu->suspended && hwp_active) {
1077                 mutex_lock(&intel_pstate_limits_lock);
1078
1079                 /* Re-enable HWP, because "online" has not done that. */
1080                 intel_pstate_hwp_reenable(cpu);
1081
1082                 mutex_unlock(&intel_pstate_limits_lock);
1083         }
1084
1085         cpu->suspended = false;
1086
1087         return 0;
1088 }
1089
1090 static void intel_pstate_update_policies(void)
1091 {
1092         int cpu;
1093
1094         for_each_possible_cpu(cpu)
1095                 cpufreq_update_policy(cpu);
1096 }
1097
1098 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1099                                            struct cpufreq_policy *policy)
1100 {
1101         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1102                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1103         refresh_frequency_limits(policy);
1104 }
1105
1106 static void intel_pstate_update_max_freq(unsigned int cpu)
1107 {
1108         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1109
1110         if (!policy)
1111                 return;
1112
1113         __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1114
1115         cpufreq_cpu_release(policy);
1116 }
1117
1118 static void intel_pstate_update_limits(unsigned int cpu)
1119 {
1120         mutex_lock(&intel_pstate_driver_lock);
1121
1122         update_turbo_state();
1123         /*
1124          * If turbo has been turned on or off globally, policy limits for
1125          * all CPUs need to be updated to reflect that.
1126          */
1127         if (global.turbo_disabled_mf != global.turbo_disabled) {
1128                 global.turbo_disabled_mf = global.turbo_disabled;
1129                 arch_set_max_freq_ratio(global.turbo_disabled);
1130                 for_each_possible_cpu(cpu)
1131                         intel_pstate_update_max_freq(cpu);
1132         } else {
1133                 cpufreq_update_policy(cpu);
1134         }
1135
1136         mutex_unlock(&intel_pstate_driver_lock);
1137 }
1138
1139 /************************** sysfs begin ************************/
1140 #define show_one(file_name, object)                                     \
1141         static ssize_t show_##file_name                                 \
1142         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
1143         {                                                               \
1144                 return sprintf(buf, "%u\n", global.object);             \
1145         }
1146
1147 static ssize_t intel_pstate_show_status(char *buf);
1148 static int intel_pstate_update_status(const char *buf, size_t size);
1149
1150 static ssize_t show_status(struct kobject *kobj,
1151                            struct kobj_attribute *attr, char *buf)
1152 {
1153         ssize_t ret;
1154
1155         mutex_lock(&intel_pstate_driver_lock);
1156         ret = intel_pstate_show_status(buf);
1157         mutex_unlock(&intel_pstate_driver_lock);
1158
1159         return ret;
1160 }
1161
1162 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1163                             const char *buf, size_t count)
1164 {
1165         char *p = memchr(buf, '\n', count);
1166         int ret;
1167
1168         mutex_lock(&intel_pstate_driver_lock);
1169         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1170         mutex_unlock(&intel_pstate_driver_lock);
1171
1172         return ret < 0 ? ret : count;
1173 }
1174
1175 static ssize_t show_turbo_pct(struct kobject *kobj,
1176                                 struct kobj_attribute *attr, char *buf)
1177 {
1178         struct cpudata *cpu;
1179         int total, no_turbo, turbo_pct;
1180         uint32_t turbo_fp;
1181
1182         mutex_lock(&intel_pstate_driver_lock);
1183
1184         if (!intel_pstate_driver) {
1185                 mutex_unlock(&intel_pstate_driver_lock);
1186                 return -EAGAIN;
1187         }
1188
1189         cpu = all_cpu_data[0];
1190
1191         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1192         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1193         turbo_fp = div_fp(no_turbo, total);
1194         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1195
1196         mutex_unlock(&intel_pstate_driver_lock);
1197
1198         return sprintf(buf, "%u\n", turbo_pct);
1199 }
1200
1201 static ssize_t show_num_pstates(struct kobject *kobj,
1202                                 struct kobj_attribute *attr, char *buf)
1203 {
1204         struct cpudata *cpu;
1205         int total;
1206
1207         mutex_lock(&intel_pstate_driver_lock);
1208
1209         if (!intel_pstate_driver) {
1210                 mutex_unlock(&intel_pstate_driver_lock);
1211                 return -EAGAIN;
1212         }
1213
1214         cpu = all_cpu_data[0];
1215         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1216
1217         mutex_unlock(&intel_pstate_driver_lock);
1218
1219         return sprintf(buf, "%u\n", total);
1220 }
1221
1222 static ssize_t show_no_turbo(struct kobject *kobj,
1223                              struct kobj_attribute *attr, char *buf)
1224 {
1225         ssize_t ret;
1226
1227         mutex_lock(&intel_pstate_driver_lock);
1228
1229         if (!intel_pstate_driver) {
1230                 mutex_unlock(&intel_pstate_driver_lock);
1231                 return -EAGAIN;
1232         }
1233
1234         update_turbo_state();
1235         if (global.turbo_disabled)
1236                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1237         else
1238                 ret = sprintf(buf, "%u\n", global.no_turbo);
1239
1240         mutex_unlock(&intel_pstate_driver_lock);
1241
1242         return ret;
1243 }
1244
1245 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1246                               const char *buf, size_t count)
1247 {
1248         unsigned int input;
1249         int ret;
1250
1251         ret = sscanf(buf, "%u", &input);
1252         if (ret != 1)
1253                 return -EINVAL;
1254
1255         mutex_lock(&intel_pstate_driver_lock);
1256
1257         if (!intel_pstate_driver) {
1258                 mutex_unlock(&intel_pstate_driver_lock);
1259                 return -EAGAIN;
1260         }
1261
1262         mutex_lock(&intel_pstate_limits_lock);
1263
1264         update_turbo_state();
1265         if (global.turbo_disabled) {
1266                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1267                 mutex_unlock(&intel_pstate_limits_lock);
1268                 mutex_unlock(&intel_pstate_driver_lock);
1269                 return -EPERM;
1270         }
1271
1272         global.no_turbo = clamp_t(int, input, 0, 1);
1273
1274         if (global.no_turbo) {
1275                 struct cpudata *cpu = all_cpu_data[0];
1276                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1277
1278                 /* Squash the global minimum into the permitted range. */
1279                 if (global.min_perf_pct > pct)
1280                         global.min_perf_pct = pct;
1281         }
1282
1283         mutex_unlock(&intel_pstate_limits_lock);
1284
1285         intel_pstate_update_policies();
1286         arch_set_max_freq_ratio(global.no_turbo);
1287
1288         mutex_unlock(&intel_pstate_driver_lock);
1289
1290         return count;
1291 }
1292
1293 static void update_qos_request(enum freq_qos_req_type type)
1294 {
1295         struct freq_qos_request *req;
1296         struct cpufreq_policy *policy;
1297         int i;
1298
1299         for_each_possible_cpu(i) {
1300                 struct cpudata *cpu = all_cpu_data[i];
1301                 unsigned int freq, perf_pct;
1302
1303                 policy = cpufreq_cpu_get(i);
1304                 if (!policy)
1305                         continue;
1306
1307                 req = policy->driver_data;
1308                 cpufreq_cpu_put(policy);
1309
1310                 if (!req)
1311                         continue;
1312
1313                 if (hwp_active)
1314                         intel_pstate_get_hwp_cap(cpu);
1315
1316                 if (type == FREQ_QOS_MIN) {
1317                         perf_pct = global.min_perf_pct;
1318                 } else {
1319                         req++;
1320                         perf_pct = global.max_perf_pct;
1321                 }
1322
1323                 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1324
1325                 if (freq_qos_update_request(req, freq) < 0)
1326                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1327         }
1328 }
1329
1330 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1331                                   const char *buf, size_t count)
1332 {
1333         unsigned int input;
1334         int ret;
1335
1336         ret = sscanf(buf, "%u", &input);
1337         if (ret != 1)
1338                 return -EINVAL;
1339
1340         mutex_lock(&intel_pstate_driver_lock);
1341
1342         if (!intel_pstate_driver) {
1343                 mutex_unlock(&intel_pstate_driver_lock);
1344                 return -EAGAIN;
1345         }
1346
1347         mutex_lock(&intel_pstate_limits_lock);
1348
1349         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1350
1351         mutex_unlock(&intel_pstate_limits_lock);
1352
1353         if (intel_pstate_driver == &intel_pstate)
1354                 intel_pstate_update_policies();
1355         else
1356                 update_qos_request(FREQ_QOS_MAX);
1357
1358         mutex_unlock(&intel_pstate_driver_lock);
1359
1360         return count;
1361 }
1362
1363 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1364                                   const char *buf, size_t count)
1365 {
1366         unsigned int input;
1367         int ret;
1368
1369         ret = sscanf(buf, "%u", &input);
1370         if (ret != 1)
1371                 return -EINVAL;
1372
1373         mutex_lock(&intel_pstate_driver_lock);
1374
1375         if (!intel_pstate_driver) {
1376                 mutex_unlock(&intel_pstate_driver_lock);
1377                 return -EAGAIN;
1378         }
1379
1380         mutex_lock(&intel_pstate_limits_lock);
1381
1382         global.min_perf_pct = clamp_t(int, input,
1383                                       min_perf_pct_min(), global.max_perf_pct);
1384
1385         mutex_unlock(&intel_pstate_limits_lock);
1386
1387         if (intel_pstate_driver == &intel_pstate)
1388                 intel_pstate_update_policies();
1389         else
1390                 update_qos_request(FREQ_QOS_MIN);
1391
1392         mutex_unlock(&intel_pstate_driver_lock);
1393
1394         return count;
1395 }
1396
1397 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1398                                 struct kobj_attribute *attr, char *buf)
1399 {
1400         return sprintf(buf, "%u\n", hwp_boost);
1401 }
1402
1403 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1404                                        struct kobj_attribute *b,
1405                                        const char *buf, size_t count)
1406 {
1407         unsigned int input;
1408         int ret;
1409
1410         ret = kstrtouint(buf, 10, &input);
1411         if (ret)
1412                 return ret;
1413
1414         mutex_lock(&intel_pstate_driver_lock);
1415         hwp_boost = !!input;
1416         intel_pstate_update_policies();
1417         mutex_unlock(&intel_pstate_driver_lock);
1418
1419         return count;
1420 }
1421
1422 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1423                                       char *buf)
1424 {
1425         u64 power_ctl;
1426         int enable;
1427
1428         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1429         enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1430         return sprintf(buf, "%d\n", !enable);
1431 }
1432
1433 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1434                                        const char *buf, size_t count)
1435 {
1436         bool input;
1437         int ret;
1438
1439         ret = kstrtobool(buf, &input);
1440         if (ret)
1441                 return ret;
1442
1443         set_power_ctl_ee_state(input);
1444
1445         return count;
1446 }
1447
1448 show_one(max_perf_pct, max_perf_pct);
1449 show_one(min_perf_pct, min_perf_pct);
1450
1451 define_one_global_rw(status);
1452 define_one_global_rw(no_turbo);
1453 define_one_global_rw(max_perf_pct);
1454 define_one_global_rw(min_perf_pct);
1455 define_one_global_ro(turbo_pct);
1456 define_one_global_ro(num_pstates);
1457 define_one_global_rw(hwp_dynamic_boost);
1458 define_one_global_rw(energy_efficiency);
1459
1460 static struct attribute *intel_pstate_attributes[] = {
1461         &status.attr,
1462         &no_turbo.attr,
1463         NULL
1464 };
1465
1466 static const struct attribute_group intel_pstate_attr_group = {
1467         .attrs = intel_pstate_attributes,
1468 };
1469
1470 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1471
1472 static struct kobject *intel_pstate_kobject;
1473
1474 static void __init intel_pstate_sysfs_expose_params(void)
1475 {
1476         struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1477         int rc;
1478
1479         if (dev_root) {
1480                 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1481                 put_device(dev_root);
1482         }
1483         if (WARN_ON(!intel_pstate_kobject))
1484                 return;
1485
1486         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1487         if (WARN_ON(rc))
1488                 return;
1489
1490         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1491                 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1492                 WARN_ON(rc);
1493
1494                 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1495                 WARN_ON(rc);
1496         }
1497
1498         /*
1499          * If per cpu limits are enforced there are no global limits, so
1500          * return without creating max/min_perf_pct attributes
1501          */
1502         if (per_cpu_limits)
1503                 return;
1504
1505         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1506         WARN_ON(rc);
1507
1508         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1509         WARN_ON(rc);
1510
1511         if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1512                 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1513                 WARN_ON(rc);
1514         }
1515 }
1516
1517 static void __init intel_pstate_sysfs_remove(void)
1518 {
1519         if (!intel_pstate_kobject)
1520                 return;
1521
1522         sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1523
1524         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1525                 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1526                 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1527         }
1528
1529         if (!per_cpu_limits) {
1530                 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1531                 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1532
1533                 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1534                         sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1535         }
1536
1537         kobject_put(intel_pstate_kobject);
1538 }
1539
1540 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1541 {
1542         int rc;
1543
1544         if (!hwp_active)
1545                 return;
1546
1547         rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1548         WARN_ON_ONCE(rc);
1549 }
1550
1551 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1552 {
1553         if (!hwp_active)
1554                 return;
1555
1556         sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1557 }
1558
1559 /************************** sysfs end ************************/
1560
1561 static void intel_pstate_notify_work(struct work_struct *work)
1562 {
1563         struct cpudata *cpudata =
1564                 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1565         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1566
1567         if (policy) {
1568                 intel_pstate_get_hwp_cap(cpudata);
1569                 __intel_pstate_update_max_freq(cpudata, policy);
1570
1571                 cpufreq_cpu_release(policy);
1572         }
1573
1574         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1575 }
1576
1577 static DEFINE_SPINLOCK(hwp_notify_lock);
1578 static cpumask_t hwp_intr_enable_mask;
1579
1580 void notify_hwp_interrupt(void)
1581 {
1582         unsigned int this_cpu = smp_processor_id();
1583         struct cpudata *cpudata;
1584         unsigned long flags;
1585         u64 value;
1586
1587         if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1588                 return;
1589
1590         rdmsrl_safe(MSR_HWP_STATUS, &value);
1591         if (!(value & 0x01))
1592                 return;
1593
1594         spin_lock_irqsave(&hwp_notify_lock, flags);
1595
1596         if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1597                 goto ack_intr;
1598
1599         /*
1600          * Currently we never free all_cpu_data. And we can't reach here
1601          * without this allocated. But for safety for future changes, added
1602          * check.
1603          */
1604         if (unlikely(!READ_ONCE(all_cpu_data)))
1605                 goto ack_intr;
1606
1607         /*
1608          * The free is done during cleanup, when cpufreq registry is failed.
1609          * We wouldn't be here if it fails on init or switch status. But for
1610          * future changes, added check.
1611          */
1612         cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1613         if (unlikely(!cpudata))
1614                 goto ack_intr;
1615
1616         schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1617
1618         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1619
1620         return;
1621
1622 ack_intr:
1623         wrmsrl_safe(MSR_HWP_STATUS, 0);
1624         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1625 }
1626
1627 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1628 {
1629         unsigned long flags;
1630
1631         if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1632                 return;
1633
1634         /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1635         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1636
1637         spin_lock_irqsave(&hwp_notify_lock, flags);
1638         if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1639                 cancel_delayed_work(&cpudata->hwp_notify_work);
1640         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1641 }
1642
1643 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1644 {
1645         /* Enable HWP notification interrupt for guaranteed performance change */
1646         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1647                 unsigned long flags;
1648
1649                 spin_lock_irqsave(&hwp_notify_lock, flags);
1650                 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1651                 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1652                 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1653
1654                 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1655                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1656                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1657         }
1658 }
1659
1660 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1661 {
1662         cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1663
1664         /*
1665          * If this CPU gen doesn't call for change in balance_perf
1666          * EPP return.
1667          */
1668         if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1669                 return;
1670
1671         /*
1672          * If the EPP is set by firmware, which means that firmware enabled HWP
1673          * - Is equal or less than 0x80 (default balance_perf EPP)
1674          * - But less performance oriented than performance EPP
1675          *   then use this as new balance_perf EPP.
1676          */
1677         if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1678             cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1679                 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1680                 return;
1681         }
1682
1683         /*
1684          * Use hard coded value per gen to update the balance_perf
1685          * and default EPP.
1686          */
1687         cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1688         intel_pstate_set_epp(cpudata, cpudata->epp_default);
1689 }
1690
1691 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1692 {
1693         /* First disable HWP notification interrupt till we activate again */
1694         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1695                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1696
1697         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1698
1699         intel_pstate_enable_hwp_interrupt(cpudata);
1700
1701         if (cpudata->epp_default >= 0)
1702                 return;
1703
1704         intel_pstate_update_epp_defaults(cpudata);
1705 }
1706
1707 static int atom_get_min_pstate(int not_used)
1708 {
1709         u64 value;
1710
1711         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1712         return (value >> 8) & 0x7F;
1713 }
1714
1715 static int atom_get_max_pstate(int not_used)
1716 {
1717         u64 value;
1718
1719         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1720         return (value >> 16) & 0x7F;
1721 }
1722
1723 static int atom_get_turbo_pstate(int not_used)
1724 {
1725         u64 value;
1726
1727         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1728         return value & 0x7F;
1729 }
1730
1731 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1732 {
1733         u64 val;
1734         int32_t vid_fp;
1735         u32 vid;
1736
1737         val = (u64)pstate << 8;
1738         if (global.no_turbo && !global.turbo_disabled)
1739                 val |= (u64)1 << 32;
1740
1741         vid_fp = cpudata->vid.min + mul_fp(
1742                 int_tofp(pstate - cpudata->pstate.min_pstate),
1743                 cpudata->vid.ratio);
1744
1745         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1746         vid = ceiling_fp(vid_fp);
1747
1748         if (pstate > cpudata->pstate.max_pstate)
1749                 vid = cpudata->vid.turbo;
1750
1751         return val | vid;
1752 }
1753
1754 static int silvermont_get_scaling(void)
1755 {
1756         u64 value;
1757         int i;
1758         /* Defined in Table 35-6 from SDM (Sept 2015) */
1759         static int silvermont_freq_table[] = {
1760                 83300, 100000, 133300, 116700, 80000};
1761
1762         rdmsrl(MSR_FSB_FREQ, value);
1763         i = value & 0x7;
1764         WARN_ON(i > 4);
1765
1766         return silvermont_freq_table[i];
1767 }
1768
1769 static int airmont_get_scaling(void)
1770 {
1771         u64 value;
1772         int i;
1773         /* Defined in Table 35-10 from SDM (Sept 2015) */
1774         static int airmont_freq_table[] = {
1775                 83300, 100000, 133300, 116700, 80000,
1776                 93300, 90000, 88900, 87500};
1777
1778         rdmsrl(MSR_FSB_FREQ, value);
1779         i = value & 0xF;
1780         WARN_ON(i > 8);
1781
1782         return airmont_freq_table[i];
1783 }
1784
1785 static void atom_get_vid(struct cpudata *cpudata)
1786 {
1787         u64 value;
1788
1789         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1790         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1791         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1792         cpudata->vid.ratio = div_fp(
1793                 cpudata->vid.max - cpudata->vid.min,
1794                 int_tofp(cpudata->pstate.max_pstate -
1795                         cpudata->pstate.min_pstate));
1796
1797         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1798         cpudata->vid.turbo = value & 0x7f;
1799 }
1800
1801 static int core_get_min_pstate(int cpu)
1802 {
1803         u64 value;
1804
1805         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1806         return (value >> 40) & 0xFF;
1807 }
1808
1809 static int core_get_max_pstate_physical(int cpu)
1810 {
1811         u64 value;
1812
1813         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1814         return (value >> 8) & 0xFF;
1815 }
1816
1817 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1818 {
1819         /* Check how many TDP levels present */
1820         if (plat_info & 0x600000000) {
1821                 u64 tdp_ctrl;
1822                 u64 tdp_ratio;
1823                 int tdp_msr;
1824                 int err;
1825
1826                 /* Get the TDP level (0, 1, 2) to get ratios */
1827                 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1828                 if (err)
1829                         return err;
1830
1831                 /* TDP MSR are continuous starting at 0x648 */
1832                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1833                 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1834                 if (err)
1835                         return err;
1836
1837                 /* For level 1 and 2, bits[23:16] contain the ratio */
1838                 if (tdp_ctrl & 0x03)
1839                         tdp_ratio >>= 16;
1840
1841                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1842                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1843
1844                 return (int)tdp_ratio;
1845         }
1846
1847         return -ENXIO;
1848 }
1849
1850 static int core_get_max_pstate(int cpu)
1851 {
1852         u64 tar;
1853         u64 plat_info;
1854         int max_pstate;
1855         int tdp_ratio;
1856         int err;
1857
1858         rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1859         max_pstate = (plat_info >> 8) & 0xFF;
1860
1861         tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1862         if (tdp_ratio <= 0)
1863                 return max_pstate;
1864
1865         if (hwp_active) {
1866                 /* Turbo activation ratio is not used on HWP platforms */
1867                 return tdp_ratio;
1868         }
1869
1870         err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1871         if (!err) {
1872                 int tar_levels;
1873
1874                 /* Do some sanity checking for safety */
1875                 tar_levels = tar & 0xff;
1876                 if (tdp_ratio - 1 == tar_levels) {
1877                         max_pstate = tar_levels;
1878                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1879                 }
1880         }
1881
1882         return max_pstate;
1883 }
1884
1885 static int core_get_turbo_pstate(int cpu)
1886 {
1887         u64 value;
1888         int nont, ret;
1889
1890         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1891         nont = core_get_max_pstate(cpu);
1892         ret = (value) & 255;
1893         if (ret <= nont)
1894                 ret = nont;
1895         return ret;
1896 }
1897
1898 static inline int core_get_scaling(void)
1899 {
1900         return 100000;
1901 }
1902
1903 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1904 {
1905         u64 val;
1906
1907         val = (u64)pstate << 8;
1908         if (global.no_turbo && !global.turbo_disabled)
1909                 val |= (u64)1 << 32;
1910
1911         return val;
1912 }
1913
1914 static int knl_get_aperf_mperf_shift(void)
1915 {
1916         return 10;
1917 }
1918
1919 static int knl_get_turbo_pstate(int cpu)
1920 {
1921         u64 value;
1922         int nont, ret;
1923
1924         rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1925         nont = core_get_max_pstate(cpu);
1926         ret = (((value) >> 8) & 0xFF);
1927         if (ret <= nont)
1928                 ret = nont;
1929         return ret;
1930 }
1931
1932 static void hybrid_get_type(void *data)
1933 {
1934         u8 *cpu_type = data;
1935
1936         *cpu_type = get_this_hybrid_cpu_type();
1937 }
1938
1939 static int hybrid_get_cpu_scaling(int cpu)
1940 {
1941         u8 cpu_type = 0;
1942
1943         smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1944         /* P-cores have a smaller perf level-to-freqency scaling factor. */
1945         if (cpu_type == 0x40)
1946                 return 78741;
1947
1948         return core_get_scaling();
1949 }
1950
1951 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1952 {
1953         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1954         cpu->pstate.current_pstate = pstate;
1955         /*
1956          * Generally, there is no guarantee that this code will always run on
1957          * the CPU being updated, so force the register update to run on the
1958          * right CPU.
1959          */
1960         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1961                       pstate_funcs.get_val(cpu, pstate));
1962 }
1963
1964 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1965 {
1966         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1967 }
1968
1969 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1970 {
1971         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1972
1973         update_turbo_state();
1974         intel_pstate_set_pstate(cpu, pstate);
1975 }
1976
1977 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1978 {
1979         int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
1980         int perf_ctl_scaling = pstate_funcs.get_scaling();
1981
1982         cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
1983         cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
1984         cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
1985
1986         if (hwp_active && !hwp_mode_bdw) {
1987                 __intel_pstate_get_hwp_cap(cpu);
1988
1989                 if (pstate_funcs.get_cpu_scaling) {
1990                         cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
1991                         if (cpu->pstate.scaling != perf_ctl_scaling)
1992                                 intel_pstate_hybrid_hwp_adjust(cpu);
1993                 } else {
1994                         cpu->pstate.scaling = perf_ctl_scaling;
1995                 }
1996         } else {
1997                 cpu->pstate.scaling = perf_ctl_scaling;
1998                 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
1999                 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2000         }
2001
2002         if (cpu->pstate.scaling == perf_ctl_scaling) {
2003                 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2004                 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2005                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2006         }
2007
2008         if (pstate_funcs.get_aperf_mperf_shift)
2009                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2010
2011         if (pstate_funcs.get_vid)
2012                 pstate_funcs.get_vid(cpu);
2013
2014         intel_pstate_set_min_pstate(cpu);
2015 }
2016
2017 /*
2018  * Long hold time will keep high perf limits for long time,
2019  * which negatively impacts perf/watt for some workloads,
2020  * like specpower. 3ms is based on experiements on some
2021  * workoads.
2022  */
2023 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2024
2025 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2026 {
2027         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2028         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2029         u32 max_limit = (hwp_req & 0xff00) >> 8;
2030         u32 min_limit = (hwp_req & 0xff);
2031         u32 boost_level1;
2032
2033         /*
2034          * Cases to consider (User changes via sysfs or boot time):
2035          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2036          *      No boost, return.
2037          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2038          *     Should result in one level boost only for P0.
2039          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2040          *     Should result in two level boost:
2041          *         (min + p1)/2 and P1.
2042          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2043          *     Should result in three level boost:
2044          *        (min + p1)/2, P1 and P0.
2045          */
2046
2047         /* If max and min are equal or already at max, nothing to boost */
2048         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2049                 return;
2050
2051         if (!cpu->hwp_boost_min)
2052                 cpu->hwp_boost_min = min_limit;
2053
2054         /* level at half way mark between min and guranteed */
2055         boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2056
2057         if (cpu->hwp_boost_min < boost_level1)
2058                 cpu->hwp_boost_min = boost_level1;
2059         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2060                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2061         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2062                  max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2063                 cpu->hwp_boost_min = max_limit;
2064         else
2065                 return;
2066
2067         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2068         wrmsrl(MSR_HWP_REQUEST, hwp_req);
2069         cpu->last_update = cpu->sample.time;
2070 }
2071
2072 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2073 {
2074         if (cpu->hwp_boost_min) {
2075                 bool expired;
2076
2077                 /* Check if we are idle for hold time to boost down */
2078                 expired = time_after64(cpu->sample.time, cpu->last_update +
2079                                        hwp_boost_hold_time_ns);
2080                 if (expired) {
2081                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2082                         cpu->hwp_boost_min = 0;
2083                 }
2084         }
2085         cpu->last_update = cpu->sample.time;
2086 }
2087
2088 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2089                                                       u64 time)
2090 {
2091         cpu->sample.time = time;
2092
2093         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2094                 bool do_io = false;
2095
2096                 cpu->sched_flags = 0;
2097                 /*
2098                  * Set iowait_boost flag and update time. Since IO WAIT flag
2099                  * is set all the time, we can't just conclude that there is
2100                  * some IO bound activity is scheduled on this CPU with just
2101                  * one occurrence. If we receive at least two in two
2102                  * consecutive ticks, then we treat as boost candidate.
2103                  */
2104                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2105                         do_io = true;
2106
2107                 cpu->last_io_update = time;
2108
2109                 if (do_io)
2110                         intel_pstate_hwp_boost_up(cpu);
2111
2112         } else {
2113                 intel_pstate_hwp_boost_down(cpu);
2114         }
2115 }
2116
2117 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2118                                                 u64 time, unsigned int flags)
2119 {
2120         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2121
2122         cpu->sched_flags |= flags;
2123
2124         if (smp_processor_id() == cpu->cpu)
2125                 intel_pstate_update_util_hwp_local(cpu, time);
2126 }
2127
2128 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2129 {
2130         struct sample *sample = &cpu->sample;
2131
2132         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2133 }
2134
2135 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2136 {
2137         u64 aperf, mperf;
2138         unsigned long flags;
2139         u64 tsc;
2140
2141         local_irq_save(flags);
2142         rdmsrl(MSR_IA32_APERF, aperf);
2143         rdmsrl(MSR_IA32_MPERF, mperf);
2144         tsc = rdtsc();
2145         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2146                 local_irq_restore(flags);
2147                 return false;
2148         }
2149         local_irq_restore(flags);
2150
2151         cpu->last_sample_time = cpu->sample.time;
2152         cpu->sample.time = time;
2153         cpu->sample.aperf = aperf;
2154         cpu->sample.mperf = mperf;
2155         cpu->sample.tsc =  tsc;
2156         cpu->sample.aperf -= cpu->prev_aperf;
2157         cpu->sample.mperf -= cpu->prev_mperf;
2158         cpu->sample.tsc -= cpu->prev_tsc;
2159
2160         cpu->prev_aperf = aperf;
2161         cpu->prev_mperf = mperf;
2162         cpu->prev_tsc = tsc;
2163         /*
2164          * First time this function is invoked in a given cycle, all of the
2165          * previous sample data fields are equal to zero or stale and they must
2166          * be populated with meaningful numbers for things to work, so assume
2167          * that sample.time will always be reset before setting the utilization
2168          * update hook and make the caller skip the sample then.
2169          */
2170         if (cpu->last_sample_time) {
2171                 intel_pstate_calc_avg_perf(cpu);
2172                 return true;
2173         }
2174         return false;
2175 }
2176
2177 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2178 {
2179         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2180 }
2181
2182 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2183 {
2184         return mul_ext_fp(cpu->pstate.max_pstate_physical,
2185                           cpu->sample.core_avg_perf);
2186 }
2187
2188 static inline int32_t get_target_pstate(struct cpudata *cpu)
2189 {
2190         struct sample *sample = &cpu->sample;
2191         int32_t busy_frac;
2192         int target, avg_pstate;
2193
2194         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2195                            sample->tsc);
2196
2197         if (busy_frac < cpu->iowait_boost)
2198                 busy_frac = cpu->iowait_boost;
2199
2200         sample->busy_scaled = busy_frac * 100;
2201
2202         target = global.no_turbo || global.turbo_disabled ?
2203                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2204         target += target >> 2;
2205         target = mul_fp(target, busy_frac);
2206         if (target < cpu->pstate.min_pstate)
2207                 target = cpu->pstate.min_pstate;
2208
2209         /*
2210          * If the average P-state during the previous cycle was higher than the
2211          * current target, add 50% of the difference to the target to reduce
2212          * possible performance oscillations and offset possible performance
2213          * loss related to moving the workload from one CPU to another within
2214          * a package/module.
2215          */
2216         avg_pstate = get_avg_pstate(cpu);
2217         if (avg_pstate > target)
2218                 target += (avg_pstate - target) >> 1;
2219
2220         return target;
2221 }
2222
2223 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2224 {
2225         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2226         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2227
2228         return clamp_t(int, pstate, min_pstate, max_pstate);
2229 }
2230
2231 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2232 {
2233         if (pstate == cpu->pstate.current_pstate)
2234                 return;
2235
2236         cpu->pstate.current_pstate = pstate;
2237         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2238 }
2239
2240 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2241 {
2242         int from = cpu->pstate.current_pstate;
2243         struct sample *sample;
2244         int target_pstate;
2245
2246         update_turbo_state();
2247
2248         target_pstate = get_target_pstate(cpu);
2249         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2250         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2251         intel_pstate_update_pstate(cpu, target_pstate);
2252
2253         sample = &cpu->sample;
2254         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2255                 fp_toint(sample->busy_scaled),
2256                 from,
2257                 cpu->pstate.current_pstate,
2258                 sample->mperf,
2259                 sample->aperf,
2260                 sample->tsc,
2261                 get_avg_frequency(cpu),
2262                 fp_toint(cpu->iowait_boost * 100));
2263 }
2264
2265 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2266                                      unsigned int flags)
2267 {
2268         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2269         u64 delta_ns;
2270
2271         /* Don't allow remote callbacks */
2272         if (smp_processor_id() != cpu->cpu)
2273                 return;
2274
2275         delta_ns = time - cpu->last_update;
2276         if (flags & SCHED_CPUFREQ_IOWAIT) {
2277                 /* Start over if the CPU may have been idle. */
2278                 if (delta_ns > TICK_NSEC) {
2279                         cpu->iowait_boost = ONE_EIGHTH_FP;
2280                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2281                         cpu->iowait_boost <<= 1;
2282                         if (cpu->iowait_boost > int_tofp(1))
2283                                 cpu->iowait_boost = int_tofp(1);
2284                 } else {
2285                         cpu->iowait_boost = ONE_EIGHTH_FP;
2286                 }
2287         } else if (cpu->iowait_boost) {
2288                 /* Clear iowait_boost if the CPU may have been idle. */
2289                 if (delta_ns > TICK_NSEC)
2290                         cpu->iowait_boost = 0;
2291                 else
2292                         cpu->iowait_boost >>= 1;
2293         }
2294         cpu->last_update = time;
2295         delta_ns = time - cpu->sample.time;
2296         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2297                 return;
2298
2299         if (intel_pstate_sample(cpu, time))
2300                 intel_pstate_adjust_pstate(cpu);
2301 }
2302
2303 static struct pstate_funcs core_funcs = {
2304         .get_max = core_get_max_pstate,
2305         .get_max_physical = core_get_max_pstate_physical,
2306         .get_min = core_get_min_pstate,
2307         .get_turbo = core_get_turbo_pstate,
2308         .get_scaling = core_get_scaling,
2309         .get_val = core_get_val,
2310 };
2311
2312 static const struct pstate_funcs silvermont_funcs = {
2313         .get_max = atom_get_max_pstate,
2314         .get_max_physical = atom_get_max_pstate,
2315         .get_min = atom_get_min_pstate,
2316         .get_turbo = atom_get_turbo_pstate,
2317         .get_val = atom_get_val,
2318         .get_scaling = silvermont_get_scaling,
2319         .get_vid = atom_get_vid,
2320 };
2321
2322 static const struct pstate_funcs airmont_funcs = {
2323         .get_max = atom_get_max_pstate,
2324         .get_max_physical = atom_get_max_pstate,
2325         .get_min = atom_get_min_pstate,
2326         .get_turbo = atom_get_turbo_pstate,
2327         .get_val = atom_get_val,
2328         .get_scaling = airmont_get_scaling,
2329         .get_vid = atom_get_vid,
2330 };
2331
2332 static const struct pstate_funcs knl_funcs = {
2333         .get_max = core_get_max_pstate,
2334         .get_max_physical = core_get_max_pstate_physical,
2335         .get_min = core_get_min_pstate,
2336         .get_turbo = knl_get_turbo_pstate,
2337         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2338         .get_scaling = core_get_scaling,
2339         .get_val = core_get_val,
2340 };
2341
2342 #define X86_MATCH(model, policy)                                         \
2343         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2344                                            X86_FEATURE_APERFMPERF, &policy)
2345
2346 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2347         X86_MATCH(SANDYBRIDGE,          core_funcs),
2348         X86_MATCH(SANDYBRIDGE_X,        core_funcs),
2349         X86_MATCH(ATOM_SILVERMONT,      silvermont_funcs),
2350         X86_MATCH(IVYBRIDGE,            core_funcs),
2351         X86_MATCH(HASWELL,              core_funcs),
2352         X86_MATCH(BROADWELL,            core_funcs),
2353         X86_MATCH(IVYBRIDGE_X,          core_funcs),
2354         X86_MATCH(HASWELL_X,            core_funcs),
2355         X86_MATCH(HASWELL_L,            core_funcs),
2356         X86_MATCH(HASWELL_G,            core_funcs),
2357         X86_MATCH(BROADWELL_G,          core_funcs),
2358         X86_MATCH(ATOM_AIRMONT,         airmont_funcs),
2359         X86_MATCH(SKYLAKE_L,            core_funcs),
2360         X86_MATCH(BROADWELL_X,          core_funcs),
2361         X86_MATCH(SKYLAKE,              core_funcs),
2362         X86_MATCH(BROADWELL_D,          core_funcs),
2363         X86_MATCH(XEON_PHI_KNL,         knl_funcs),
2364         X86_MATCH(XEON_PHI_KNM,         knl_funcs),
2365         X86_MATCH(ATOM_GOLDMONT,        core_funcs),
2366         X86_MATCH(ATOM_GOLDMONT_PLUS,   core_funcs),
2367         X86_MATCH(SKYLAKE_X,            core_funcs),
2368         X86_MATCH(COMETLAKE,            core_funcs),
2369         X86_MATCH(ICELAKE_X,            core_funcs),
2370         X86_MATCH(TIGERLAKE,            core_funcs),
2371         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2372         {}
2373 };
2374 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2375
2376 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2377         X86_MATCH(BROADWELL_D,          core_funcs),
2378         X86_MATCH(BROADWELL_X,          core_funcs),
2379         X86_MATCH(SKYLAKE_X,            core_funcs),
2380         X86_MATCH(ICELAKE_X,            core_funcs),
2381         X86_MATCH(SAPPHIRERAPIDS_X,     core_funcs),
2382         {}
2383 };
2384
2385 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2386         X86_MATCH(KABYLAKE,             core_funcs),
2387         {}
2388 };
2389
2390 static int intel_pstate_init_cpu(unsigned int cpunum)
2391 {
2392         struct cpudata *cpu;
2393
2394         cpu = all_cpu_data[cpunum];
2395
2396         if (!cpu) {
2397                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2398                 if (!cpu)
2399                         return -ENOMEM;
2400
2401                 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2402
2403                 cpu->cpu = cpunum;
2404
2405                 cpu->epp_default = -EINVAL;
2406
2407                 if (hwp_active) {
2408                         intel_pstate_hwp_enable(cpu);
2409
2410                         if (intel_pstate_acpi_pm_profile_server())
2411                                 hwp_boost = true;
2412                 }
2413         } else if (hwp_active) {
2414                 /*
2415                  * Re-enable HWP in case this happens after a resume from ACPI
2416                  * S3 if the CPU was offline during the whole system/resume
2417                  * cycle.
2418                  */
2419                 intel_pstate_hwp_reenable(cpu);
2420         }
2421
2422         cpu->epp_powersave = -EINVAL;
2423         cpu->epp_policy = 0;
2424
2425         intel_pstate_get_cpu_pstates(cpu);
2426
2427         pr_debug("controlling: cpu %d\n", cpunum);
2428
2429         return 0;
2430 }
2431
2432 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2433 {
2434         struct cpudata *cpu = all_cpu_data[cpu_num];
2435
2436         if (hwp_active && !hwp_boost)
2437                 return;
2438
2439         if (cpu->update_util_set)
2440                 return;
2441
2442         /* Prevent intel_pstate_update_util() from using stale data. */
2443         cpu->sample.time = 0;
2444         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2445                                      (hwp_active ?
2446                                       intel_pstate_update_util_hwp :
2447                                       intel_pstate_update_util));
2448         cpu->update_util_set = true;
2449 }
2450
2451 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2452 {
2453         struct cpudata *cpu_data = all_cpu_data[cpu];
2454
2455         if (!cpu_data->update_util_set)
2456                 return;
2457
2458         cpufreq_remove_update_util_hook(cpu);
2459         cpu_data->update_util_set = false;
2460         synchronize_rcu();
2461 }
2462
2463 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2464 {
2465         return global.turbo_disabled || global.no_turbo ?
2466                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2467 }
2468
2469 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2470                                             unsigned int policy_min,
2471                                             unsigned int policy_max)
2472 {
2473         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2474         int32_t max_policy_perf, min_policy_perf;
2475
2476         max_policy_perf = policy_max / perf_ctl_scaling;
2477         if (policy_max == policy_min) {
2478                 min_policy_perf = max_policy_perf;
2479         } else {
2480                 min_policy_perf = policy_min / perf_ctl_scaling;
2481                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2482                                           0, max_policy_perf);
2483         }
2484
2485         /*
2486          * HWP needs some special consideration, because HWP_REQUEST uses
2487          * abstract values to represent performance rather than pure ratios.
2488          */
2489         if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2490                 int scaling = cpu->pstate.scaling;
2491                 int freq;
2492
2493                 freq = max_policy_perf * perf_ctl_scaling;
2494                 max_policy_perf = DIV_ROUND_UP(freq, scaling);
2495                 freq = min_policy_perf * perf_ctl_scaling;
2496                 min_policy_perf = DIV_ROUND_UP(freq, scaling);
2497         }
2498
2499         pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2500                  cpu->cpu, min_policy_perf, max_policy_perf);
2501
2502         /* Normalize user input to [min_perf, max_perf] */
2503         if (per_cpu_limits) {
2504                 cpu->min_perf_ratio = min_policy_perf;
2505                 cpu->max_perf_ratio = max_policy_perf;
2506         } else {
2507                 int turbo_max = cpu->pstate.turbo_pstate;
2508                 int32_t global_min, global_max;
2509
2510                 /* Global limits are in percent of the maximum turbo P-state. */
2511                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2512                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2513                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2514
2515                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2516                          global_min, global_max);
2517
2518                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2519                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2520                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2521                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2522
2523                 /* Make sure min_perf <= max_perf */
2524                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2525                                           cpu->max_perf_ratio);
2526
2527         }
2528         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2529                  cpu->max_perf_ratio,
2530                  cpu->min_perf_ratio);
2531 }
2532
2533 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2534 {
2535         struct cpudata *cpu;
2536
2537         if (!policy->cpuinfo.max_freq)
2538                 return -ENODEV;
2539
2540         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2541                  policy->cpuinfo.max_freq, policy->max);
2542
2543         cpu = all_cpu_data[policy->cpu];
2544         cpu->policy = policy->policy;
2545
2546         mutex_lock(&intel_pstate_limits_lock);
2547
2548         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2549
2550         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2551                 /*
2552                  * NOHZ_FULL CPUs need this as the governor callback may not
2553                  * be invoked on them.
2554                  */
2555                 intel_pstate_clear_update_util_hook(policy->cpu);
2556                 intel_pstate_max_within_limits(cpu);
2557         } else {
2558                 intel_pstate_set_update_util_hook(policy->cpu);
2559         }
2560
2561         if (hwp_active) {
2562                 /*
2563                  * When hwp_boost was active before and dynamically it
2564                  * was turned off, in that case we need to clear the
2565                  * update util hook.
2566                  */
2567                 if (!hwp_boost)
2568                         intel_pstate_clear_update_util_hook(policy->cpu);
2569                 intel_pstate_hwp_set(policy->cpu);
2570         }
2571
2572         mutex_unlock(&intel_pstate_limits_lock);
2573
2574         return 0;
2575 }
2576
2577 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2578                                            struct cpufreq_policy_data *policy)
2579 {
2580         if (!hwp_active &&
2581             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2582             policy->max < policy->cpuinfo.max_freq &&
2583             policy->max > cpu->pstate.max_freq) {
2584                 pr_debug("policy->max > max non turbo frequency\n");
2585                 policy->max = policy->cpuinfo.max_freq;
2586         }
2587 }
2588
2589 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2590                                            struct cpufreq_policy_data *policy)
2591 {
2592         int max_freq;
2593
2594         update_turbo_state();
2595         if (hwp_active) {
2596                 intel_pstate_get_hwp_cap(cpu);
2597                 max_freq = global.no_turbo || global.turbo_disabled ?
2598                                 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2599         } else {
2600                 max_freq = intel_pstate_get_max_freq(cpu);
2601         }
2602         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2603
2604         intel_pstate_adjust_policy_max(cpu, policy);
2605 }
2606
2607 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2608 {
2609         intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2610
2611         return 0;
2612 }
2613
2614 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2615 {
2616         struct cpudata *cpu = all_cpu_data[policy->cpu];
2617
2618         pr_debug("CPU %d going offline\n", cpu->cpu);
2619
2620         if (cpu->suspended)
2621                 return 0;
2622
2623         /*
2624          * If the CPU is an SMT thread and it goes offline with the performance
2625          * settings different from the minimum, it will prevent its sibling
2626          * from getting to lower performance levels, so force the minimum
2627          * performance on CPU offline to prevent that from happening.
2628          */
2629         if (hwp_active)
2630                 intel_pstate_hwp_offline(cpu);
2631         else
2632                 intel_pstate_set_min_pstate(cpu);
2633
2634         intel_pstate_exit_perf_limits(policy);
2635
2636         return 0;
2637 }
2638
2639 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2640 {
2641         struct cpudata *cpu = all_cpu_data[policy->cpu];
2642
2643         pr_debug("CPU %d going online\n", cpu->cpu);
2644
2645         intel_pstate_init_acpi_perf_limits(policy);
2646
2647         if (hwp_active) {
2648                 /*
2649                  * Re-enable HWP and clear the "suspended" flag to let "resume"
2650                  * know that it need not do that.
2651                  */
2652                 intel_pstate_hwp_reenable(cpu);
2653                 cpu->suspended = false;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2660 {
2661         intel_pstate_clear_update_util_hook(policy->cpu);
2662
2663         return intel_cpufreq_cpu_offline(policy);
2664 }
2665
2666 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2667 {
2668         pr_debug("CPU %d exiting\n", policy->cpu);
2669
2670         policy->fast_switch_possible = false;
2671
2672         return 0;
2673 }
2674
2675 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2676 {
2677         struct cpudata *cpu;
2678         int rc;
2679
2680         rc = intel_pstate_init_cpu(policy->cpu);
2681         if (rc)
2682                 return rc;
2683
2684         cpu = all_cpu_data[policy->cpu];
2685
2686         cpu->max_perf_ratio = 0xFF;
2687         cpu->min_perf_ratio = 0;
2688
2689         /* cpuinfo and default policy values */
2690         policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2691         update_turbo_state();
2692         global.turbo_disabled_mf = global.turbo_disabled;
2693         policy->cpuinfo.max_freq = global.turbo_disabled ?
2694                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2695
2696         policy->min = policy->cpuinfo.min_freq;
2697         policy->max = policy->cpuinfo.max_freq;
2698
2699         intel_pstate_init_acpi_perf_limits(policy);
2700
2701         policy->fast_switch_possible = true;
2702
2703         return 0;
2704 }
2705
2706 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2707 {
2708         int ret = __intel_pstate_cpu_init(policy);
2709
2710         if (ret)
2711                 return ret;
2712
2713         /*
2714          * Set the policy to powersave to provide a valid fallback value in case
2715          * the default cpufreq governor is neither powersave nor performance.
2716          */
2717         policy->policy = CPUFREQ_POLICY_POWERSAVE;
2718
2719         if (hwp_active) {
2720                 struct cpudata *cpu = all_cpu_data[policy->cpu];
2721
2722                 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2723         }
2724
2725         return 0;
2726 }
2727
2728 static struct cpufreq_driver intel_pstate = {
2729         .flags          = CPUFREQ_CONST_LOOPS,
2730         .verify         = intel_pstate_verify_policy,
2731         .setpolicy      = intel_pstate_set_policy,
2732         .suspend        = intel_pstate_suspend,
2733         .resume         = intel_pstate_resume,
2734         .init           = intel_pstate_cpu_init,
2735         .exit           = intel_pstate_cpu_exit,
2736         .offline        = intel_pstate_cpu_offline,
2737         .online         = intel_pstate_cpu_online,
2738         .update_limits  = intel_pstate_update_limits,
2739         .name           = "intel_pstate",
2740 };
2741
2742 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2743 {
2744         struct cpudata *cpu = all_cpu_data[policy->cpu];
2745
2746         intel_pstate_verify_cpu_policy(cpu, policy);
2747         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2748
2749         return 0;
2750 }
2751
2752 /* Use of trace in passive mode:
2753  *
2754  * In passive mode the trace core_busy field (also known as the
2755  * performance field, and lablelled as such on the graphs; also known as
2756  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2757  * driver call was via the normal or fast switch path. Various graphs
2758  * output from the intel_pstate_tracer.py utility that include core_busy
2759  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2760  * so we use 10 to indicate the normal path through the driver, and
2761  * 90 to indicate the fast switch path through the driver.
2762  * The scaled_busy field is not used, and is set to 0.
2763  */
2764
2765 #define INTEL_PSTATE_TRACE_TARGET 10
2766 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2767
2768 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2769 {
2770         struct sample *sample;
2771
2772         if (!trace_pstate_sample_enabled())
2773                 return;
2774
2775         if (!intel_pstate_sample(cpu, ktime_get()))
2776                 return;
2777
2778         sample = &cpu->sample;
2779         trace_pstate_sample(trace_type,
2780                 0,
2781                 old_pstate,
2782                 cpu->pstate.current_pstate,
2783                 sample->mperf,
2784                 sample->aperf,
2785                 sample->tsc,
2786                 get_avg_frequency(cpu),
2787                 fp_toint(cpu->iowait_boost * 100));
2788 }
2789
2790 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2791                                      u32 desired, bool fast_switch)
2792 {
2793         u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2794
2795         value &= ~HWP_MIN_PERF(~0L);
2796         value |= HWP_MIN_PERF(min);
2797
2798         value &= ~HWP_MAX_PERF(~0L);
2799         value |= HWP_MAX_PERF(max);
2800
2801         value &= ~HWP_DESIRED_PERF(~0L);
2802         value |= HWP_DESIRED_PERF(desired);
2803
2804         if (value == prev)
2805                 return;
2806
2807         WRITE_ONCE(cpu->hwp_req_cached, value);
2808         if (fast_switch)
2809                 wrmsrl(MSR_HWP_REQUEST, value);
2810         else
2811                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2812 }
2813
2814 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2815                                           u32 target_pstate, bool fast_switch)
2816 {
2817         if (fast_switch)
2818                 wrmsrl(MSR_IA32_PERF_CTL,
2819                        pstate_funcs.get_val(cpu, target_pstate));
2820         else
2821                 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2822                               pstate_funcs.get_val(cpu, target_pstate));
2823 }
2824
2825 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2826                                        int target_pstate, bool fast_switch)
2827 {
2828         struct cpudata *cpu = all_cpu_data[policy->cpu];
2829         int old_pstate = cpu->pstate.current_pstate;
2830
2831         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2832         if (hwp_active) {
2833                 int max_pstate = policy->strict_target ?
2834                                         target_pstate : cpu->max_perf_ratio;
2835
2836                 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2837                                          fast_switch);
2838         } else if (target_pstate != old_pstate) {
2839                 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2840         }
2841
2842         cpu->pstate.current_pstate = target_pstate;
2843
2844         intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2845                             INTEL_PSTATE_TRACE_TARGET, old_pstate);
2846
2847         return target_pstate;
2848 }
2849
2850 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2851                                 unsigned int target_freq,
2852                                 unsigned int relation)
2853 {
2854         struct cpudata *cpu = all_cpu_data[policy->cpu];
2855         struct cpufreq_freqs freqs;
2856         int target_pstate;
2857
2858         update_turbo_state();
2859
2860         freqs.old = policy->cur;
2861         freqs.new = target_freq;
2862
2863         cpufreq_freq_transition_begin(policy, &freqs);
2864
2865         switch (relation) {
2866         case CPUFREQ_RELATION_L:
2867                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2868                 break;
2869         case CPUFREQ_RELATION_H:
2870                 target_pstate = freqs.new / cpu->pstate.scaling;
2871                 break;
2872         default:
2873                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2874                 break;
2875         }
2876
2877         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2878
2879         freqs.new = target_pstate * cpu->pstate.scaling;
2880
2881         cpufreq_freq_transition_end(policy, &freqs, false);
2882
2883         return 0;
2884 }
2885
2886 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2887                                               unsigned int target_freq)
2888 {
2889         struct cpudata *cpu = all_cpu_data[policy->cpu];
2890         int target_pstate;
2891
2892         update_turbo_state();
2893
2894         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2895
2896         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2897
2898         return target_pstate * cpu->pstate.scaling;
2899 }
2900
2901 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2902                                       unsigned long min_perf,
2903                                       unsigned long target_perf,
2904                                       unsigned long capacity)
2905 {
2906         struct cpudata *cpu = all_cpu_data[cpunum];
2907         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2908         int old_pstate = cpu->pstate.current_pstate;
2909         int cap_pstate, min_pstate, max_pstate, target_pstate;
2910
2911         update_turbo_state();
2912         cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2913                                              HWP_HIGHEST_PERF(hwp_cap);
2914
2915         /* Optimization: Avoid unnecessary divisions. */
2916
2917         target_pstate = cap_pstate;
2918         if (target_perf < capacity)
2919                 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2920
2921         min_pstate = cap_pstate;
2922         if (min_perf < capacity)
2923                 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2924
2925         if (min_pstate < cpu->pstate.min_pstate)
2926                 min_pstate = cpu->pstate.min_pstate;
2927
2928         if (min_pstate < cpu->min_perf_ratio)
2929                 min_pstate = cpu->min_perf_ratio;
2930
2931         max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2932         if (max_pstate < min_pstate)
2933                 max_pstate = min_pstate;
2934
2935         target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2936
2937         intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2938
2939         cpu->pstate.current_pstate = target_pstate;
2940         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2941 }
2942
2943 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2944 {
2945         struct freq_qos_request *req;
2946         struct cpudata *cpu;
2947         struct device *dev;
2948         int ret, freq;
2949
2950         dev = get_cpu_device(policy->cpu);
2951         if (!dev)
2952                 return -ENODEV;
2953
2954         ret = __intel_pstate_cpu_init(policy);
2955         if (ret)
2956                 return ret;
2957
2958         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2959         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2960         policy->cur = policy->cpuinfo.min_freq;
2961
2962         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2963         if (!req) {
2964                 ret = -ENOMEM;
2965                 goto pstate_exit;
2966         }
2967
2968         cpu = all_cpu_data[policy->cpu];
2969
2970         if (hwp_active) {
2971                 u64 value;
2972
2973                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2974
2975                 intel_pstate_get_hwp_cap(cpu);
2976
2977                 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2978                 WRITE_ONCE(cpu->hwp_req_cached, value);
2979
2980                 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
2981         } else {
2982                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2983         }
2984
2985         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
2986
2987         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2988                                    freq);
2989         if (ret < 0) {
2990                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
2991                 goto free_req;
2992         }
2993
2994         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
2995
2996         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2997                                    freq);
2998         if (ret < 0) {
2999                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3000                 goto remove_min_req;
3001         }
3002
3003         policy->driver_data = req;
3004
3005         return 0;
3006
3007 remove_min_req:
3008         freq_qos_remove_request(req);
3009 free_req:
3010         kfree(req);
3011 pstate_exit:
3012         intel_pstate_exit_perf_limits(policy);
3013
3014         return ret;
3015 }
3016
3017 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3018 {
3019         struct freq_qos_request *req;
3020
3021         req = policy->driver_data;
3022
3023         freq_qos_remove_request(req + 1);
3024         freq_qos_remove_request(req);
3025         kfree(req);
3026
3027         return intel_pstate_cpu_exit(policy);
3028 }
3029
3030 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3031 {
3032         intel_pstate_suspend(policy);
3033
3034         if (hwp_active) {
3035                 struct cpudata *cpu = all_cpu_data[policy->cpu];
3036                 u64 value = READ_ONCE(cpu->hwp_req_cached);
3037
3038                 /*
3039                  * Clear the desired perf field in MSR_HWP_REQUEST in case
3040                  * intel_cpufreq_adjust_perf() is in use and the last value
3041                  * written by it may not be suitable.
3042                  */
3043                 value &= ~HWP_DESIRED_PERF(~0L);
3044                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3045                 WRITE_ONCE(cpu->hwp_req_cached, value);
3046         }
3047
3048         return 0;
3049 }
3050
3051 static struct cpufreq_driver intel_cpufreq = {
3052         .flags          = CPUFREQ_CONST_LOOPS,
3053         .verify         = intel_cpufreq_verify_policy,
3054         .target         = intel_cpufreq_target,
3055         .fast_switch    = intel_cpufreq_fast_switch,
3056         .init           = intel_cpufreq_cpu_init,
3057         .exit           = intel_cpufreq_cpu_exit,
3058         .offline        = intel_cpufreq_cpu_offline,
3059         .online         = intel_pstate_cpu_online,
3060         .suspend        = intel_cpufreq_suspend,
3061         .resume         = intel_pstate_resume,
3062         .update_limits  = intel_pstate_update_limits,
3063         .name           = "intel_cpufreq",
3064 };
3065
3066 static struct cpufreq_driver *default_driver;
3067
3068 static void intel_pstate_driver_cleanup(void)
3069 {
3070         unsigned int cpu;
3071
3072         cpus_read_lock();
3073         for_each_online_cpu(cpu) {
3074                 if (all_cpu_data[cpu]) {
3075                         if (intel_pstate_driver == &intel_pstate)
3076                                 intel_pstate_clear_update_util_hook(cpu);
3077
3078                         spin_lock(&hwp_notify_lock);
3079                         kfree(all_cpu_data[cpu]);
3080                         WRITE_ONCE(all_cpu_data[cpu], NULL);
3081                         spin_unlock(&hwp_notify_lock);
3082                 }
3083         }
3084         cpus_read_unlock();
3085
3086         intel_pstate_driver = NULL;
3087 }
3088
3089 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3090 {
3091         int ret;
3092
3093         if (driver == &intel_pstate)
3094                 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3095
3096         memset(&global, 0, sizeof(global));
3097         global.max_perf_pct = 100;
3098
3099         intel_pstate_driver = driver;
3100         ret = cpufreq_register_driver(intel_pstate_driver);
3101         if (ret) {
3102                 intel_pstate_driver_cleanup();
3103                 return ret;
3104         }
3105
3106         global.min_perf_pct = min_perf_pct_min();
3107
3108         return 0;
3109 }
3110
3111 static ssize_t intel_pstate_show_status(char *buf)
3112 {
3113         if (!intel_pstate_driver)
3114                 return sprintf(buf, "off\n");
3115
3116         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3117                                         "active" : "passive");
3118 }
3119
3120 static int intel_pstate_update_status(const char *buf, size_t size)
3121 {
3122         if (size == 3 && !strncmp(buf, "off", size)) {
3123                 if (!intel_pstate_driver)
3124                         return -EINVAL;
3125
3126                 if (hwp_active)
3127                         return -EBUSY;
3128
3129                 cpufreq_unregister_driver(intel_pstate_driver);
3130                 intel_pstate_driver_cleanup();
3131                 return 0;
3132         }
3133
3134         if (size == 6 && !strncmp(buf, "active", size)) {
3135                 if (intel_pstate_driver) {
3136                         if (intel_pstate_driver == &intel_pstate)
3137                                 return 0;
3138
3139                         cpufreq_unregister_driver(intel_pstate_driver);
3140                 }
3141
3142                 return intel_pstate_register_driver(&intel_pstate);
3143         }
3144
3145         if (size == 7 && !strncmp(buf, "passive", size)) {
3146                 if (intel_pstate_driver) {
3147                         if (intel_pstate_driver == &intel_cpufreq)
3148                                 return 0;
3149
3150                         cpufreq_unregister_driver(intel_pstate_driver);
3151                         intel_pstate_sysfs_hide_hwp_dynamic_boost();
3152                 }
3153
3154                 return intel_pstate_register_driver(&intel_cpufreq);
3155         }
3156
3157         return -EINVAL;
3158 }
3159
3160 static int no_load __initdata;
3161 static int no_hwp __initdata;
3162 static int hwp_only __initdata;
3163 static unsigned int force_load __initdata;
3164
3165 static int __init intel_pstate_msrs_not_valid(void)
3166 {
3167         if (!pstate_funcs.get_max(0) ||
3168             !pstate_funcs.get_min(0) ||
3169             !pstate_funcs.get_turbo(0))
3170                 return -ENODEV;
3171
3172         return 0;
3173 }
3174
3175 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3176 {
3177         pstate_funcs.get_max   = funcs->get_max;
3178         pstate_funcs.get_max_physical = funcs->get_max_physical;
3179         pstate_funcs.get_min   = funcs->get_min;
3180         pstate_funcs.get_turbo = funcs->get_turbo;
3181         pstate_funcs.get_scaling = funcs->get_scaling;
3182         pstate_funcs.get_val   = funcs->get_val;
3183         pstate_funcs.get_vid   = funcs->get_vid;
3184         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3185 }
3186
3187 #ifdef CONFIG_ACPI
3188
3189 static bool __init intel_pstate_no_acpi_pss(void)
3190 {
3191         int i;
3192
3193         for_each_possible_cpu(i) {
3194                 acpi_status status;
3195                 union acpi_object *pss;
3196                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3197                 struct acpi_processor *pr = per_cpu(processors, i);
3198
3199                 if (!pr)
3200                         continue;
3201
3202                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3203                 if (ACPI_FAILURE(status))
3204                         continue;
3205
3206                 pss = buffer.pointer;
3207                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3208                         kfree(pss);
3209                         return false;
3210                 }
3211
3212                 kfree(pss);
3213         }
3214
3215         pr_debug("ACPI _PSS not found\n");
3216         return true;
3217 }
3218
3219 static bool __init intel_pstate_no_acpi_pcch(void)
3220 {
3221         acpi_status status;
3222         acpi_handle handle;
3223
3224         status = acpi_get_handle(NULL, "\\_SB", &handle);
3225         if (ACPI_FAILURE(status))
3226                 goto not_found;
3227
3228         if (acpi_has_method(handle, "PCCH"))
3229                 return false;
3230
3231 not_found:
3232         pr_debug("ACPI PCCH not found\n");
3233         return true;
3234 }
3235
3236 static bool __init intel_pstate_has_acpi_ppc(void)
3237 {
3238         int i;
3239
3240         for_each_possible_cpu(i) {
3241                 struct acpi_processor *pr = per_cpu(processors, i);
3242
3243                 if (!pr)
3244                         continue;
3245                 if (acpi_has_method(pr->handle, "_PPC"))
3246                         return true;
3247         }
3248         pr_debug("ACPI _PPC not found\n");
3249         return false;
3250 }
3251
3252 enum {
3253         PSS,
3254         PPC,
3255 };
3256
3257 /* Hardware vendor-specific info that has its own power management modes */
3258 static struct acpi_platform_list plat_info[] __initdata = {
3259         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3260         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3261         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3262         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3263         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3264         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3265         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3266         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3267         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3268         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3269         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3270         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3271         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3272         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3273         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3274         { } /* End */
3275 };
3276
3277 #define BITMASK_OOB     (BIT(8) | BIT(18))
3278
3279 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3280 {
3281         const struct x86_cpu_id *id;
3282         u64 misc_pwr;
3283         int idx;
3284
3285         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3286         if (id) {
3287                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3288                 if (misc_pwr & BITMASK_OOB) {
3289                         pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3290                         pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3291                         return true;
3292                 }
3293         }
3294
3295         idx = acpi_match_platform_list(plat_info);
3296         if (idx < 0)
3297                 return false;
3298
3299         switch (plat_info[idx].data) {
3300         case PSS:
3301                 if (!intel_pstate_no_acpi_pss())
3302                         return false;
3303
3304                 return intel_pstate_no_acpi_pcch();
3305         case PPC:
3306                 return intel_pstate_has_acpi_ppc() && !force_load;
3307         }
3308
3309         return false;
3310 }
3311
3312 static void intel_pstate_request_control_from_smm(void)
3313 {
3314         /*
3315          * It may be unsafe to request P-states control from SMM if _PPC support
3316          * has not been enabled.
3317          */
3318         if (acpi_ppc)
3319                 acpi_processor_pstate_control();
3320 }
3321 #else /* CONFIG_ACPI not enabled */
3322 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3323 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3324 static inline void intel_pstate_request_control_from_smm(void) {}
3325 #endif /* CONFIG_ACPI */
3326
3327 #define INTEL_PSTATE_HWP_BROADWELL      0x01
3328
3329 #define X86_MATCH_HWP(model, hwp_mode)                                  \
3330         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3331                                            X86_FEATURE_HWP, hwp_mode)
3332
3333 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3334         X86_MATCH_HWP(BROADWELL_X,      INTEL_PSTATE_HWP_BROADWELL),
3335         X86_MATCH_HWP(BROADWELL_D,      INTEL_PSTATE_HWP_BROADWELL),
3336         X86_MATCH_HWP(ANY,              0),
3337         {}
3338 };
3339
3340 static bool intel_pstate_hwp_is_enabled(void)
3341 {
3342         u64 value;
3343
3344         rdmsrl(MSR_PM_ENABLE, value);
3345         return !!(value & 0x1);
3346 }
3347
3348 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3349         /*
3350          * Set EPP value as 102, this is the max suggested EPP
3351          * which can result in one core turbo frequency for
3352          * AlderLake Mobile CPUs.
3353          */
3354         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3355         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3356         {}
3357 };
3358
3359 static int __init intel_pstate_init(void)
3360 {
3361         static struct cpudata **_all_cpu_data;
3362         const struct x86_cpu_id *id;
3363         int rc;
3364
3365         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3366                 return -ENODEV;
3367
3368         id = x86_match_cpu(hwp_support_ids);
3369         if (id) {
3370                 hwp_forced = intel_pstate_hwp_is_enabled();
3371
3372                 if (hwp_forced)
3373                         pr_info("HWP enabled by BIOS\n");
3374                 else if (no_load)
3375                         return -ENODEV;
3376
3377                 copy_cpu_funcs(&core_funcs);
3378                 /*
3379                  * Avoid enabling HWP for processors without EPP support,
3380                  * because that means incomplete HWP implementation which is a
3381                  * corner case and supporting it is generally problematic.
3382                  *
3383                  * If HWP is enabled already, though, there is no choice but to
3384                  * deal with it.
3385                  */
3386                 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3387                         WRITE_ONCE(hwp_active, 1);
3388                         hwp_mode_bdw = id->driver_data;
3389                         intel_pstate.attr = hwp_cpufreq_attrs;
3390                         intel_cpufreq.attr = hwp_cpufreq_attrs;
3391                         intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3392                         intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3393                         if (!default_driver)
3394                                 default_driver = &intel_pstate;
3395
3396                         if (boot_cpu_has(X86_FEATURE_HYBRID_CPU))
3397                                 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling;
3398
3399                         goto hwp_cpu_matched;
3400                 }
3401                 pr_info("HWP not enabled\n");
3402         } else {
3403                 if (no_load)
3404                         return -ENODEV;
3405
3406                 id = x86_match_cpu(intel_pstate_cpu_ids);
3407                 if (!id) {
3408                         pr_info("CPU model not supported\n");
3409                         return -ENODEV;
3410                 }
3411
3412                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3413         }
3414
3415         if (intel_pstate_msrs_not_valid()) {
3416                 pr_info("Invalid MSRs\n");
3417                 return -ENODEV;
3418         }
3419         /* Without HWP start in the passive mode. */
3420         if (!default_driver)
3421                 default_driver = &intel_cpufreq;
3422
3423 hwp_cpu_matched:
3424         /*
3425          * The Intel pstate driver will be ignored if the platform
3426          * firmware has its own power management modes.
3427          */
3428         if (intel_pstate_platform_pwr_mgmt_exists()) {
3429                 pr_info("P-states controlled by the platform\n");
3430                 return -ENODEV;
3431         }
3432
3433         if (!hwp_active && hwp_only)
3434                 return -ENOTSUPP;
3435
3436         pr_info("Intel P-state driver initializing\n");
3437
3438         _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3439         if (!_all_cpu_data)
3440                 return -ENOMEM;
3441
3442         WRITE_ONCE(all_cpu_data, _all_cpu_data);
3443
3444         intel_pstate_request_control_from_smm();
3445
3446         intel_pstate_sysfs_expose_params();
3447
3448         if (hwp_active) {
3449                 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3450
3451                 if (id)
3452                         epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3453         }
3454
3455         mutex_lock(&intel_pstate_driver_lock);
3456         rc = intel_pstate_register_driver(default_driver);
3457         mutex_unlock(&intel_pstate_driver_lock);
3458         if (rc) {
3459                 intel_pstate_sysfs_remove();
3460                 return rc;
3461         }
3462
3463         if (hwp_active) {
3464                 const struct x86_cpu_id *id;
3465
3466                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3467                 if (id) {
3468                         set_power_ctl_ee_state(false);
3469                         pr_info("Disabling energy efficiency optimization\n");
3470                 }
3471
3472                 pr_info("HWP enabled\n");
3473         } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3474                 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3475         }
3476
3477         return 0;
3478 }
3479 device_initcall(intel_pstate_init);
3480
3481 static int __init intel_pstate_setup(char *str)
3482 {
3483         if (!str)
3484                 return -EINVAL;
3485
3486         if (!strcmp(str, "disable"))
3487                 no_load = 1;
3488         else if (!strcmp(str, "active"))
3489                 default_driver = &intel_pstate;
3490         else if (!strcmp(str, "passive"))
3491                 default_driver = &intel_cpufreq;
3492
3493         if (!strcmp(str, "no_hwp"))
3494                 no_hwp = 1;
3495
3496         if (!strcmp(str, "force"))
3497                 force_load = 1;
3498         if (!strcmp(str, "hwp_only"))
3499                 hwp_only = 1;
3500         if (!strcmp(str, "per_cpu_perf_limits"))
3501                 per_cpu_limits = true;
3502
3503 #ifdef CONFIG_ACPI
3504         if (!strcmp(str, "support_acpi_ppc"))
3505                 acpi_ppc = true;
3506 #endif
3507
3508         return 0;
3509 }
3510 early_param("intel_pstate", intel_pstate_setup);
3511
3512 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3513 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");