1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_pstate.c: Native P state management for Intel processors
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
31 #include <asm/div64.h>
33 #include <asm/cpu_device_id.h>
34 #include <asm/cpufeature.h>
35 #include <asm/intel-family.h>
36 #include "../drivers/thermal/intel/thermal_interrupt.h"
38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
60 static inline int32_t mul_fp(int32_t x, int32_t y)
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
65 static inline int32_t div_fp(s64 x, s64 y)
67 return div64_s64((int64_t)x << FRAC_BITS, y);
70 static inline int ceiling_fp(int32_t x)
75 mask = (1 << FRAC_BITS) - 1;
81 static inline u64 mul_ext_fp(u64 x, u64 y)
83 return (x * y) >> EXT_FRAC_BITS;
86 static inline u64 div_ext_fp(u64 x, u64 y)
88 return div64_u64(x << EXT_FRAC_BITS, y);
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
104 * @time: Current time from scheduler
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
110 int32_t core_avg_perf;
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
127 * @scaling: Scaling factor between performance and frequency
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @min_freq: @min_pstate frequency in cpufreq units
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical;
140 int perf_ctl_scaling;
143 unsigned int min_freq;
144 unsigned int max_freq;
145 unsigned int turbo_freq;
149 * struct vid_data - Stores voltage information data
150 * @min: VID data for this platform corresponding to
152 * @max: VID data corresponding to the highest P State.
153 * @turbo: VID data for turbo P state
154 * @ratio: Ratio of (vid max - vid min) /
155 * (max P state - Min P State)
157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158 * This data is used in Atom platforms, where in addition to target P state,
159 * the voltage data needs to be specified to select next P State.
169 * struct global_params - Global parameters, mostly tunable via sysfs.
170 * @no_turbo: Whether or not to use turbo P-states.
171 * @turbo_disabled: Whether or not turbo P-states are available at all,
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
173 * not the maximum reported turbo P-state is different from
174 * the maximum reported non-turbo one.
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
181 struct global_params {
184 bool turbo_disabled_mf;
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @prev_cummulative_iowait: IO Wait time difference from last and
206 * @sample: Storage for storing last Sample data
207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
209 * @acpi_perf_data: Stores ACPI perf information read from _PSS
210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
211 * @epp_powersave: Last saved HWP energy performance preference
212 * (EPP) or energy performance bias (EPB),
213 * when policy switched to performance
214 * @epp_policy: Last saved policy used to set EPP/EPB
215 * @epp_default: Power on default HWP energy performance
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
220 * @last_io_update: Last time when IO wake flag was set
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @hwp_notify_work: workqueue for HWP notifications.
226 * This structure stores per CPU instance data for all CPUs.
232 struct update_util_data update_util;
233 bool update_util_set;
235 struct pstate_data pstate;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
252 unsigned int iowait_boost;
260 unsigned int sched_flags;
263 struct delayed_work hwp_notify_work;
266 static struct cpudata **all_cpu_data;
269 * struct pstate_funcs - Per CPU model specific callbacks
270 * @get_max: Callback to get maximum non turbo effective P state
271 * @get_max_physical: Callback to get maximum non turbo physical P state
272 * @get_min: Callback to get minimum P state
273 * @get_turbo: Callback to get turbo P state
274 * @get_scaling: Callback to get frequency scaling factor
275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
283 struct pstate_funcs {
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
288 int (*get_scaling)(void);
289 int (*get_cpu_scaling)(int cpu);
290 int (*get_aperf_mperf_shift)(void);
291 u64 (*get_val)(struct cpudata*, int pstate);
292 void (*get_vid)(struct cpudata *);
295 static struct pstate_funcs pstate_funcs __read_mostly;
297 static int hwp_active __read_mostly;
298 static int hwp_mode_bdw __read_mostly;
299 static bool per_cpu_limits __read_mostly;
300 static bool hwp_boost __read_mostly;
301 static bool hwp_forced __read_mostly;
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
306 static bool acpi_ppc;
309 static struct global_params global;
311 static DEFINE_MUTEX(intel_pstate_driver_lock);
312 static DEFINE_MUTEX(intel_pstate_limits_lock);
316 static bool intel_pstate_acpi_pm_profile_server(void)
318 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
319 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
325 static bool intel_pstate_get_ppc_enable_status(void)
327 if (intel_pstate_acpi_pm_profile_server())
333 #ifdef CONFIG_ACPI_CPPC_LIB
335 /* The work item is needed to avoid CPU hotplug locking issues */
336 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
338 sched_set_itmt_support();
341 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
343 #define CPPC_MAX_PERF U8_MAX
345 static void intel_pstate_set_itmt_prio(int cpu)
347 struct cppc_perf_caps cppc_perf;
348 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
351 ret = cppc_get_perf_caps(cpu, &cppc_perf);
356 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
357 * In this case we can't use CPPC.highest_perf to enable ITMT.
358 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
360 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
361 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
364 * The priorities can be set regardless of whether or not
365 * sched_set_itmt_support(true) has been called and it is valid to
366 * update them at any time after it has been called.
368 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
370 if (max_highest_perf <= min_highest_perf) {
371 if (cppc_perf.highest_perf > max_highest_perf)
372 max_highest_perf = cppc_perf.highest_perf;
374 if (cppc_perf.highest_perf < min_highest_perf)
375 min_highest_perf = cppc_perf.highest_perf;
377 if (max_highest_perf > min_highest_perf) {
379 * This code can be run during CPU online under the
380 * CPU hotplug locks, so sched_set_itmt_support()
381 * cannot be called from here. Queue up a work item
384 schedule_work(&sched_itmt_work);
389 static int intel_pstate_get_cppc_guaranteed(int cpu)
391 struct cppc_perf_caps cppc_perf;
394 ret = cppc_get_perf_caps(cpu, &cppc_perf);
398 if (cppc_perf.guaranteed_perf)
399 return cppc_perf.guaranteed_perf;
401 return cppc_perf.nominal_perf;
403 #else /* CONFIG_ACPI_CPPC_LIB */
404 static inline void intel_pstate_set_itmt_prio(int cpu)
407 #endif /* CONFIG_ACPI_CPPC_LIB */
409 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
416 intel_pstate_set_itmt_prio(policy->cpu);
420 if (!intel_pstate_get_ppc_enable_status())
423 cpu = all_cpu_data[policy->cpu];
425 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
431 * Check if the control value in _PSS is for PERF_CTL MSR, which should
432 * guarantee that the states returned by it map to the states in our
435 if (cpu->acpi_perf_data.control_register.space_id !=
436 ACPI_ADR_SPACE_FIXED_HARDWARE)
440 * If there is only one entry _PSS, simply ignore _PSS and continue as
441 * usual without taking _PSS into account
443 if (cpu->acpi_perf_data.state_count < 2)
446 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
447 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
448 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
449 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
450 (u32) cpu->acpi_perf_data.states[i].core_frequency,
451 (u32) cpu->acpi_perf_data.states[i].power,
452 (u32) cpu->acpi_perf_data.states[i].control);
455 cpu->valid_pss_table = true;
456 pr_debug("_PPC limits will be enforced\n");
461 cpu->valid_pss_table = false;
462 acpi_processor_unregister_performance(policy->cpu);
465 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
469 cpu = all_cpu_data[policy->cpu];
470 if (!cpu->valid_pss_table)
473 acpi_processor_unregister_performance(policy->cpu);
475 #else /* CONFIG_ACPI */
476 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
480 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
484 static inline bool intel_pstate_acpi_pm_profile_server(void)
488 #endif /* CONFIG_ACPI */
490 #ifndef CONFIG_ACPI_CPPC_LIB
491 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
495 #endif /* CONFIG_ACPI_CPPC_LIB */
498 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
501 * On hybrid processors, HWP may expose more performance levels than there are
502 * P-states accessible through the PERF_CTL interface. If that happens, the
503 * scaling factor between HWP performance levels and CPU frequency will be less
504 * than the scaling factor between P-state values and CPU frequency.
506 * In that case, adjust the CPU parameters used in computations accordingly.
508 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
510 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
511 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
512 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
513 int scaling = cpu->pstate.scaling;
515 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
516 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
517 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
518 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
519 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
520 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
522 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
524 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
527 cpu->pstate.max_pstate_physical =
528 DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling,
531 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
533 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
534 * the effective range of HWP performance levels.
536 cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling);
539 static inline void update_turbo_state(void)
544 cpu = all_cpu_data[0];
545 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
546 global.turbo_disabled =
547 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
548 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
551 static int min_perf_pct_min(void)
553 struct cpudata *cpu = all_cpu_data[0];
554 int turbo_pstate = cpu->pstate.turbo_pstate;
556 return turbo_pstate ?
557 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
560 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
565 if (!boot_cpu_has(X86_FEATURE_EPB))
568 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
572 return (s16)(epb & 0x0f);
575 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
579 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
581 * When hwp_req_data is 0, means that caller didn't read
582 * MSR_HWP_REQUEST, so need to read and get EPP.
585 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
590 epp = (hwp_req_data >> 24) & 0xff;
592 /* When there is no EPP present, HWP uses EPB settings */
593 epp = intel_pstate_get_epb(cpu_data);
599 static int intel_pstate_set_epb(int cpu, s16 pref)
604 if (!boot_cpu_has(X86_FEATURE_EPB))
607 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
611 epb = (epb & ~0x0f) | pref;
612 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
618 * EPP/EPB display strings corresponding to EPP index in the
619 * energy_perf_strings[]
621 *-------------------------------------
624 * 2 balance_performance
629 enum energy_perf_value_index {
630 EPP_INDEX_DEFAULT = 0,
631 EPP_INDEX_PERFORMANCE,
632 EPP_INDEX_BALANCE_PERFORMANCE,
633 EPP_INDEX_BALANCE_POWERSAVE,
637 static const char * const energy_perf_strings[] = {
638 [EPP_INDEX_DEFAULT] = "default",
639 [EPP_INDEX_PERFORMANCE] = "performance",
640 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
641 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
642 [EPP_INDEX_POWERSAVE] = "power",
645 static unsigned int epp_values[] = {
646 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
647 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
648 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
649 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
650 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
653 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
659 epp = intel_pstate_get_epp(cpu_data, 0);
663 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
664 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
665 return EPP_INDEX_PERFORMANCE;
666 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
667 return EPP_INDEX_BALANCE_PERFORMANCE;
668 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
669 return EPP_INDEX_BALANCE_POWERSAVE;
670 if (epp == epp_values[EPP_INDEX_POWERSAVE])
671 return EPP_INDEX_POWERSAVE;
674 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
677 * 0x00-0x03 : Performance
678 * 0x04-0x07 : Balance performance
679 * 0x08-0x0B : Balance power
681 * The EPB is a 4 bit value, but our ranges restrict the
682 * value which can be set. Here only using top two bits
685 index = (epp >> 2) + 1;
691 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
696 * Use the cached HWP Request MSR value, because in the active mode the
697 * register itself may be updated by intel_pstate_hwp_boost_up() or
698 * intel_pstate_hwp_boost_down() at any time.
700 u64 value = READ_ONCE(cpu->hwp_req_cached);
702 value &= ~GENMASK_ULL(31, 24);
703 value |= (u64)epp << 24;
705 * The only other updater of hwp_req_cached in the active mode,
706 * intel_pstate_hwp_set(), is called under the same lock as this
707 * function, so it cannot run in parallel with the update below.
709 WRITE_ONCE(cpu->hwp_req_cached, value);
710 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
712 cpu->epp_cached = epp;
717 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
718 int pref_index, bool use_raw,
725 epp = cpu_data->epp_default;
727 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
730 else if (epp == -EINVAL)
731 epp = epp_values[pref_index];
734 * To avoid confusion, refuse to set EPP to any values different
735 * from 0 (performance) if the current policy is "performance",
736 * because those values would be overridden.
738 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
741 ret = intel_pstate_set_epp(cpu_data, epp);
744 epp = (pref_index - 1) << 2;
745 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
751 static ssize_t show_energy_performance_available_preferences(
752 struct cpufreq_policy *policy, char *buf)
757 while (energy_perf_strings[i] != NULL)
758 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
760 ret += sprintf(&buf[ret], "\n");
765 cpufreq_freq_attr_ro(energy_performance_available_preferences);
767 static struct cpufreq_driver intel_pstate;
769 static ssize_t store_energy_performance_preference(
770 struct cpufreq_policy *policy, const char *buf, size_t count)
772 struct cpudata *cpu = all_cpu_data[policy->cpu];
773 char str_preference[21];
778 ret = sscanf(buf, "%20s", str_preference);
782 ret = match_string(energy_perf_strings, -1, str_preference);
784 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
787 ret = kstrtouint(buf, 10, &epp);
798 * This function runs with the policy R/W semaphore held, which
799 * guarantees that the driver pointer will not change while it is
802 if (!intel_pstate_driver)
805 mutex_lock(&intel_pstate_limits_lock);
807 if (intel_pstate_driver == &intel_pstate) {
808 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
811 * In the passive mode the governor needs to be stopped on the
812 * target CPU before the EPP update and restarted after it,
813 * which is super-heavy-weight, so make sure it is worth doing
817 epp = ret ? epp_values[ret] : cpu->epp_default;
819 if (cpu->epp_cached != epp) {
822 cpufreq_stop_governor(policy);
823 ret = intel_pstate_set_epp(cpu, epp);
824 err = cpufreq_start_governor(policy);
830 mutex_unlock(&intel_pstate_limits_lock);
835 static ssize_t show_energy_performance_preference(
836 struct cpufreq_policy *policy, char *buf)
838 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
839 int preference, raw_epp;
841 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
846 return sprintf(buf, "%d\n", raw_epp);
848 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
851 cpufreq_freq_attr_rw(energy_performance_preference);
853 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
855 struct cpudata *cpu = all_cpu_data[policy->cpu];
858 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
862 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
863 ratio = HWP_GUARANTEED_PERF(cap);
866 freq = ratio * cpu->pstate.scaling;
867 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
868 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
870 return sprintf(buf, "%d\n", freq);
873 cpufreq_freq_attr_ro(base_frequency);
875 static struct freq_attr *hwp_cpufreq_attrs[] = {
876 &energy_performance_preference,
877 &energy_performance_available_preferences,
882 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
886 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
887 WRITE_ONCE(cpu->hwp_cap_cached, cap);
888 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
889 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
892 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
894 int scaling = cpu->pstate.scaling;
896 __intel_pstate_get_hwp_cap(cpu);
898 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
899 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
900 if (scaling != cpu->pstate.perf_ctl_scaling) {
901 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
903 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
905 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
910 static void intel_pstate_hwp_set(unsigned int cpu)
912 struct cpudata *cpu_data = all_cpu_data[cpu];
917 max = cpu_data->max_perf_ratio;
918 min = cpu_data->min_perf_ratio;
920 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
923 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
925 value &= ~HWP_MIN_PERF(~0L);
926 value |= HWP_MIN_PERF(min);
928 value &= ~HWP_MAX_PERF(~0L);
929 value |= HWP_MAX_PERF(max);
931 if (cpu_data->epp_policy == cpu_data->policy)
934 cpu_data->epp_policy = cpu_data->policy;
936 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
937 epp = intel_pstate_get_epp(cpu_data, value);
938 cpu_data->epp_powersave = epp;
939 /* If EPP read was failed, then don't try to write */
945 /* skip setting EPP, when saved value is invalid */
946 if (cpu_data->epp_powersave < 0)
950 * No need to restore EPP when it is not zero. This
952 * - Policy is not changed
953 * - user has manually changed
954 * - Error reading EPB
956 epp = intel_pstate_get_epp(cpu_data, value);
960 epp = cpu_data->epp_powersave;
962 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
963 value &= ~GENMASK_ULL(31, 24);
964 value |= (u64)epp << 24;
966 intel_pstate_set_epb(cpu, epp);
969 WRITE_ONCE(cpu_data->hwp_req_cached, value);
970 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
973 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
975 static void intel_pstate_hwp_offline(struct cpudata *cpu)
977 u64 value = READ_ONCE(cpu->hwp_req_cached);
980 intel_pstate_disable_hwp_interrupt(cpu);
982 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
984 * In case the EPP has been set to "performance" by the
985 * active mode "performance" scaling algorithm, replace that
986 * temporary value with the cached EPP one.
988 value &= ~GENMASK_ULL(31, 24);
989 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
991 * However, make sure that EPP will be set to "performance" when
992 * the CPU is brought back online again and the "performance"
993 * scaling algorithm is still in effect.
995 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
999 * Clear the desired perf field in the cached HWP request value to
1000 * prevent nonzero desired values from being leaked into the active
1003 value &= ~HWP_DESIRED_PERF(~0L);
1004 WRITE_ONCE(cpu->hwp_req_cached, value);
1006 value &= ~GENMASK_ULL(31, 0);
1007 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1009 /* Set hwp_max = hwp_min */
1010 value |= HWP_MAX_PERF(min_perf);
1011 value |= HWP_MIN_PERF(min_perf);
1013 /* Set EPP to min */
1014 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1015 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1017 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1020 #define POWER_CTL_EE_ENABLE 1
1021 #define POWER_CTL_EE_DISABLE 2
1023 static int power_ctl_ee_state;
1025 static void set_power_ctl_ee_state(bool input)
1029 mutex_lock(&intel_pstate_driver_lock);
1030 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1032 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1033 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1035 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1036 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1038 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1039 mutex_unlock(&intel_pstate_driver_lock);
1042 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1044 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1046 intel_pstate_hwp_enable(cpu);
1047 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1050 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1052 struct cpudata *cpu = all_cpu_data[policy->cpu];
1054 pr_debug("CPU %d suspending\n", cpu->cpu);
1056 cpu->suspended = true;
1058 /* disable HWP interrupt and cancel any pending work */
1059 intel_pstate_disable_hwp_interrupt(cpu);
1064 static int intel_pstate_resume(struct cpufreq_policy *policy)
1066 struct cpudata *cpu = all_cpu_data[policy->cpu];
1068 pr_debug("CPU %d resuming\n", cpu->cpu);
1070 /* Only restore if the system default is changed */
1071 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1072 set_power_ctl_ee_state(true);
1073 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1074 set_power_ctl_ee_state(false);
1076 if (cpu->suspended && hwp_active) {
1077 mutex_lock(&intel_pstate_limits_lock);
1079 /* Re-enable HWP, because "online" has not done that. */
1080 intel_pstate_hwp_reenable(cpu);
1082 mutex_unlock(&intel_pstate_limits_lock);
1085 cpu->suspended = false;
1090 static void intel_pstate_update_policies(void)
1094 for_each_possible_cpu(cpu)
1095 cpufreq_update_policy(cpu);
1098 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1099 struct cpufreq_policy *policy)
1101 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1102 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1103 refresh_frequency_limits(policy);
1106 static void intel_pstate_update_max_freq(unsigned int cpu)
1108 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1113 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1115 cpufreq_cpu_release(policy);
1118 static void intel_pstate_update_limits(unsigned int cpu)
1120 mutex_lock(&intel_pstate_driver_lock);
1122 update_turbo_state();
1124 * If turbo has been turned on or off globally, policy limits for
1125 * all CPUs need to be updated to reflect that.
1127 if (global.turbo_disabled_mf != global.turbo_disabled) {
1128 global.turbo_disabled_mf = global.turbo_disabled;
1129 arch_set_max_freq_ratio(global.turbo_disabled);
1130 for_each_possible_cpu(cpu)
1131 intel_pstate_update_max_freq(cpu);
1133 cpufreq_update_policy(cpu);
1136 mutex_unlock(&intel_pstate_driver_lock);
1139 /************************** sysfs begin ************************/
1140 #define show_one(file_name, object) \
1141 static ssize_t show_##file_name \
1142 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1144 return sprintf(buf, "%u\n", global.object); \
1147 static ssize_t intel_pstate_show_status(char *buf);
1148 static int intel_pstate_update_status(const char *buf, size_t size);
1150 static ssize_t show_status(struct kobject *kobj,
1151 struct kobj_attribute *attr, char *buf)
1155 mutex_lock(&intel_pstate_driver_lock);
1156 ret = intel_pstate_show_status(buf);
1157 mutex_unlock(&intel_pstate_driver_lock);
1162 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1163 const char *buf, size_t count)
1165 char *p = memchr(buf, '\n', count);
1168 mutex_lock(&intel_pstate_driver_lock);
1169 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1170 mutex_unlock(&intel_pstate_driver_lock);
1172 return ret < 0 ? ret : count;
1175 static ssize_t show_turbo_pct(struct kobject *kobj,
1176 struct kobj_attribute *attr, char *buf)
1178 struct cpudata *cpu;
1179 int total, no_turbo, turbo_pct;
1182 mutex_lock(&intel_pstate_driver_lock);
1184 if (!intel_pstate_driver) {
1185 mutex_unlock(&intel_pstate_driver_lock);
1189 cpu = all_cpu_data[0];
1191 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1192 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1193 turbo_fp = div_fp(no_turbo, total);
1194 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1196 mutex_unlock(&intel_pstate_driver_lock);
1198 return sprintf(buf, "%u\n", turbo_pct);
1201 static ssize_t show_num_pstates(struct kobject *kobj,
1202 struct kobj_attribute *attr, char *buf)
1204 struct cpudata *cpu;
1207 mutex_lock(&intel_pstate_driver_lock);
1209 if (!intel_pstate_driver) {
1210 mutex_unlock(&intel_pstate_driver_lock);
1214 cpu = all_cpu_data[0];
1215 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1217 mutex_unlock(&intel_pstate_driver_lock);
1219 return sprintf(buf, "%u\n", total);
1222 static ssize_t show_no_turbo(struct kobject *kobj,
1223 struct kobj_attribute *attr, char *buf)
1227 mutex_lock(&intel_pstate_driver_lock);
1229 if (!intel_pstate_driver) {
1230 mutex_unlock(&intel_pstate_driver_lock);
1234 update_turbo_state();
1235 if (global.turbo_disabled)
1236 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1238 ret = sprintf(buf, "%u\n", global.no_turbo);
1240 mutex_unlock(&intel_pstate_driver_lock);
1245 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1246 const char *buf, size_t count)
1251 ret = sscanf(buf, "%u", &input);
1255 mutex_lock(&intel_pstate_driver_lock);
1257 if (!intel_pstate_driver) {
1258 mutex_unlock(&intel_pstate_driver_lock);
1262 mutex_lock(&intel_pstate_limits_lock);
1264 update_turbo_state();
1265 if (global.turbo_disabled) {
1266 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1267 mutex_unlock(&intel_pstate_limits_lock);
1268 mutex_unlock(&intel_pstate_driver_lock);
1272 global.no_turbo = clamp_t(int, input, 0, 1);
1274 if (global.no_turbo) {
1275 struct cpudata *cpu = all_cpu_data[0];
1276 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1278 /* Squash the global minimum into the permitted range. */
1279 if (global.min_perf_pct > pct)
1280 global.min_perf_pct = pct;
1283 mutex_unlock(&intel_pstate_limits_lock);
1285 intel_pstate_update_policies();
1286 arch_set_max_freq_ratio(global.no_turbo);
1288 mutex_unlock(&intel_pstate_driver_lock);
1293 static void update_qos_request(enum freq_qos_req_type type)
1295 struct freq_qos_request *req;
1296 struct cpufreq_policy *policy;
1299 for_each_possible_cpu(i) {
1300 struct cpudata *cpu = all_cpu_data[i];
1301 unsigned int freq, perf_pct;
1303 policy = cpufreq_cpu_get(i);
1307 req = policy->driver_data;
1308 cpufreq_cpu_put(policy);
1314 intel_pstate_get_hwp_cap(cpu);
1316 if (type == FREQ_QOS_MIN) {
1317 perf_pct = global.min_perf_pct;
1320 perf_pct = global.max_perf_pct;
1323 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1325 if (freq_qos_update_request(req, freq) < 0)
1326 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1330 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1331 const char *buf, size_t count)
1336 ret = sscanf(buf, "%u", &input);
1340 mutex_lock(&intel_pstate_driver_lock);
1342 if (!intel_pstate_driver) {
1343 mutex_unlock(&intel_pstate_driver_lock);
1347 mutex_lock(&intel_pstate_limits_lock);
1349 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1351 mutex_unlock(&intel_pstate_limits_lock);
1353 if (intel_pstate_driver == &intel_pstate)
1354 intel_pstate_update_policies();
1356 update_qos_request(FREQ_QOS_MAX);
1358 mutex_unlock(&intel_pstate_driver_lock);
1363 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1364 const char *buf, size_t count)
1369 ret = sscanf(buf, "%u", &input);
1373 mutex_lock(&intel_pstate_driver_lock);
1375 if (!intel_pstate_driver) {
1376 mutex_unlock(&intel_pstate_driver_lock);
1380 mutex_lock(&intel_pstate_limits_lock);
1382 global.min_perf_pct = clamp_t(int, input,
1383 min_perf_pct_min(), global.max_perf_pct);
1385 mutex_unlock(&intel_pstate_limits_lock);
1387 if (intel_pstate_driver == &intel_pstate)
1388 intel_pstate_update_policies();
1390 update_qos_request(FREQ_QOS_MIN);
1392 mutex_unlock(&intel_pstate_driver_lock);
1397 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1398 struct kobj_attribute *attr, char *buf)
1400 return sprintf(buf, "%u\n", hwp_boost);
1403 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1404 struct kobj_attribute *b,
1405 const char *buf, size_t count)
1410 ret = kstrtouint(buf, 10, &input);
1414 mutex_lock(&intel_pstate_driver_lock);
1415 hwp_boost = !!input;
1416 intel_pstate_update_policies();
1417 mutex_unlock(&intel_pstate_driver_lock);
1422 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1428 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1429 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1430 return sprintf(buf, "%d\n", !enable);
1433 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1434 const char *buf, size_t count)
1439 ret = kstrtobool(buf, &input);
1443 set_power_ctl_ee_state(input);
1448 show_one(max_perf_pct, max_perf_pct);
1449 show_one(min_perf_pct, min_perf_pct);
1451 define_one_global_rw(status);
1452 define_one_global_rw(no_turbo);
1453 define_one_global_rw(max_perf_pct);
1454 define_one_global_rw(min_perf_pct);
1455 define_one_global_ro(turbo_pct);
1456 define_one_global_ro(num_pstates);
1457 define_one_global_rw(hwp_dynamic_boost);
1458 define_one_global_rw(energy_efficiency);
1460 static struct attribute *intel_pstate_attributes[] = {
1466 static const struct attribute_group intel_pstate_attr_group = {
1467 .attrs = intel_pstate_attributes,
1470 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1472 static struct kobject *intel_pstate_kobject;
1474 static void __init intel_pstate_sysfs_expose_params(void)
1476 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1480 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1481 put_device(dev_root);
1483 if (WARN_ON(!intel_pstate_kobject))
1486 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1490 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1491 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1494 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1499 * If per cpu limits are enforced there are no global limits, so
1500 * return without creating max/min_perf_pct attributes
1505 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1508 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1511 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1512 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1517 static void __init intel_pstate_sysfs_remove(void)
1519 if (!intel_pstate_kobject)
1522 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1524 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1525 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1526 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1529 if (!per_cpu_limits) {
1530 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1531 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1533 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1534 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1537 kobject_put(intel_pstate_kobject);
1540 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1547 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1551 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1556 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1559 /************************** sysfs end ************************/
1561 static void intel_pstate_notify_work(struct work_struct *work)
1563 struct cpudata *cpudata =
1564 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1565 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1568 intel_pstate_get_hwp_cap(cpudata);
1569 __intel_pstate_update_max_freq(cpudata, policy);
1571 cpufreq_cpu_release(policy);
1574 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1577 static DEFINE_SPINLOCK(hwp_notify_lock);
1578 static cpumask_t hwp_intr_enable_mask;
1580 void notify_hwp_interrupt(void)
1582 unsigned int this_cpu = smp_processor_id();
1583 struct cpudata *cpudata;
1584 unsigned long flags;
1587 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1590 rdmsrl_safe(MSR_HWP_STATUS, &value);
1591 if (!(value & 0x01))
1594 spin_lock_irqsave(&hwp_notify_lock, flags);
1596 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1600 * Currently we never free all_cpu_data. And we can't reach here
1601 * without this allocated. But for safety for future changes, added
1604 if (unlikely(!READ_ONCE(all_cpu_data)))
1608 * The free is done during cleanup, when cpufreq registry is failed.
1609 * We wouldn't be here if it fails on init or switch status. But for
1610 * future changes, added check.
1612 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1613 if (unlikely(!cpudata))
1616 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1618 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1623 wrmsrl_safe(MSR_HWP_STATUS, 0);
1624 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1627 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1629 unsigned long flags;
1631 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1634 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1635 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1637 spin_lock_irqsave(&hwp_notify_lock, flags);
1638 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1639 cancel_delayed_work(&cpudata->hwp_notify_work);
1640 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1643 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1645 /* Enable HWP notification interrupt for guaranteed performance change */
1646 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1647 unsigned long flags;
1649 spin_lock_irqsave(&hwp_notify_lock, flags);
1650 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1651 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1652 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1654 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1655 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1656 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1660 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1662 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1665 * If this CPU gen doesn't call for change in balance_perf
1668 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1672 * If the EPP is set by firmware, which means that firmware enabled HWP
1673 * - Is equal or less than 0x80 (default balance_perf EPP)
1674 * - But less performance oriented than performance EPP
1675 * then use this as new balance_perf EPP.
1677 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1678 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1679 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1684 * Use hard coded value per gen to update the balance_perf
1687 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1688 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1691 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1693 /* First disable HWP notification interrupt till we activate again */
1694 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1695 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1697 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1699 intel_pstate_enable_hwp_interrupt(cpudata);
1701 if (cpudata->epp_default >= 0)
1704 intel_pstate_update_epp_defaults(cpudata);
1707 static int atom_get_min_pstate(int not_used)
1711 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1712 return (value >> 8) & 0x7F;
1715 static int atom_get_max_pstate(int not_used)
1719 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1720 return (value >> 16) & 0x7F;
1723 static int atom_get_turbo_pstate(int not_used)
1727 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1728 return value & 0x7F;
1731 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1737 val = (u64)pstate << 8;
1738 if (global.no_turbo && !global.turbo_disabled)
1739 val |= (u64)1 << 32;
1741 vid_fp = cpudata->vid.min + mul_fp(
1742 int_tofp(pstate - cpudata->pstate.min_pstate),
1743 cpudata->vid.ratio);
1745 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1746 vid = ceiling_fp(vid_fp);
1748 if (pstate > cpudata->pstate.max_pstate)
1749 vid = cpudata->vid.turbo;
1754 static int silvermont_get_scaling(void)
1758 /* Defined in Table 35-6 from SDM (Sept 2015) */
1759 static int silvermont_freq_table[] = {
1760 83300, 100000, 133300, 116700, 80000};
1762 rdmsrl(MSR_FSB_FREQ, value);
1766 return silvermont_freq_table[i];
1769 static int airmont_get_scaling(void)
1773 /* Defined in Table 35-10 from SDM (Sept 2015) */
1774 static int airmont_freq_table[] = {
1775 83300, 100000, 133300, 116700, 80000,
1776 93300, 90000, 88900, 87500};
1778 rdmsrl(MSR_FSB_FREQ, value);
1782 return airmont_freq_table[i];
1785 static void atom_get_vid(struct cpudata *cpudata)
1789 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1790 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1791 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1792 cpudata->vid.ratio = div_fp(
1793 cpudata->vid.max - cpudata->vid.min,
1794 int_tofp(cpudata->pstate.max_pstate -
1795 cpudata->pstate.min_pstate));
1797 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1798 cpudata->vid.turbo = value & 0x7f;
1801 static int core_get_min_pstate(int cpu)
1805 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1806 return (value >> 40) & 0xFF;
1809 static int core_get_max_pstate_physical(int cpu)
1813 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1814 return (value >> 8) & 0xFF;
1817 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1819 /* Check how many TDP levels present */
1820 if (plat_info & 0x600000000) {
1826 /* Get the TDP level (0, 1, 2) to get ratios */
1827 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1831 /* TDP MSR are continuous starting at 0x648 */
1832 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1833 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1837 /* For level 1 and 2, bits[23:16] contain the ratio */
1838 if (tdp_ctrl & 0x03)
1841 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1842 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1844 return (int)tdp_ratio;
1850 static int core_get_max_pstate(int cpu)
1858 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1859 max_pstate = (plat_info >> 8) & 0xFF;
1861 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1866 /* Turbo activation ratio is not used on HWP platforms */
1870 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1874 /* Do some sanity checking for safety */
1875 tar_levels = tar & 0xff;
1876 if (tdp_ratio - 1 == tar_levels) {
1877 max_pstate = tar_levels;
1878 pr_debug("max_pstate=TAC %x\n", max_pstate);
1885 static int core_get_turbo_pstate(int cpu)
1890 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1891 nont = core_get_max_pstate(cpu);
1892 ret = (value) & 255;
1898 static inline int core_get_scaling(void)
1903 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1907 val = (u64)pstate << 8;
1908 if (global.no_turbo && !global.turbo_disabled)
1909 val |= (u64)1 << 32;
1914 static int knl_get_aperf_mperf_shift(void)
1919 static int knl_get_turbo_pstate(int cpu)
1924 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1925 nont = core_get_max_pstate(cpu);
1926 ret = (((value) >> 8) & 0xFF);
1932 static void hybrid_get_type(void *data)
1934 u8 *cpu_type = data;
1936 *cpu_type = get_this_hybrid_cpu_type();
1939 static int hybrid_get_cpu_scaling(int cpu)
1943 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1944 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1945 if (cpu_type == 0x40)
1948 return core_get_scaling();
1951 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1953 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1954 cpu->pstate.current_pstate = pstate;
1956 * Generally, there is no guarantee that this code will always run on
1957 * the CPU being updated, so force the register update to run on the
1960 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1961 pstate_funcs.get_val(cpu, pstate));
1964 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1966 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1969 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1971 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1973 update_turbo_state();
1974 intel_pstate_set_pstate(cpu, pstate);
1977 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1979 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
1980 int perf_ctl_scaling = pstate_funcs.get_scaling();
1982 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
1983 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
1984 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
1986 if (hwp_active && !hwp_mode_bdw) {
1987 __intel_pstate_get_hwp_cap(cpu);
1989 if (pstate_funcs.get_cpu_scaling) {
1990 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
1991 if (cpu->pstate.scaling != perf_ctl_scaling)
1992 intel_pstate_hybrid_hwp_adjust(cpu);
1994 cpu->pstate.scaling = perf_ctl_scaling;
1997 cpu->pstate.scaling = perf_ctl_scaling;
1998 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
1999 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2002 if (cpu->pstate.scaling == perf_ctl_scaling) {
2003 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2004 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2005 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2008 if (pstate_funcs.get_aperf_mperf_shift)
2009 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2011 if (pstate_funcs.get_vid)
2012 pstate_funcs.get_vid(cpu);
2014 intel_pstate_set_min_pstate(cpu);
2018 * Long hold time will keep high perf limits for long time,
2019 * which negatively impacts perf/watt for some workloads,
2020 * like specpower. 3ms is based on experiements on some
2023 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2025 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2027 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2028 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2029 u32 max_limit = (hwp_req & 0xff00) >> 8;
2030 u32 min_limit = (hwp_req & 0xff);
2034 * Cases to consider (User changes via sysfs or boot time):
2035 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2037 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2038 * Should result in one level boost only for P0.
2039 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2040 * Should result in two level boost:
2041 * (min + p1)/2 and P1.
2042 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2043 * Should result in three level boost:
2044 * (min + p1)/2, P1 and P0.
2047 /* If max and min are equal or already at max, nothing to boost */
2048 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2051 if (!cpu->hwp_boost_min)
2052 cpu->hwp_boost_min = min_limit;
2054 /* level at half way mark between min and guranteed */
2055 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2057 if (cpu->hwp_boost_min < boost_level1)
2058 cpu->hwp_boost_min = boost_level1;
2059 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2060 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2061 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2062 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2063 cpu->hwp_boost_min = max_limit;
2067 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2068 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2069 cpu->last_update = cpu->sample.time;
2072 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2074 if (cpu->hwp_boost_min) {
2077 /* Check if we are idle for hold time to boost down */
2078 expired = time_after64(cpu->sample.time, cpu->last_update +
2079 hwp_boost_hold_time_ns);
2081 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2082 cpu->hwp_boost_min = 0;
2085 cpu->last_update = cpu->sample.time;
2088 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2091 cpu->sample.time = time;
2093 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2096 cpu->sched_flags = 0;
2098 * Set iowait_boost flag and update time. Since IO WAIT flag
2099 * is set all the time, we can't just conclude that there is
2100 * some IO bound activity is scheduled on this CPU with just
2101 * one occurrence. If we receive at least two in two
2102 * consecutive ticks, then we treat as boost candidate.
2104 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2107 cpu->last_io_update = time;
2110 intel_pstate_hwp_boost_up(cpu);
2113 intel_pstate_hwp_boost_down(cpu);
2117 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2118 u64 time, unsigned int flags)
2120 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2122 cpu->sched_flags |= flags;
2124 if (smp_processor_id() == cpu->cpu)
2125 intel_pstate_update_util_hwp_local(cpu, time);
2128 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2130 struct sample *sample = &cpu->sample;
2132 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2135 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2138 unsigned long flags;
2141 local_irq_save(flags);
2142 rdmsrl(MSR_IA32_APERF, aperf);
2143 rdmsrl(MSR_IA32_MPERF, mperf);
2145 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2146 local_irq_restore(flags);
2149 local_irq_restore(flags);
2151 cpu->last_sample_time = cpu->sample.time;
2152 cpu->sample.time = time;
2153 cpu->sample.aperf = aperf;
2154 cpu->sample.mperf = mperf;
2155 cpu->sample.tsc = tsc;
2156 cpu->sample.aperf -= cpu->prev_aperf;
2157 cpu->sample.mperf -= cpu->prev_mperf;
2158 cpu->sample.tsc -= cpu->prev_tsc;
2160 cpu->prev_aperf = aperf;
2161 cpu->prev_mperf = mperf;
2162 cpu->prev_tsc = tsc;
2164 * First time this function is invoked in a given cycle, all of the
2165 * previous sample data fields are equal to zero or stale and they must
2166 * be populated with meaningful numbers for things to work, so assume
2167 * that sample.time will always be reset before setting the utilization
2168 * update hook and make the caller skip the sample then.
2170 if (cpu->last_sample_time) {
2171 intel_pstate_calc_avg_perf(cpu);
2177 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2179 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2182 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2184 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2185 cpu->sample.core_avg_perf);
2188 static inline int32_t get_target_pstate(struct cpudata *cpu)
2190 struct sample *sample = &cpu->sample;
2192 int target, avg_pstate;
2194 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2197 if (busy_frac < cpu->iowait_boost)
2198 busy_frac = cpu->iowait_boost;
2200 sample->busy_scaled = busy_frac * 100;
2202 target = global.no_turbo || global.turbo_disabled ?
2203 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2204 target += target >> 2;
2205 target = mul_fp(target, busy_frac);
2206 if (target < cpu->pstate.min_pstate)
2207 target = cpu->pstate.min_pstate;
2210 * If the average P-state during the previous cycle was higher than the
2211 * current target, add 50% of the difference to the target to reduce
2212 * possible performance oscillations and offset possible performance
2213 * loss related to moving the workload from one CPU to another within
2216 avg_pstate = get_avg_pstate(cpu);
2217 if (avg_pstate > target)
2218 target += (avg_pstate - target) >> 1;
2223 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2225 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2226 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2228 return clamp_t(int, pstate, min_pstate, max_pstate);
2231 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2233 if (pstate == cpu->pstate.current_pstate)
2236 cpu->pstate.current_pstate = pstate;
2237 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2240 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2242 int from = cpu->pstate.current_pstate;
2243 struct sample *sample;
2246 update_turbo_state();
2248 target_pstate = get_target_pstate(cpu);
2249 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2250 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2251 intel_pstate_update_pstate(cpu, target_pstate);
2253 sample = &cpu->sample;
2254 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2255 fp_toint(sample->busy_scaled),
2257 cpu->pstate.current_pstate,
2261 get_avg_frequency(cpu),
2262 fp_toint(cpu->iowait_boost * 100));
2265 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2268 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2271 /* Don't allow remote callbacks */
2272 if (smp_processor_id() != cpu->cpu)
2275 delta_ns = time - cpu->last_update;
2276 if (flags & SCHED_CPUFREQ_IOWAIT) {
2277 /* Start over if the CPU may have been idle. */
2278 if (delta_ns > TICK_NSEC) {
2279 cpu->iowait_boost = ONE_EIGHTH_FP;
2280 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2281 cpu->iowait_boost <<= 1;
2282 if (cpu->iowait_boost > int_tofp(1))
2283 cpu->iowait_boost = int_tofp(1);
2285 cpu->iowait_boost = ONE_EIGHTH_FP;
2287 } else if (cpu->iowait_boost) {
2288 /* Clear iowait_boost if the CPU may have been idle. */
2289 if (delta_ns > TICK_NSEC)
2290 cpu->iowait_boost = 0;
2292 cpu->iowait_boost >>= 1;
2294 cpu->last_update = time;
2295 delta_ns = time - cpu->sample.time;
2296 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2299 if (intel_pstate_sample(cpu, time))
2300 intel_pstate_adjust_pstate(cpu);
2303 static struct pstate_funcs core_funcs = {
2304 .get_max = core_get_max_pstate,
2305 .get_max_physical = core_get_max_pstate_physical,
2306 .get_min = core_get_min_pstate,
2307 .get_turbo = core_get_turbo_pstate,
2308 .get_scaling = core_get_scaling,
2309 .get_val = core_get_val,
2312 static const struct pstate_funcs silvermont_funcs = {
2313 .get_max = atom_get_max_pstate,
2314 .get_max_physical = atom_get_max_pstate,
2315 .get_min = atom_get_min_pstate,
2316 .get_turbo = atom_get_turbo_pstate,
2317 .get_val = atom_get_val,
2318 .get_scaling = silvermont_get_scaling,
2319 .get_vid = atom_get_vid,
2322 static const struct pstate_funcs airmont_funcs = {
2323 .get_max = atom_get_max_pstate,
2324 .get_max_physical = atom_get_max_pstate,
2325 .get_min = atom_get_min_pstate,
2326 .get_turbo = atom_get_turbo_pstate,
2327 .get_val = atom_get_val,
2328 .get_scaling = airmont_get_scaling,
2329 .get_vid = atom_get_vid,
2332 static const struct pstate_funcs knl_funcs = {
2333 .get_max = core_get_max_pstate,
2334 .get_max_physical = core_get_max_pstate_physical,
2335 .get_min = core_get_min_pstate,
2336 .get_turbo = knl_get_turbo_pstate,
2337 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2338 .get_scaling = core_get_scaling,
2339 .get_val = core_get_val,
2342 #define X86_MATCH(model, policy) \
2343 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2344 X86_FEATURE_APERFMPERF, &policy)
2346 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2347 X86_MATCH(SANDYBRIDGE, core_funcs),
2348 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2349 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2350 X86_MATCH(IVYBRIDGE, core_funcs),
2351 X86_MATCH(HASWELL, core_funcs),
2352 X86_MATCH(BROADWELL, core_funcs),
2353 X86_MATCH(IVYBRIDGE_X, core_funcs),
2354 X86_MATCH(HASWELL_X, core_funcs),
2355 X86_MATCH(HASWELL_L, core_funcs),
2356 X86_MATCH(HASWELL_G, core_funcs),
2357 X86_MATCH(BROADWELL_G, core_funcs),
2358 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2359 X86_MATCH(SKYLAKE_L, core_funcs),
2360 X86_MATCH(BROADWELL_X, core_funcs),
2361 X86_MATCH(SKYLAKE, core_funcs),
2362 X86_MATCH(BROADWELL_D, core_funcs),
2363 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2364 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2365 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2366 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2367 X86_MATCH(SKYLAKE_X, core_funcs),
2368 X86_MATCH(COMETLAKE, core_funcs),
2369 X86_MATCH(ICELAKE_X, core_funcs),
2370 X86_MATCH(TIGERLAKE, core_funcs),
2371 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2374 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2376 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2377 X86_MATCH(BROADWELL_D, core_funcs),
2378 X86_MATCH(BROADWELL_X, core_funcs),
2379 X86_MATCH(SKYLAKE_X, core_funcs),
2380 X86_MATCH(ICELAKE_X, core_funcs),
2381 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2385 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2386 X86_MATCH(KABYLAKE, core_funcs),
2390 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2391 X86_MATCH(SKYLAKE_X, core_funcs),
2392 X86_MATCH(SKYLAKE, core_funcs),
2396 static int intel_pstate_init_cpu(unsigned int cpunum)
2398 struct cpudata *cpu;
2400 cpu = all_cpu_data[cpunum];
2403 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2407 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2411 cpu->epp_default = -EINVAL;
2414 const struct x86_cpu_id *id;
2416 intel_pstate_hwp_enable(cpu);
2418 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2419 if (id && intel_pstate_acpi_pm_profile_server())
2422 } else if (hwp_active) {
2424 * Re-enable HWP in case this happens after a resume from ACPI
2425 * S3 if the CPU was offline during the whole system/resume
2428 intel_pstate_hwp_reenable(cpu);
2431 cpu->epp_powersave = -EINVAL;
2432 cpu->epp_policy = 0;
2434 intel_pstate_get_cpu_pstates(cpu);
2436 pr_debug("controlling: cpu %d\n", cpunum);
2441 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2443 struct cpudata *cpu = all_cpu_data[cpu_num];
2445 if (hwp_active && !hwp_boost)
2448 if (cpu->update_util_set)
2451 /* Prevent intel_pstate_update_util() from using stale data. */
2452 cpu->sample.time = 0;
2453 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2455 intel_pstate_update_util_hwp :
2456 intel_pstate_update_util));
2457 cpu->update_util_set = true;
2460 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2462 struct cpudata *cpu_data = all_cpu_data[cpu];
2464 if (!cpu_data->update_util_set)
2467 cpufreq_remove_update_util_hook(cpu);
2468 cpu_data->update_util_set = false;
2472 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2474 return global.turbo_disabled || global.no_turbo ?
2475 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2478 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2479 unsigned int policy_min,
2480 unsigned int policy_max)
2482 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2483 int32_t max_policy_perf, min_policy_perf;
2485 max_policy_perf = policy_max / perf_ctl_scaling;
2486 if (policy_max == policy_min) {
2487 min_policy_perf = max_policy_perf;
2489 min_policy_perf = policy_min / perf_ctl_scaling;
2490 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2491 0, max_policy_perf);
2495 * HWP needs some special consideration, because HWP_REQUEST uses
2496 * abstract values to represent performance rather than pure ratios.
2498 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2499 int scaling = cpu->pstate.scaling;
2502 freq = max_policy_perf * perf_ctl_scaling;
2503 max_policy_perf = DIV_ROUND_UP(freq, scaling);
2504 freq = min_policy_perf * perf_ctl_scaling;
2505 min_policy_perf = DIV_ROUND_UP(freq, scaling);
2508 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2509 cpu->cpu, min_policy_perf, max_policy_perf);
2511 /* Normalize user input to [min_perf, max_perf] */
2512 if (per_cpu_limits) {
2513 cpu->min_perf_ratio = min_policy_perf;
2514 cpu->max_perf_ratio = max_policy_perf;
2516 int turbo_max = cpu->pstate.turbo_pstate;
2517 int32_t global_min, global_max;
2519 /* Global limits are in percent of the maximum turbo P-state. */
2520 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2521 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2522 global_min = clamp_t(int32_t, global_min, 0, global_max);
2524 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2525 global_min, global_max);
2527 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2528 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2529 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2530 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2532 /* Make sure min_perf <= max_perf */
2533 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2534 cpu->max_perf_ratio);
2537 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2538 cpu->max_perf_ratio,
2539 cpu->min_perf_ratio);
2542 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2544 struct cpudata *cpu;
2546 if (!policy->cpuinfo.max_freq)
2549 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2550 policy->cpuinfo.max_freq, policy->max);
2552 cpu = all_cpu_data[policy->cpu];
2553 cpu->policy = policy->policy;
2555 mutex_lock(&intel_pstate_limits_lock);
2557 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2559 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2561 * NOHZ_FULL CPUs need this as the governor callback may not
2562 * be invoked on them.
2564 intel_pstate_clear_update_util_hook(policy->cpu);
2565 intel_pstate_max_within_limits(cpu);
2567 intel_pstate_set_update_util_hook(policy->cpu);
2572 * When hwp_boost was active before and dynamically it
2573 * was turned off, in that case we need to clear the
2577 intel_pstate_clear_update_util_hook(policy->cpu);
2578 intel_pstate_hwp_set(policy->cpu);
2581 mutex_unlock(&intel_pstate_limits_lock);
2586 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2587 struct cpufreq_policy_data *policy)
2590 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2591 policy->max < policy->cpuinfo.max_freq &&
2592 policy->max > cpu->pstate.max_freq) {
2593 pr_debug("policy->max > max non turbo frequency\n");
2594 policy->max = policy->cpuinfo.max_freq;
2598 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2599 struct cpufreq_policy_data *policy)
2603 update_turbo_state();
2605 intel_pstate_get_hwp_cap(cpu);
2606 max_freq = global.no_turbo || global.turbo_disabled ?
2607 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2609 max_freq = intel_pstate_get_max_freq(cpu);
2611 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2613 intel_pstate_adjust_policy_max(cpu, policy);
2616 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2618 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2623 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2625 struct cpudata *cpu = all_cpu_data[policy->cpu];
2627 pr_debug("CPU %d going offline\n", cpu->cpu);
2633 * If the CPU is an SMT thread and it goes offline with the performance
2634 * settings different from the minimum, it will prevent its sibling
2635 * from getting to lower performance levels, so force the minimum
2636 * performance on CPU offline to prevent that from happening.
2639 intel_pstate_hwp_offline(cpu);
2641 intel_pstate_set_min_pstate(cpu);
2643 intel_pstate_exit_perf_limits(policy);
2648 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2650 struct cpudata *cpu = all_cpu_data[policy->cpu];
2652 pr_debug("CPU %d going online\n", cpu->cpu);
2654 intel_pstate_init_acpi_perf_limits(policy);
2658 * Re-enable HWP and clear the "suspended" flag to let "resume"
2659 * know that it need not do that.
2661 intel_pstate_hwp_reenable(cpu);
2662 cpu->suspended = false;
2668 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2670 intel_pstate_clear_update_util_hook(policy->cpu);
2672 return intel_cpufreq_cpu_offline(policy);
2675 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2677 pr_debug("CPU %d exiting\n", policy->cpu);
2679 policy->fast_switch_possible = false;
2684 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2686 struct cpudata *cpu;
2689 rc = intel_pstate_init_cpu(policy->cpu);
2693 cpu = all_cpu_data[policy->cpu];
2695 cpu->max_perf_ratio = 0xFF;
2696 cpu->min_perf_ratio = 0;
2698 /* cpuinfo and default policy values */
2699 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2700 update_turbo_state();
2701 global.turbo_disabled_mf = global.turbo_disabled;
2702 policy->cpuinfo.max_freq = global.turbo_disabled ?
2703 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2705 policy->min = policy->cpuinfo.min_freq;
2706 policy->max = policy->cpuinfo.max_freq;
2708 intel_pstate_init_acpi_perf_limits(policy);
2710 policy->fast_switch_possible = true;
2715 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2717 int ret = __intel_pstate_cpu_init(policy);
2723 * Set the policy to powersave to provide a valid fallback value in case
2724 * the default cpufreq governor is neither powersave nor performance.
2726 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2729 struct cpudata *cpu = all_cpu_data[policy->cpu];
2731 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2737 static struct cpufreq_driver intel_pstate = {
2738 .flags = CPUFREQ_CONST_LOOPS,
2739 .verify = intel_pstate_verify_policy,
2740 .setpolicy = intel_pstate_set_policy,
2741 .suspend = intel_pstate_suspend,
2742 .resume = intel_pstate_resume,
2743 .init = intel_pstate_cpu_init,
2744 .exit = intel_pstate_cpu_exit,
2745 .offline = intel_pstate_cpu_offline,
2746 .online = intel_pstate_cpu_online,
2747 .update_limits = intel_pstate_update_limits,
2748 .name = "intel_pstate",
2751 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2753 struct cpudata *cpu = all_cpu_data[policy->cpu];
2755 intel_pstate_verify_cpu_policy(cpu, policy);
2756 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2761 /* Use of trace in passive mode:
2763 * In passive mode the trace core_busy field (also known as the
2764 * performance field, and lablelled as such on the graphs; also known as
2765 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2766 * driver call was via the normal or fast switch path. Various graphs
2767 * output from the intel_pstate_tracer.py utility that include core_busy
2768 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2769 * so we use 10 to indicate the normal path through the driver, and
2770 * 90 to indicate the fast switch path through the driver.
2771 * The scaled_busy field is not used, and is set to 0.
2774 #define INTEL_PSTATE_TRACE_TARGET 10
2775 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2777 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2779 struct sample *sample;
2781 if (!trace_pstate_sample_enabled())
2784 if (!intel_pstate_sample(cpu, ktime_get()))
2787 sample = &cpu->sample;
2788 trace_pstate_sample(trace_type,
2791 cpu->pstate.current_pstate,
2795 get_avg_frequency(cpu),
2796 fp_toint(cpu->iowait_boost * 100));
2799 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2800 u32 desired, bool fast_switch)
2802 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2804 value &= ~HWP_MIN_PERF(~0L);
2805 value |= HWP_MIN_PERF(min);
2807 value &= ~HWP_MAX_PERF(~0L);
2808 value |= HWP_MAX_PERF(max);
2810 value &= ~HWP_DESIRED_PERF(~0L);
2811 value |= HWP_DESIRED_PERF(desired);
2816 WRITE_ONCE(cpu->hwp_req_cached, value);
2818 wrmsrl(MSR_HWP_REQUEST, value);
2820 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2823 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2824 u32 target_pstate, bool fast_switch)
2827 wrmsrl(MSR_IA32_PERF_CTL,
2828 pstate_funcs.get_val(cpu, target_pstate));
2830 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2831 pstate_funcs.get_val(cpu, target_pstate));
2834 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2835 int target_pstate, bool fast_switch)
2837 struct cpudata *cpu = all_cpu_data[policy->cpu];
2838 int old_pstate = cpu->pstate.current_pstate;
2840 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2842 int max_pstate = policy->strict_target ?
2843 target_pstate : cpu->max_perf_ratio;
2845 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2847 } else if (target_pstate != old_pstate) {
2848 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2851 cpu->pstate.current_pstate = target_pstate;
2853 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2854 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2856 return target_pstate;
2859 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2860 unsigned int target_freq,
2861 unsigned int relation)
2863 struct cpudata *cpu = all_cpu_data[policy->cpu];
2864 struct cpufreq_freqs freqs;
2867 update_turbo_state();
2869 freqs.old = policy->cur;
2870 freqs.new = target_freq;
2872 cpufreq_freq_transition_begin(policy, &freqs);
2875 case CPUFREQ_RELATION_L:
2876 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2878 case CPUFREQ_RELATION_H:
2879 target_pstate = freqs.new / cpu->pstate.scaling;
2882 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2886 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2888 freqs.new = target_pstate * cpu->pstate.scaling;
2890 cpufreq_freq_transition_end(policy, &freqs, false);
2895 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2896 unsigned int target_freq)
2898 struct cpudata *cpu = all_cpu_data[policy->cpu];
2901 update_turbo_state();
2903 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2905 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2907 return target_pstate * cpu->pstate.scaling;
2910 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2911 unsigned long min_perf,
2912 unsigned long target_perf,
2913 unsigned long capacity)
2915 struct cpudata *cpu = all_cpu_data[cpunum];
2916 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2917 int old_pstate = cpu->pstate.current_pstate;
2918 int cap_pstate, min_pstate, max_pstate, target_pstate;
2920 update_turbo_state();
2921 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2922 HWP_HIGHEST_PERF(hwp_cap);
2924 /* Optimization: Avoid unnecessary divisions. */
2926 target_pstate = cap_pstate;
2927 if (target_perf < capacity)
2928 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2930 min_pstate = cap_pstate;
2931 if (min_perf < capacity)
2932 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2934 if (min_pstate < cpu->pstate.min_pstate)
2935 min_pstate = cpu->pstate.min_pstate;
2937 if (min_pstate < cpu->min_perf_ratio)
2938 min_pstate = cpu->min_perf_ratio;
2940 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2941 if (max_pstate < min_pstate)
2942 max_pstate = min_pstate;
2944 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2946 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2948 cpu->pstate.current_pstate = target_pstate;
2949 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2952 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2954 struct freq_qos_request *req;
2955 struct cpudata *cpu;
2959 dev = get_cpu_device(policy->cpu);
2963 ret = __intel_pstate_cpu_init(policy);
2967 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2968 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2969 policy->cur = policy->cpuinfo.min_freq;
2971 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2977 cpu = all_cpu_data[policy->cpu];
2982 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2984 intel_pstate_get_hwp_cap(cpu);
2986 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2987 WRITE_ONCE(cpu->hwp_req_cached, value);
2989 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
2991 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2994 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
2996 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2999 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3003 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3005 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3008 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3009 goto remove_min_req;
3012 policy->driver_data = req;
3017 freq_qos_remove_request(req);
3021 intel_pstate_exit_perf_limits(policy);
3026 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3028 struct freq_qos_request *req;
3030 req = policy->driver_data;
3032 freq_qos_remove_request(req + 1);
3033 freq_qos_remove_request(req);
3036 return intel_pstate_cpu_exit(policy);
3039 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3041 intel_pstate_suspend(policy);
3044 struct cpudata *cpu = all_cpu_data[policy->cpu];
3045 u64 value = READ_ONCE(cpu->hwp_req_cached);
3048 * Clear the desired perf field in MSR_HWP_REQUEST in case
3049 * intel_cpufreq_adjust_perf() is in use and the last value
3050 * written by it may not be suitable.
3052 value &= ~HWP_DESIRED_PERF(~0L);
3053 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3054 WRITE_ONCE(cpu->hwp_req_cached, value);
3060 static struct cpufreq_driver intel_cpufreq = {
3061 .flags = CPUFREQ_CONST_LOOPS,
3062 .verify = intel_cpufreq_verify_policy,
3063 .target = intel_cpufreq_target,
3064 .fast_switch = intel_cpufreq_fast_switch,
3065 .init = intel_cpufreq_cpu_init,
3066 .exit = intel_cpufreq_cpu_exit,
3067 .offline = intel_cpufreq_cpu_offline,
3068 .online = intel_pstate_cpu_online,
3069 .suspend = intel_cpufreq_suspend,
3070 .resume = intel_pstate_resume,
3071 .update_limits = intel_pstate_update_limits,
3072 .name = "intel_cpufreq",
3075 static struct cpufreq_driver *default_driver;
3077 static void intel_pstate_driver_cleanup(void)
3082 for_each_online_cpu(cpu) {
3083 if (all_cpu_data[cpu]) {
3084 if (intel_pstate_driver == &intel_pstate)
3085 intel_pstate_clear_update_util_hook(cpu);
3087 spin_lock(&hwp_notify_lock);
3088 kfree(all_cpu_data[cpu]);
3089 WRITE_ONCE(all_cpu_data[cpu], NULL);
3090 spin_unlock(&hwp_notify_lock);
3095 intel_pstate_driver = NULL;
3098 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3102 if (driver == &intel_pstate)
3103 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3105 memset(&global, 0, sizeof(global));
3106 global.max_perf_pct = 100;
3108 intel_pstate_driver = driver;
3109 ret = cpufreq_register_driver(intel_pstate_driver);
3111 intel_pstate_driver_cleanup();
3115 global.min_perf_pct = min_perf_pct_min();
3120 static ssize_t intel_pstate_show_status(char *buf)
3122 if (!intel_pstate_driver)
3123 return sprintf(buf, "off\n");
3125 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3126 "active" : "passive");
3129 static int intel_pstate_update_status(const char *buf, size_t size)
3131 if (size == 3 && !strncmp(buf, "off", size)) {
3132 if (!intel_pstate_driver)
3138 cpufreq_unregister_driver(intel_pstate_driver);
3139 intel_pstate_driver_cleanup();
3143 if (size == 6 && !strncmp(buf, "active", size)) {
3144 if (intel_pstate_driver) {
3145 if (intel_pstate_driver == &intel_pstate)
3148 cpufreq_unregister_driver(intel_pstate_driver);
3151 return intel_pstate_register_driver(&intel_pstate);
3154 if (size == 7 && !strncmp(buf, "passive", size)) {
3155 if (intel_pstate_driver) {
3156 if (intel_pstate_driver == &intel_cpufreq)
3159 cpufreq_unregister_driver(intel_pstate_driver);
3160 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3163 return intel_pstate_register_driver(&intel_cpufreq);
3169 static int no_load __initdata;
3170 static int no_hwp __initdata;
3171 static int hwp_only __initdata;
3172 static unsigned int force_load __initdata;
3174 static int __init intel_pstate_msrs_not_valid(void)
3176 if (!pstate_funcs.get_max(0) ||
3177 !pstate_funcs.get_min(0) ||
3178 !pstate_funcs.get_turbo(0))
3184 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3186 pstate_funcs.get_max = funcs->get_max;
3187 pstate_funcs.get_max_physical = funcs->get_max_physical;
3188 pstate_funcs.get_min = funcs->get_min;
3189 pstate_funcs.get_turbo = funcs->get_turbo;
3190 pstate_funcs.get_scaling = funcs->get_scaling;
3191 pstate_funcs.get_val = funcs->get_val;
3192 pstate_funcs.get_vid = funcs->get_vid;
3193 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3198 static bool __init intel_pstate_no_acpi_pss(void)
3202 for_each_possible_cpu(i) {
3204 union acpi_object *pss;
3205 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3206 struct acpi_processor *pr = per_cpu(processors, i);
3211 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3212 if (ACPI_FAILURE(status))
3215 pss = buffer.pointer;
3216 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3224 pr_debug("ACPI _PSS not found\n");
3228 static bool __init intel_pstate_no_acpi_pcch(void)
3233 status = acpi_get_handle(NULL, "\\_SB", &handle);
3234 if (ACPI_FAILURE(status))
3237 if (acpi_has_method(handle, "PCCH"))
3241 pr_debug("ACPI PCCH not found\n");
3245 static bool __init intel_pstate_has_acpi_ppc(void)
3249 for_each_possible_cpu(i) {
3250 struct acpi_processor *pr = per_cpu(processors, i);
3254 if (acpi_has_method(pr->handle, "_PPC"))
3257 pr_debug("ACPI _PPC not found\n");
3266 /* Hardware vendor-specific info that has its own power management modes */
3267 static struct acpi_platform_list plat_info[] __initdata = {
3268 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3269 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3270 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3271 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3272 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3273 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3274 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3275 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3276 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3277 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3278 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3279 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3280 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3281 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3282 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3286 #define BITMASK_OOB (BIT(8) | BIT(18))
3288 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3290 const struct x86_cpu_id *id;
3294 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3296 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3297 if (misc_pwr & BITMASK_OOB) {
3298 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3299 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3304 idx = acpi_match_platform_list(plat_info);
3308 switch (plat_info[idx].data) {
3310 if (!intel_pstate_no_acpi_pss())
3313 return intel_pstate_no_acpi_pcch();
3315 return intel_pstate_has_acpi_ppc() && !force_load;
3321 static void intel_pstate_request_control_from_smm(void)
3324 * It may be unsafe to request P-states control from SMM if _PPC support
3325 * has not been enabled.
3328 acpi_processor_pstate_control();
3330 #else /* CONFIG_ACPI not enabled */
3331 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3332 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3333 static inline void intel_pstate_request_control_from_smm(void) {}
3334 #endif /* CONFIG_ACPI */
3336 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3338 #define X86_MATCH_HWP(model, hwp_mode) \
3339 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3340 X86_FEATURE_HWP, hwp_mode)
3342 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3343 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3344 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3345 X86_MATCH_HWP(ANY, 0),
3349 static bool intel_pstate_hwp_is_enabled(void)
3353 rdmsrl(MSR_PM_ENABLE, value);
3354 return !!(value & 0x1);
3357 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3359 * Set EPP value as 102, this is the max suggested EPP
3360 * which can result in one core turbo frequency for
3361 * AlderLake Mobile CPUs.
3363 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3364 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3368 static int __init intel_pstate_init(void)
3370 static struct cpudata **_all_cpu_data;
3371 const struct x86_cpu_id *id;
3374 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3377 id = x86_match_cpu(hwp_support_ids);
3379 hwp_forced = intel_pstate_hwp_is_enabled();
3382 pr_info("HWP enabled by BIOS\n");
3386 copy_cpu_funcs(&core_funcs);
3388 * Avoid enabling HWP for processors without EPP support,
3389 * because that means incomplete HWP implementation which is a
3390 * corner case and supporting it is generally problematic.
3392 * If HWP is enabled already, though, there is no choice but to
3395 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3396 WRITE_ONCE(hwp_active, 1);
3397 hwp_mode_bdw = id->driver_data;
3398 intel_pstate.attr = hwp_cpufreq_attrs;
3399 intel_cpufreq.attr = hwp_cpufreq_attrs;
3400 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3401 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3402 if (!default_driver)
3403 default_driver = &intel_pstate;
3405 if (boot_cpu_has(X86_FEATURE_HYBRID_CPU))
3406 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling;
3408 goto hwp_cpu_matched;
3410 pr_info("HWP not enabled\n");
3415 id = x86_match_cpu(intel_pstate_cpu_ids);
3417 pr_info("CPU model not supported\n");
3421 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3424 if (intel_pstate_msrs_not_valid()) {
3425 pr_info("Invalid MSRs\n");
3428 /* Without HWP start in the passive mode. */
3429 if (!default_driver)
3430 default_driver = &intel_cpufreq;
3434 * The Intel pstate driver will be ignored if the platform
3435 * firmware has its own power management modes.
3437 if (intel_pstate_platform_pwr_mgmt_exists()) {
3438 pr_info("P-states controlled by the platform\n");
3442 if (!hwp_active && hwp_only)
3445 pr_info("Intel P-state driver initializing\n");
3447 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3451 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3453 intel_pstate_request_control_from_smm();
3455 intel_pstate_sysfs_expose_params();
3458 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3461 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3464 mutex_lock(&intel_pstate_driver_lock);
3465 rc = intel_pstate_register_driver(default_driver);
3466 mutex_unlock(&intel_pstate_driver_lock);
3468 intel_pstate_sysfs_remove();
3473 const struct x86_cpu_id *id;
3475 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3477 set_power_ctl_ee_state(false);
3478 pr_info("Disabling energy efficiency optimization\n");
3481 pr_info("HWP enabled\n");
3482 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3483 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3488 device_initcall(intel_pstate_init);
3490 static int __init intel_pstate_setup(char *str)
3495 if (!strcmp(str, "disable"))
3497 else if (!strcmp(str, "active"))
3498 default_driver = &intel_pstate;
3499 else if (!strcmp(str, "passive"))
3500 default_driver = &intel_cpufreq;
3502 if (!strcmp(str, "no_hwp"))
3505 if (!strcmp(str, "force"))
3507 if (!strcmp(str, "hwp_only"))
3509 if (!strcmp(str, "per_cpu_perf_limits"))
3510 per_cpu_limits = true;
3513 if (!strcmp(str, "support_acpi_ppc"))
3519 early_param("intel_pstate", intel_pstate_setup);
3521 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3522 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");