1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * amd-pstate.c - AMD Processor P-state Frequency Driver
5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All Rights Reserved.
7 * Author: Huang Rui <ray.huang@amd.com>
9 * AMD P-State introduces a new CPU performance scaling design for AMD
10 * processors using the ACPI Collaborative Performance and Power Control (CPPC)
11 * feature which works with the AMD SMU firmware providing a finer grained
12 * frequency control range. It is to replace the legacy ACPI P-States control,
13 * allows a flexible, low-latency interface for the Linux kernel to directly
14 * communicate the performance hints to hardware.
16 * AMD P-State is supported on recent AMD Zen base CPU series include some of
17 * Zen2 and Zen3 processors. _CPC needs to be present in the ACPI tables of AMD
18 * P-State supported system. And there are two types of hardware implementations
19 * for AMD P-State: 1) Full MSR Solution and 2) Shared Memory Solution.
20 * X86_FEATURE_CPPC CPU feature flag is used to distinguish the different types.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/smp.h>
29 #include <linux/sched.h>
30 #include <linux/cpufreq.h>
31 #include <linux/compiler.h>
32 #include <linux/dmi.h>
33 #include <linux/slab.h>
34 #include <linux/acpi.h>
36 #include <linux/delay.h>
37 #include <linux/uaccess.h>
38 #include <linux/static_call.h>
39 #include <linux/amd-pstate.h>
41 #include <acpi/processor.h>
42 #include <acpi/cppc_acpi.h>
45 #include <asm/processor.h>
46 #include <asm/cpufeature.h>
47 #include <asm/cpu_device_id.h>
48 #include "amd-pstate-trace.h"
50 #define AMD_PSTATE_TRANSITION_LATENCY 20000
51 #define AMD_PSTATE_TRANSITION_DELAY 1000
54 * TODO: We need more time to fine tune processors with shared memory solution
55 * with community together.
57 * There are some performance drops on the CPU benchmarks which reports from
58 * Suse. We are co-working with them to fine tune the shared memory solution. So
59 * we disable it by default to go acpi-cpufreq on these processors and add a
60 * module parameter to be able to enable it manually for debugging.
62 static struct cpufreq_driver amd_pstate_driver;
63 static int cppc_load __initdata;
65 static inline int pstate_enable(bool enable)
67 return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
70 static int cppc_enable(bool enable)
74 for_each_present_cpu(cpu) {
75 ret = cppc_set_enable(cpu, enable);
83 DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
85 static inline int amd_pstate_enable(bool enable)
87 return static_call(amd_pstate_enable)(enable);
90 static int pstate_init_perf(struct amd_cpudata *cpudata)
95 int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
101 * TODO: Introduce AMD specific power feature.
103 * CPPC entry doesn't indicate the highest performance in some ASICs.
105 highest_perf = amd_get_highest_perf();
106 if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1))
107 highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
109 WRITE_ONCE(cpudata->highest_perf, highest_perf);
111 WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
112 WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
113 WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
118 static int cppc_init_perf(struct amd_cpudata *cpudata)
120 struct cppc_perf_caps cppc_perf;
123 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
127 highest_perf = amd_get_highest_perf();
128 if (highest_perf > cppc_perf.highest_perf)
129 highest_perf = cppc_perf.highest_perf;
131 WRITE_ONCE(cpudata->highest_perf, highest_perf);
133 WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
134 WRITE_ONCE(cpudata->lowest_nonlinear_perf,
135 cppc_perf.lowest_nonlinear_perf);
136 WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
141 DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
143 static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
145 return static_call(amd_pstate_init_perf)(cpudata);
148 static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
149 u32 des_perf, u32 max_perf, bool fast_switch)
152 wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached));
154 wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
155 READ_ONCE(cpudata->cppc_req_cached));
158 static void cppc_update_perf(struct amd_cpudata *cpudata,
159 u32 min_perf, u32 des_perf,
160 u32 max_perf, bool fast_switch)
162 struct cppc_perf_ctrls perf_ctrls;
164 perf_ctrls.max_perf = max_perf;
165 perf_ctrls.min_perf = min_perf;
166 perf_ctrls.desired_perf = des_perf;
168 cppc_set_perf(cpudata->cpu, &perf_ctrls);
171 DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
173 static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
174 u32 min_perf, u32 des_perf,
175 u32 max_perf, bool fast_switch)
177 static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf,
178 max_perf, fast_switch);
181 static inline bool amd_pstate_sample(struct amd_cpudata *cpudata)
183 u64 aperf, mperf, tsc;
186 local_irq_save(flags);
187 rdmsrl(MSR_IA32_APERF, aperf);
188 rdmsrl(MSR_IA32_MPERF, mperf);
191 if (cpudata->prev.mperf == mperf || cpudata->prev.tsc == tsc) {
192 local_irq_restore(flags);
196 local_irq_restore(flags);
198 cpudata->cur.aperf = aperf;
199 cpudata->cur.mperf = mperf;
200 cpudata->cur.tsc = tsc;
201 cpudata->cur.aperf -= cpudata->prev.aperf;
202 cpudata->cur.mperf -= cpudata->prev.mperf;
203 cpudata->cur.tsc -= cpudata->prev.tsc;
205 cpudata->prev.aperf = aperf;
206 cpudata->prev.mperf = mperf;
207 cpudata->prev.tsc = tsc;
209 cpudata->freq = div64_u64((cpudata->cur.aperf * cpu_khz), cpudata->cur.mperf);
214 static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf,
215 u32 des_perf, u32 max_perf, bool fast_switch)
217 u64 prev = READ_ONCE(cpudata->cppc_req_cached);
220 des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf);
221 value &= ~AMD_CPPC_MIN_PERF(~0L);
222 value |= AMD_CPPC_MIN_PERF(min_perf);
224 value &= ~AMD_CPPC_DES_PERF(~0L);
225 value |= AMD_CPPC_DES_PERF(des_perf);
227 value &= ~AMD_CPPC_MAX_PERF(~0L);
228 value |= AMD_CPPC_MAX_PERF(max_perf);
230 if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
231 trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
232 cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc,
233 cpudata->cpu, (value != prev), fast_switch);
239 WRITE_ONCE(cpudata->cppc_req_cached, value);
241 amd_pstate_update_perf(cpudata, min_perf, des_perf,
242 max_perf, fast_switch);
245 static int amd_pstate_verify(struct cpufreq_policy_data *policy)
247 cpufreq_verify_within_cpu_limits(policy);
252 static int amd_pstate_target(struct cpufreq_policy *policy,
253 unsigned int target_freq,
254 unsigned int relation)
256 struct cpufreq_freqs freqs;
257 struct amd_cpudata *cpudata = policy->driver_data;
258 unsigned long max_perf, min_perf, des_perf, cap_perf;
260 if (!cpudata->max_freq)
263 cap_perf = READ_ONCE(cpudata->highest_perf);
264 min_perf = READ_ONCE(cpudata->lowest_perf);
267 freqs.old = policy->cur;
268 freqs.new = target_freq;
270 des_perf = DIV_ROUND_CLOSEST(target_freq * cap_perf,
273 cpufreq_freq_transition_begin(policy, &freqs);
274 amd_pstate_update(cpudata, min_perf, des_perf,
276 cpufreq_freq_transition_end(policy, &freqs, false);
281 static void amd_pstate_adjust_perf(unsigned int cpu,
282 unsigned long _min_perf,
283 unsigned long target_perf,
284 unsigned long capacity)
286 unsigned long max_perf, min_perf, des_perf,
287 cap_perf, lowest_nonlinear_perf;
288 struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
289 struct amd_cpudata *cpudata = policy->driver_data;
291 cap_perf = READ_ONCE(cpudata->highest_perf);
292 lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
295 if (target_perf < capacity)
296 des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity);
298 min_perf = READ_ONCE(cpudata->highest_perf);
299 if (_min_perf < capacity)
300 min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity);
302 if (min_perf < lowest_nonlinear_perf)
303 min_perf = lowest_nonlinear_perf;
306 if (max_perf < min_perf)
309 amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true);
312 static int amd_get_min_freq(struct amd_cpudata *cpudata)
314 struct cppc_perf_caps cppc_perf;
316 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
321 return cppc_perf.lowest_freq * 1000;
324 static int amd_get_max_freq(struct amd_cpudata *cpudata)
326 struct cppc_perf_caps cppc_perf;
327 u32 max_perf, max_freq, nominal_freq, nominal_perf;
330 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
334 nominal_freq = cppc_perf.nominal_freq;
335 nominal_perf = READ_ONCE(cpudata->nominal_perf);
336 max_perf = READ_ONCE(cpudata->highest_perf);
338 boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT,
341 max_freq = nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT;
344 return max_freq * 1000;
347 static int amd_get_nominal_freq(struct amd_cpudata *cpudata)
349 struct cppc_perf_caps cppc_perf;
351 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
356 return cppc_perf.nominal_freq * 1000;
359 static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata)
361 struct cppc_perf_caps cppc_perf;
362 u32 lowest_nonlinear_freq, lowest_nonlinear_perf,
363 nominal_freq, nominal_perf;
364 u64 lowest_nonlinear_ratio;
366 int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
370 nominal_freq = cppc_perf.nominal_freq;
371 nominal_perf = READ_ONCE(cpudata->nominal_perf);
373 lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf;
375 lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT,
378 lowest_nonlinear_freq = nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT;
381 return lowest_nonlinear_freq * 1000;
384 static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state)
386 struct amd_cpudata *cpudata = policy->driver_data;
389 if (!cpudata->boost_supported) {
390 pr_err("Boost mode is not supported by this processor or SBIOS\n");
395 policy->cpuinfo.max_freq = cpudata->max_freq;
397 policy->cpuinfo.max_freq = cpudata->nominal_freq;
399 policy->max = policy->cpuinfo.max_freq;
401 ret = freq_qos_update_request(&cpudata->req[1],
402 policy->cpuinfo.max_freq);
409 static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
411 u32 highest_perf, nominal_perf;
413 highest_perf = READ_ONCE(cpudata->highest_perf);
414 nominal_perf = READ_ONCE(cpudata->nominal_perf);
416 if (highest_perf <= nominal_perf)
419 cpudata->boost_supported = true;
420 amd_pstate_driver.boost_enabled = true;
423 static void amd_perf_ctl_reset(unsigned int cpu)
425 wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0);
428 static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
430 int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
432 struct amd_cpudata *cpudata;
435 * Resetting PERF_CTL_MSR will put the CPU in P0 frequency,
436 * which is ideal for initialization process.
438 amd_perf_ctl_reset(policy->cpu);
439 dev = get_cpu_device(policy->cpu);
443 cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
447 cpudata->cpu = policy->cpu;
449 ret = amd_pstate_init_perf(cpudata);
453 min_freq = amd_get_min_freq(cpudata);
454 max_freq = amd_get_max_freq(cpudata);
455 nominal_freq = amd_get_nominal_freq(cpudata);
456 lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
458 if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
459 dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
465 policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY;
466 policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY;
468 policy->min = min_freq;
469 policy->max = max_freq;
471 policy->cpuinfo.min_freq = min_freq;
472 policy->cpuinfo.max_freq = max_freq;
474 /* It will be updated by governor */
475 policy->cur = policy->cpuinfo.min_freq;
477 if (boot_cpu_has(X86_FEATURE_CPPC))
478 policy->fast_switch_possible = true;
480 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
481 FREQ_QOS_MIN, policy->cpuinfo.min_freq);
483 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
487 ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1],
488 FREQ_QOS_MAX, policy->cpuinfo.max_freq);
490 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
494 /* Initial processor data capability frequencies */
495 cpudata->max_freq = max_freq;
496 cpudata->min_freq = min_freq;
497 cpudata->nominal_freq = nominal_freq;
498 cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
500 policy->driver_data = cpudata;
502 amd_pstate_boost_init(cpudata);
507 freq_qos_remove_request(&cpudata->req[0]);
513 static int amd_pstate_cpu_exit(struct cpufreq_policy *policy)
515 struct amd_cpudata *cpudata = policy->driver_data;
517 freq_qos_remove_request(&cpudata->req[1]);
518 freq_qos_remove_request(&cpudata->req[0]);
524 static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
528 ret = amd_pstate_enable(true);
530 pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
535 static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
539 ret = amd_pstate_enable(false);
541 pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
546 /* Sysfs attributes */
549 * This frequency is to indicate the maximum hardware frequency.
550 * If boost is not active but supported, the frequency will be larger than the
553 static ssize_t show_amd_pstate_max_freq(struct cpufreq_policy *policy,
557 struct amd_cpudata *cpudata = policy->driver_data;
559 max_freq = amd_get_max_freq(cpudata);
563 return sprintf(&buf[0], "%u\n", max_freq);
566 static ssize_t show_amd_pstate_lowest_nonlinear_freq(struct cpufreq_policy *policy,
570 struct amd_cpudata *cpudata = policy->driver_data;
572 freq = amd_get_lowest_nonlinear_freq(cpudata);
576 return sprintf(&buf[0], "%u\n", freq);
580 * In some of ASICs, the highest_perf is not the one in the _CPC table, so we
581 * need to expose it to sysfs.
583 static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
587 struct amd_cpudata *cpudata = policy->driver_data;
589 perf = READ_ONCE(cpudata->highest_perf);
591 return sprintf(&buf[0], "%u\n", perf);
594 cpufreq_freq_attr_ro(amd_pstate_max_freq);
595 cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
597 cpufreq_freq_attr_ro(amd_pstate_highest_perf);
599 static struct freq_attr *amd_pstate_attr[] = {
600 &amd_pstate_max_freq,
601 &amd_pstate_lowest_nonlinear_freq,
602 &amd_pstate_highest_perf,
606 static struct cpufreq_driver amd_pstate_driver = {
607 .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
608 .verify = amd_pstate_verify,
609 .target = amd_pstate_target,
610 .init = amd_pstate_cpu_init,
611 .exit = amd_pstate_cpu_exit,
612 .suspend = amd_pstate_cpu_suspend,
613 .resume = amd_pstate_cpu_resume,
614 .set_boost = amd_pstate_set_boost,
615 .name = "amd-pstate",
616 .attr = amd_pstate_attr,
619 static int __init amd_pstate_init(void)
623 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
626 * by default the pstate driver is disabled to load
627 * enable the amd_pstate passive mode driver explicitly
628 * with amd_pstate=passive in kernel command line
631 pr_debug("driver load is disabled, boot with amd_pstate=passive to enable this\n");
635 if (!acpi_cpc_valid()) {
636 pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n");
640 /* don't keep reloading if cpufreq_driver exists */
641 if (cpufreq_get_current_driver())
644 /* capability check */
645 if (boot_cpu_has(X86_FEATURE_CPPC)) {
646 pr_debug("AMD CPPC MSR based functionality is supported\n");
647 amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
649 pr_debug("AMD CPPC shared memory based functionality is supported\n");
650 static_call_update(amd_pstate_enable, cppc_enable);
651 static_call_update(amd_pstate_init_perf, cppc_init_perf);
652 static_call_update(amd_pstate_update_perf, cppc_update_perf);
655 /* enable amd pstate feature */
656 ret = amd_pstate_enable(true);
658 pr_err("failed to enable amd-pstate with return %d\n", ret);
662 ret = cpufreq_register_driver(&amd_pstate_driver);
664 pr_err("failed to register amd_pstate_driver with return %d\n",
669 device_initcall(amd_pstate_init);
671 static int __init amd_pstate_param(char *str)
676 if (!strcmp(str, "disable")) {
678 pr_info("driver is explicitly disabled\n");
679 } else if (!strcmp(str, "passive"))
684 early_param("amd_pstate", amd_pstate_param);
686 MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
687 MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
688 MODULE_LICENSE("GPL");